Efficient Method for Error Detection and Correction in In‐Memory Computing Based on Reliable Ex‐Logic Gates

In‐memory computing using memristor‐based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high‐energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module‐enable signal and input‐checker bits.

DOI: 10.1002/aisy.202200341 In-memory computing using memristor-based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high-energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module-enable signal and input-checker bits.
impossible. As a result, the reliable memristive logic gate design should pursue the condition that is relied on the optimized region as closely as possible. The error can occur during the memristive logic programming and reading of the states, but the latter was ignored in this work because of its much lower probability than the former. While the term "logic operation" generally indicates logic gate programming and subsequent reading, it mainly indicates the logic gate programming in the following sections.
There are diverse memristive logic gates, and the nomenclature rule [17] of "Structure-N-n Function" in the previous study is used in this work. The numbers of logic inputs and memristor cells are represented by N and n, respectively. The types of structure include PM, APM, SM, ASM, and M denoted for "parallel memristors", "antiparallel memristors", "serial memristors", "antiserial memristors", and "a single memristor". If a series resistor is added, the letter "R" is added to the structure name. For example, the PMR-two-3NAND logic gate denotes three (n ¼ 3) parallel memristors with a series resistor that takes two (N ¼ 2) inputs to operate the NAND logic operation.
Combining a memristor with other memristors and resistors in series or parallel enables the conditional switching of the memristor depending on their initial states and circuit configuration. For instance, the stateful neural network proposed by Sun et al. [20] comprises three bipolar resistive switching memristors connected with a common node along with a series resistor that can implement 14 Boolean logic operations without altering the primitive circuit when a conditional voltage (V cond ) is applied to input memristors and driving voltage (V dd ) to the output memristor. This implementation revealed a possibility for an efficient method to implement combinational circuits, such as a 1-bit full adder, which can be implemented in two sequential steps with five memristors. However, selecting the desired state among the several possible states in multiple logic constraints without errors is challenging when variations are introduced. [21][22][23] Moreover, the applied voltage to a memristor higher than the optimized threshold voltage of a memristor, necessary to overcome the variation of a memristor, has a negative side effect of increasing the probability of hard breakdown of the memristor. This effect was quantified using the device stress factor. [24] Consequently, handling an error within the optimized threshold voltage is essential to increase the reliability of logic operations.
In the same vein, a new memristive error detection (ED) and correction module (EDCM) is proposed in this work to compensate for the error cases in logic gates by detecting and correcting the nonswitching and switching errors that may occur at the output memristor. It is worth noting that the memristive EDCM is different from the hamming error correction code (ECC), [25,26] where the error correction code is applied to check errors in the memory array, not the logic operations. Since the module operation must be reliable, the previously reported logic gates named ex-logic gates with the lowest device stress factor are used. [24] The proposed memristive EDCM consists of two ex-logic gates and a single memristor embedded in the PMR-two-3NOR and PMR-two-3NAND logic gates in the stateful neural network for the demonstration. After the logic operation, the moduleenable (ME) signal bit determines the possible error in the output bit and enables the module operations in EDCM. The operations convert the ME signal bit to the ED code (EDC) using inputchecker (IC) bits. Here, EDC is defined as a generated bit that can be used to detect an error in the output bit. When the error is detected from the generated EDC and output bit, EDCM provides an ED signal bit, in which ED ¼ "1" for the error case. Then, the EDCM corrects the error depending on the ED signal bit. This work also introduces an optimized method to ensure EDC generation and synchronous error correction to increase reliability and efficiency. Then, the feasibility of the EDCM is demonstrated by the SPICE simulation. Finally, the suggested memristive EDCM is compared with the previous EDCMs, and comparable performance was proven with a much minor device area penalty and higher functionality.
2. Variation-Aware Stateful Logic Gate of PMR-Two-3NOR and PMR-Two-3NAND Based on Stateful Neural Network The implementation of the stateful neural network proposed by Sun et al. considers device variation for stateful logic gates based on the McCulloch-Pitts neuron model [27] on a combined memristive structure. In this network, the summation of the components in the combined network with the step function results in the Boolean logic gates. A primitive circuit for the network is shown in Figure 1a. The memristors M 1t1 and M 2t1 are configured for two input bits, p and q, of the logic gate, and the output bit, r, is stored in the memristor M 3t1 . Here, the "M" means the memristor, and the two subscript numbers indicate the word line (WL) and bit line (BL) number of the specific memristor. In this notation of the memristors, the subscript t (or b ) means "top (or bottom)" of the BL. The electric signals are applied to WL 1t , WL 2t , and WL 3t , while the common-node voltage is applied to BL 1 . The magnitude of operation voltage (V dd ¼ jbV set j, where b > 1), which is applied to the WL 3t connected to the output memristor (M 3t1 in this case), is selected to be higher than that of the set voltage of the memristor (V set ) to enable conditional switching of the output memristor. However, the actual switching of the M 3t1 (output r) is modulated by the small V cond (jaV set j, where 0 < a < 1), which is applied to WL 1t and WL 2t , depending on the previously settled p and q values to the M 1t1 and M 2t1 . Such a conditional switching of the M 3t1 comprises the fundamentals of the logic gate operation. The a and b are the bias constants that need to be varied to achieve the desired logic function, such as NOR and NAND. For the primitive circuit shown in Figure 1a, the common-node voltage (V c ), which is the voltage of the BL 1 under the simultaneous application of V cond and V dd and the presence of the series resistor, can be found by solving Kirchhoff 's law. The derivation can be found in Section S1 of online Supporting Infortmation (SI).
V i and G i are the bias voltage to each node in the network and the conductance of the memristors (G i ¼ R À1 i Þ, respectively, where i corresponds to the p, q, r, and s (series resistor). The set transition (switching from the off-state to the on-state) of the output memristor occurs when jbV set À V c j ≥ jV set j. Substituting Equation (1) to this conditional switching equation (jbV set À V c j ≥ jV set j) results in the following equation.
The conductance of a memristor G on and G off was normalized to "1" and "0", respectively, to represent the input and output bits, which are either 1 or 0. For adding the tolerance to the device variation, G s value (G s ¼ R À1 s ) is selected to be ffiffi ffi 2 p G on , and a more detailed explanation of the determination of R s is included in Section S2 of the online Supporting Information. Then, Equation (2), which represents the conditional set condition, can be rewritten as Equation (4) by substituting Equation (3), where p and q are the normalized conductance of input memristors, and the detailed derivation is shown in Section S3 of the online Supporting Information.
Then, four input combinations can linearly be separated to achieve logic functions such as NOR pq and NAND pq , as shown in Figure 1b. The y-intercepts of the separation line (red line in Figure 1b) having a slope of À1 are selected to be þ1/2 and þ3/2 to achieve maximum tolerance to the device variation of PMRtwo-3NOR and PMR-two-3NAND gates, respectively. As a result, the appropriate a and b values for PMR-two-3NOR and PMRtwo-3NAND gates are summarized in Figure 1c.
Although the logic gate implementation considers the device variation by selecting the maximum distance between input combinations, it is insufficient to compensate for the actual variation in a memristor. In the previous works, [24,28] Au/Pt/Ti/TiO 2Àx / Pt/Ti memristors were fabricated to demonstrate logic gates. The fabrication methods are explained in the Experimental Section. The bipolar resistive switching memristor adopted in this work has an average V set of À1.625 V and V reset of þ0.718 V, as shown in the current-voltage curves in Figure 2a. The resistance distributions due to the device variation of the R off and R on for the 150 consecutive switching cycles are shown in Figure 2b. Although they apparently show uniform resistance distributions at a read voltage of 0.35 V, the V set has non-negligible variation, as shown in Figure 2c. The maximum allowable device variations in the PMR-two-3NOR and PMR-two-3NAND gates are found in the constraint plot, as shown in Figure 2d. Each line represents the voltage dropped by the output memristor when input combinations of a logic gate are given, represented by the two numbers and a gate type in the legend. For instance, "01NOR" stands for the case where the input memristors M 1t1 and M 2t1 , corresponding to the logic inputs p and q, are in R off (data "0") and R on (data "1") in the  www.advancedsciencenews.com www.advintellsyst.com PMR-two-3NOR gate. The black horizontal line represents the V set of a memristor, which means that the conditional lines above this black line indicate set switching of the output memristor. It should be noted that M 3t1 is always initialized to the offstate before the onset of the logic operation. Thus, the PMR-two-3NOR and PMR-two-3NAND gates require one (00NOR) and two (00NAND, 01(10)NAND) conditional lines, respectively, must locate above the set transition line, while all other conditional lines must locate below it. This condition is met in the shaded range. In consideration of variation, the optimized R s value of 150.8 Ω is selected for the demonstration in this work, represented by the vertical line in the same figure. Under this circumstance, the absolute minimum voltage applied to the output memristor is jÀ 1.767 Vj and jÀ 1.714 Vj for the NOR and NAND cases, respectively, which can induce the set switching. Thus, the variations of 0.142 V (jÀ1.767j À j À 1.625VjÞ for the PMR-two-3NOR gate and 0.089 V (jÀ1.714j À j À 1.625Vj) for PMR-two-3NAND gate are allowable. Although the one standard deviation of the V set (0.07 V) is lower than these allowable variations, the possible circuit noise may induce erroneous operation.
The following sections explain the suggested EDCM to handle these problems.

Limiting Error Cases and Requirements for ED and Correction Modules
Error handling starts with assessing the possible error cases in the logic operation. The resultant outputs depending on the input combinations of the PMR-two-3NOR and PMR-two-3NAND gates are summarized in truth tables in Figure 3a,b, where no stochastic variations of the memristors are assumed. However, the stochastic behavior of a memristor is likely to be involved in the combined structure during the logic operation. In that case, the possible error cases in PMR-two-3NOR and PMR-two-3NAND gates can be divided into three categories, as shown in Figure 3c,d, respectively. The error case I represents the case where the output memristor remained in R off (r 0 ¼ 0) even though it is supposed to switch to R on (r 0 ¼ 1). This occasion applies to input case 1 in the PMR-two-3NOR gate ( Figure 3c) and input cases 1, 2, and 3 in the PMR-two-3NAND gate ( Figure 3d). On the other hand, error case II occurs when the output memristor is unintentionally switched to R on , which can occur in input cases 2, 3, and 4 in the PMR-two-3NOR gate and input case 4 in the PMR-two-3NAND gate. In addition, the unintentional switching error of the input memristors is possible, which is error case III. The error probability within the input memristors can be minimized by selecting the bias constant a sufficiently less than 1. The largest constant a used between the PMR-two-3NOR and PMR-two-3NAND gates is 0.70, which is more than five standard deviations from the mean of V set in Figure 2c (μ set ) when the V c is zero, ðV set À 0.7V set Þ=σ set % 7. Consequently, the probability of the set transition of the input memristors can be sufficiently low. Next, the possible reset of the input states has to be considered since there is a possibility that the magnitude of the V c can be larger than the bias voltage, especially in the case when the memory window (M.W.), a ratio of R off to R on , is small. The following equation for the reset prevention can be derived considering the voltage difference between the V c and bias constants. The detailed derivation is shown in Section S4 of the online Supporting Information. www.advancedsciencenews.com www.advintellsyst.com Note that the V set is negative, whereas the V reset is positive. Thus, the bracket on the left side of the equation has to be negative to induce the reset switching of input memristors, given that the absolute value of V set is larger than V reset (Figure 2a). Since the M.W. is %100 (Figure 2b) in this work, this constraint will be satisfied in all operational ranges of V dd . Consequently, error case III is neglected since the set and reset switchings of the input memristors barely occur, meaning that the error handling can be limited to the output memristor, which are the error cases I and II. The probability of the error cases for each PMR-two-3NOR and PMR-two-3NAND gate, depending on V dd , is shown in Figure 4a,b, respectively, when V cond is determined by the given bias constant a of 0.5 and 0.7. Input case 4 in the PMR-two-3NOR gate (11NOR) and input case 1 in the PMR-two-3NAND gate (00NAND) has the highest success rate since it has the largest distance between the constraint line, as shown in Figure S1 in Section S5 of online Supporting Infortmation. Accordingly, two approaches can handle the errors for the output memristor. The first approach is handling only one error case by limiting V dd in either the operational region ① for error case I or region ③ for error case II. The other approach relies on the operation region ② to handle both error cases. Previous EDCMs for in-memory computing [29,30] used the first approach limiting the operation region to the region ①, but this approach sacrifices the success rate of the logic gates resulting in more frequent module operations, as shown in Figure 4c,d. Hence, the second approach is required since the highest success rate of the logic gates relies on the operational region ② with the optimized BER for each input case shown in Figure 4e. Thus, the requirements for the new EDCM can be summarized as follows. First, the module operations should handle both error cases, I and II, after the logic operation. Second, the module operations should remain within the memory; if the operations require data transfer from memory to peripheral circuits, the cost of the data transfer for ED and correction increases as the number of data increases, losing the advantages of in-memory computing. Third, the error rate of the module operations must be low enough not to add errors.

ED and Correction Modules with Ex-Logic Gates
The authors previously proposed reliable logic gates, named ex-logic gates, composed of APMR-two-2XOR and APMRthree-4XOR gates that can perform XOR logic operations with low device stress factor using the antiparallel bipolar resistive switching memristors. [24] The reliability of the logic gates can be analyzed using the memristive behavior model represented in Section S5 in online Supporting Information. The PMRtwo-3NAND and PMR-two-3NOR gates in the stateful neural network have less than 10% tolerance, whereas the APMRthree-4XOR gate has a %30% tolerance. Since the one standard Figure 4. The success rate of logic operations of a) PMR-two-3NOR and b) PMR-two-3NAND gates for error cases I and II at fixed conditional voltage of À0.813 and À1.138 V as a function of driving voltage, respectively. The region ① represents the region where error case I is dominated, whereas coexistence of the error cases I and II are presented in the region ②. Similarly, the error case II is dominated in the region ③. The average BER in c) PMR-two-3NOR and d) PMR-two-3NAND gates. The lowest BER is found at the optimized driving voltage of the À1.68 and À2.14 V for the PMR-two-3NOR and PMR-two-3NAND gates, respectively. e) The BER for each input case at the optimized driving voltage.
www.advancedsciencenews.com www.advintellsyst.com deviation of the threshold voltage of a memristor is 4.31%, more than three standard deviations of the mean can be considered negligible error rates for the APMR-three-4XOR gates compared to the PMR-two-3NAND and PMR-two-3NOR gates. The logic gates have the voltage form input bits and the resistance form output bits. Since the voltage form input bits are used, negating one input bit of the APMR-two-2XOR gate results in the APMRtwo-2XNOR gate. In addition, the proposed APMR-three-4XOR gate can cascade the output of the APMR-two-2XOR gate with a third input bit stored in the added memristor to obtain a three-input XOR logic operation. The ex-logic has a sufficiently low error rate, rendering it useful for EDCMs. The proposed memristive EDCM consists of two ex-logic gates and a single memristor, as shown in Figure 5a. The EDCM provides two signal bits, ME and ED, to the controller, as shown in Figure 5b, to improve the ED and correction efficiency, which will be discussed later. For demonstrating the memristive EDCM, the PMR-two-3NOR and PMR-two-3NAND logic gates are adopted, and the operation method is summarized in Figure 6. The proposed EDCM can be applied to both correct and error cases of the PMR-two-3NOR and PMR-two-3NAND gates. The more detailed algorithm, including a step-by-step bias scheme for all input cases, might be better understood through the videos included in the online SI. In this circuit structure, M 3t1 contains the output (r) of the given logic operation in a resistance form, where the two inputs (p and q) are stored to M 1t1 and M 2t1 in a resistance form by applying bias via WL 1t and WL 2t . When the EDCM operates, the r always becomes to have the correct values.
The principle of the algorithm is adapted from the parity code in signal transmission, which can be found in Section S7 of online Supporting Information for more detailed information. After the logic operation of the PMR-two-3NOR or PMR-two-3NAND gate is executed to the output memristor M 3t1 , the probability of the output bit having an error depends on the input case, as shown in Figure 4. When an error occurs in the output memristor, the error can be detected through the following equation.
P c is the parity bit of a logic gate having no error bit, and P 0 indicates the parity bit after the logic operation, which may contain an error bit. Since the possible error case is limited to the output memristor, the Equation (6) can be simplified to the  www.advancedsciencenews.com www.advintellsyst.com Equation (7) for the output bits. Since the correct result of logic gates, r c , can be used to detect an error in the other logic gates, r 0 , r c can be defined as EDC. However, ensuring the correct result of the selected logic gates requires other logic gates with higher reliability than the original logic gate. One of the methods to ensure the correct result of logic gates is to adopt a look-up table in the CMOS-based peripheral circuit. However, this method costs too much in data transfer and circuit complexity. Instead, in-memory sequential logic gates having low κ can be used. Although the sequential logic gates, such as the APMR-two-2XOR and APMR-three-4XOR in this work, have the cascading problem to be used as a main logic gate, combining the stateful logic gates relieves the problem while maintaining the reliability of the logic operation. [24] Therefore, the suggested EDCM in this work adopts the reliable ex-logic gate despite its sequential logic feature. The EDC can be generated using Equation (8).
The ME signal bit is defined as a signal bit indicating that the module operations are required, so the EDCM only operates when the ME signal bit is in a "1" state. Since the error rates of input case 4 in the PMR-two-3NOR gate and input case 1 in the PMR-two-3NAND gate are less significant, the ME signal bit becomes a "0" state to disable the EDCM preventing unnecessary module operations in the correct case. Hence, the PMRtwo-3NAND gate, for example, requires OR function (between input p and q) to generate the ME signal bit ("0") since input case 1 (00NAND) in Figure 4b has the lowest error rate in which the EDCM is not required. The OR function can be realized using the single-memristor logic gate, M-two-1(NAND, OR, RIMP, IMP) gate, which can be realized by applying fWL 4t g←T 1 , fBL 1 g←T 2 to the memristor initialized to "1" state, where T 1 and T 2 are q and p 0 , respectively (T ¼ T 1 T 2 ¼ qp 0 ). Similarly, the other possible ME signal bits can be defined in the same single memristor, as shown in Figure 7a.
The IC bit determines whether the number of "1" in the input bits is odd or even, which is similar to the input parity bit but different in application. It is used to convert the ME signal bit to EDC through the XOR operation, which can be realized using the APMR-two-2(XOR, XNOR) of the Ex-logic gate, as shown in Figure 7b. Since the BL 1 is shared by ME and IC circuits, they can be generated parallelly. However, it should be noted that the circuits for the ME and IC must be appropriately selected for the given logic gate. For example, the PMR-two-3NOR gate requires NAND pq and XOR pq to be the ME and IC circuits, respectively. The required ME and IC circuits for the other logic gates in the stateful neural network are summarized in Table S1, Supporting Information. The XOR logic operation between ME and IC bits using the APMR-three-4XOR gate results in EDC in M 41 , as shown in Figure 8a. Then, the XOR logic operation between the EDC and r 0 results in the ED signal bit in the M 41 memristor, according to the Equation (9). If the error has occurred in r 0 in the M 3t1 memristor, the result of ED would be "1". Since the location of the error is known, the error can be corrected by flipping the error bit by the following equation. ED ⊕ r 0 ¼ r c (10) Figure 7. a) Module enable signal bit generation using a single-memristor logic gate. b) IC bit generation using the APMR-two-2(XOR, XNOR) gate.
www.advancedsciencenews.com www.advintellsyst.com The XOR operation with "1" is the negation operation (flipping bit), so the ED bit can be used as an ECC, similar to EDC, to correct the r 0 . It should be noted that the ED bit is "1" when the error is detected. For a more precise understanding, the step-by-step operation of the error correction for the PMR-two-3NOR gate with error case I (Figure 3c) is described in the online Supporting Information Table S2, as an example. In this case, the p and q inputs may produce output r, (1,0,0,0), the correct output, or (0,0,0,0), the erroneous output. The generated ME (NAND pq ) and IC (XOR pq ) result in the EDC of (1,0,0,X). Then, the ED is (0,0,0,X) for the correct case, or (1,0,0,X) for the erroneous case, where "X" is the don't-care term since the module is disabled. Therefore, the ED⊕r 0 always produces (1,0,0,0), the correct output. The XOR logic operation between M 31 and M 41 memristors corresponds to the last step, that is, ED ⊕ r 0 . The APMR-three-4XOR gate offers additional merit to save the operational energy cost further by its specific property of the "1" ED bit, which could be either "1þ" or "1À". The basic Ex-logic gate unit comprises the upper and lower memristors with a common BL (Figure 5a). Therefore, when the upper (or lower) memristor switches on, it corresponds to "1þ" (or "1À") state. Also, the APMR-three-4XOR gate has eight possible input cases among the three inputs. The previous studies revealed that the logic operation of the APMR-three-4XOR gate changes the inputs for the second and eighth input cases. In contrast, the inputs in other cases remain intact, as shown in Figure S4 in Section S8 of the online Supporting Information. The two possible "1" states, "1þ" and "1À", of the Ex-logic gate allow for detecting the case when the input switching occurs. The second and eighth input cases result in a "1þ" state in the output memristor, M 41 , of the APMR-three-4XOR gate, and other input cases result in a "0" or "1À" state. In other words, when M 41 is a "1þ" state, the memristor M 3t1 is switched to a "1" state during the ED bit generation. Therefore, the input switching property of the second or eighth input cases of the APMR-three-4XOR gate can simultaneously correct an error in the M 3t1 memristor and generate the ED bit, named a synchronous correction. An additional error correction step is required for other input cases since the output memristor is unchanged. Thus, the ED bit can be used as a signal bit to determine whether the error correction step is required if the synchronous correction does not occur. After the correction, the module operations are finished, as summarized in Figure 8b.
Next, the suggested EDCM is verified by SPICE simulation of the PMR-two-3NOR and PMR-two-3NAND gate, where the TiO 2 -based bipolar resistive switching memristors are used (see experimental section for the details of the memristor). A modified Arizona state university resistive random access memory model of the memristor [31] based on the experimental current-voltage characteristic and statistical analysis is constructed for the demonstration, where the Gaussian distribution is considered in activation energy for vacancy generation for the V set distribution of the fabricated memristor. The proposed EDCM is demonstrated on logic operations of PMR-two-3NOR and PMR-two-3NAND gates based on the adopted model with the variation, as shown in Figure 9 and 10, respectively. After the logic operations, the error may or may not occur to the output memristor. Then, the ED and correction for the PMR-two-3NOR and PMR-two-3NAND gates can be demonstrated for each input. The black and red lines indicate the resistance of top and bottom memristors at the given location, respectively. Each number in the five different regions indicates the step number in the algorithm in Figure 6. Step 1 represents the logic operation of a target logic gate. The ME signal bits are activated in the M 4t1 memristor in step 2 for the input cases with the high probable error case. In parallel, the IC bit is generated in the M 51 memristor. In step 3, EDC is generated in the M 41 memristor for the input case where ME is activated. The error is successfully detected for each case since the M 41 memristor is "1" in step 4. When the M 4t1 memristor is "1", the synchronous error correction occurs in input case 1 in the PMR-two-3NOR gate and input cases 2 and 3 in the PMR-two-3NAND gate, and the module is deactivated. On the other hand, when the M 4b1 memristor is "1", the error is successfully corrected in step 5. Overall, the average steps to detect www.advancedsciencenews.com www.advintellsyst.com and correct an error in EDCM when the distribution of the input cases is uniform are three steps for the PMR-two-3NOR gate and 2.75 steps for the PMR-two-3NAND gate.

Comparison and Discussion
Previously, three EDCMs for in-memory computing gates were reported, namely, zero-counting module (ZCM), [29] odd-counting module (OCM), [29] and IMP EDCM. The ZCM is based on CMOS-based three-input NOR gates in the peripheral region, which can be applied to the NOR-type gates (3NOR, 2IMP, and 2NOT) for ED. Since the module operation is based on the NOR function by ensuring the nonzero bit for the correct operations, the applied bias to the logic gates is limited to the operational region ① in Figure 4 to handle the error case I. This results in a high initial BER of 72.2%. The high initial BER indicates the frequent correction operations of the correction modules, increasing the energy consumption and lowering the endurance of memristors. Moreover, the ZCM cannot be used to detect an error of non-NOR-type gates (3NAND, 3(R) NIMP, 3(R)IMP, 3OR, and 3AND). Instead, the OCM consisting of two three-input XOR gates and one two-input XOR gate is  www.advancedsciencenews.com www.advintellsyst.com required. The module operation is based on the XOR operation, ensuring that the total number of "1" of memristors is odd for the correct operations. However, a separate balance gate is required to modify all input combinations to have the odd number of "1". Depending on the target logic gate, the different balance gate is realized by the cascaded NOR-type stateful logic gates based on memristors. Since the realization of the balance gates is also vulnerable to errors, the ZCM is added to each cascaded step, resulting in a significant area cost of 324F 2 , assuming a single memristor and transistor take 4F 2 and 8F 2 , respectively, where F is the minimum feature size. Although the previous ZCM and OCM can be applied to various stateful logic gates using highly reliable transistors, adopting two different EDCMs and balance gates depending on the target logic gates can increase the complexity and latency of the large computing system. Besides, IMP EDCM proposed by Li et al. recently suggested the fully memristor-based EDCM. [30] Instead of using the CMOSbased modules, two sequences of the PMR-two-3NOR gate are used to detect errors in the PMR-two-2IMP gate. Then, the PMR-three-3OR gate is used to correct the erroneous output. Thus, the detection and correction can be done within the memory domain without requiring separate correction steps after the module operations. However, the method has some challenges. First, the high initial BER cannot be resolved since the error case is limited to case I. Plus, since the module operations are based on the stateful logic gates of having a relatively high device stress factor, the final BER is not 0% due to the possible errors in module operations. In addition, the IMP EDCM can only be applied to the PMR-two-2IMP gate.
On the other hand, the proposed memristive EDCM is based on the XOR logic operations with the five additional memristors to the logic gates, which can detect both the switching and nonswitching error of an output memristor (error cases I and II). Thus, the optimal bias voltage condition can be selected with the lowest mean error probability, resulting in the smallest initial BER of 0.75% for PMR-two-3NOR and 12.25% for the PMR-two-3NAND gates. Thus, low-energy consumption can be obtained for the proposed EDCM. The energy consumption depends on the input combinations and error cases, as represented in Figure 11a, for the logic operations without EDCM. The ED and correction result in the additional cost to energy consumption, as shown in Figure 11b. Concerning the average energy consumption of the logic operations, the EDCM takes a relatively small portion of 3.8% and 10.3% for PMR-two-3NAND and PMR-two-3NOR gates, respectively, as shown in Figure 11c.
The comparison between other EDCMs for in-memory computing gates is summarized in Table 1. Compared to other EDCMs, the average energy consumption is the lowest since the operational region relies on the optimized condition for the lowest initial BER of sequential logic gates and synchronous error correction. The area efficiency is improved by 75.8% and Figure 11. The energy consumption of the logic gates and the proposed EDCM. The energy per bit of a) logic operations of PMR-two-3NAND and PMRtwo-3NOR gate for each input case and b) the proposed EDCM depending on the error states. c) The average energy per bit for all input cases. NOR-type gates are NOR, IMP, NOT, and non-NOR-type gates are NAND, (R)NIMP, (R)IMP, OR, AND; b) The BER of the EDCMs are estimated based on the success rate described in the manuscript. For demonstration, ZCM for NOR gate is used, and ZCM þ OCM for NAND gate is used; c) The area of single transistor and memristor are assumed to be 8F 2 and 4F 2 , respectively. For ZCM and OCM, separate module for correction is required but not included in area cost since no specification is indicated in the manuscript.
www.advancedsciencenews.com www.advintellsyst.com 93.8% compared to the ZCM and ZCM þ OCM, respectively. Although the three additional memristors (%12F 2 area penalty) are required for the proposed EDCM compared to IMP EDCM, the proposed module can be applied to both NOR-type and non-NOR-type gates within the stateful neural network with lower-energy consumption. Despite the advantages of the proposed EDCM, the generation of ME and IC bits may require additional peripheral circuits for converting output bits when two input bits are the result of the cascaded logic gates. Designing the efficient peripheral circuit for the proposed EDCM would be further work but feasible using the multiplexers [32] or transimpedance amplifiers, [33,34] which are often used in the in-memory computing of vector-matrix multiplication. For instance, the two-input NOR operation for the two outputs of the cascaded logic gates can be achieved using transimpedance amplifiers with the same detection and correction sequence but a longer time, as shown in Figure S5 in Section S9 of online Supporting Information. The cost of the transimpedance amplifiers is not included in Table 1 since the other EDCMs, except IMP EDCM, require the amplifiers to transfer the read current of memristors to the transistors. Consequently, the proposed EDCM represents comparable performance in energy efficiency with a minor area penalty of five memristors and higher functionality than the previous EDCM.

Conclusion
During the logic operation in the stateful logic gates, an unintentional error can occur in the input and output memristors due to their variation in the state transition. Among them, errors in the input memristors can readily be suppressed by the appropriate selection of bias constant. However, the possible errors in the output memristor require an ED and correction module to operate the stateful logic circuit reliably. This work proposes the module in the five memristors consisting of two reliable ex-logic gates and a single memristor. The detection is based on the EDC generated from the logic operation between module-enable signal and IC bits using the APMR-two-2XOR gate. When a reliable EDC is generated, an error can be detected from the ED bit. Then, the error can be corrected by flipping the output bit using the APMR-three-4XOR gate. For efficiency during the module operation, the two signal bits of module-enable and error-detection are used in the detection and correction operations, respectively. The module-enable signal bit determines whether the module has to be enabled. Since one of four possible input combinations of a logic gate has a negligible error rate, the module is disabled by the module-enable signal bit. When the error is detected, the error-detection bit is generated to be either "1þ" or "1À" state. For the "1þ" state, the error can be corrected and detected simultaneously using the input switching property of the APMR-three-4XOR gate. Thus, the error correction is only conducted for the "1À" state, increasing module efficiency.
While the previous ED and correction modules limit the detectable error case to one, the proposed modules can detect both nonswitching and switching of an output memristor. More detection allows the selection of the optimized bias condition for the lowest BER in the output of logic gates, increasing energy efficiency by operating less number of module operations. Thus, an efficient method can be achieved in terms of functionality, latency, and area. The present work demonstrates the ED and correction for the stateful neural network using the appropriate module-enable and IC bits. The stateful logic gates with the modules can be embedded in large-scale logic computing chips, but other factors besides the stochastic behavior, such as sneak current, line resistance, and parasitic capacitance, must be considered. Although the ED and correction modules require additional steps and five memristors to the in-memory logic gate, the implementation is worth the cost to reduce the bit error rate and is feasible for the practical stateful logic technology. Next, the optimization in the circuit design, including the controller, may further extend the higher computation efficiency for practical implementation.

Experimental Section
The current-voltage curves of the memristor were achieved from the sample fabricated using the following method. The Au/Pt/Ti/TiO 2Àx /Pt/Ti memristor stack was fabricated on the SiO 2 /Si wafer. The 100 nm silicon dioxide (SiO 2 ) was grown by dry oxidation. The bottom electrode of 50 nm platinum (Pt) and 10 nm titanium (Ti) was deposited by electron beam evaporation. The Ti layer was used as an adhesion layer. The 35 nm TiO 2 thin film for the resistive switching layer was fabricated via radio frequency (RF) sputtering with 125 W RF power in 15 mTorr reactive working pressure with 20% O 2 and 80% Ar gas ambient at room temperature, using a 3" TiO target. Then, 100 nm Au and 50 nm Pt were deposited as top electrodes using electron beam evaporation. All electrodes were patterned by photolithography and followed by a lift-off process. The electrical measurement of the fabricated device was done using a semiconductor parameter analyzer (HP 4145B) to conduct the electroforming and current-voltage sweep. The bias voltage was applied to the top electrode, and the bottom electrode was grounded. The mathematical tool "MathWorks MATLAB" was used to calculate the optimized condition for logic operation. The analog circuit simulation tool was performed by "Synopsys HSPICE" and "Cadence Virtuoso".

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.