Integration of Neuromorphic and Reconfigurable Logic‐in‐Memory Operations in an Electrolyte‐Manipulated Ferroelectric Organic Neuristor

The rapid development of digital technology results in a tremendous increase in computational tasks that impose stringent performance requirements on next‐generation computing. Biological neurons with fault tolerance and logic functions exhibit powerful computing capacity when facing complex real‐world problems, which strikes the inspiration for the development of highly energy‐efficient brain‐like computing. Herein, a novel device architecture, an electrolyte‐manipulated ferroelectric organic neuristor, which emulates biological neurons to perform both neuromorphic and reconfigurable logic‐in‐memory operations in a single cell, is proposed. The interfacial coupling of ions and dipoles in the neuristor contributes to the tunable synaptic behaviors of short‐ to long‐term plasticity. Notably, by virtue of lateral capacitive coupling, the neuristor is effectively controlled by multiple in‐plane gates to achieve heterosynaptic plasticity. An artificial neural network exhibits robust recognition ability with high accuracy of 93.7% in speech recognition, further demonstrating the feasibility of the neuristor for neuromorphic computing. Additionally, reconfigurable logic‐in‐memory operations (OR and AND) are successfully demonstrated in a single device. Therefore, the devices shed new light on the development of more brain‐inspired computing systems in the era of big data.


Introduction
With the explosive growth of data-intensive tasks, conventional computing systems are insufficient to satisfy the increasing demand for stringent computational performance. [1][2][3] Human brain, which is composed of numerous neurons interwoven through synapses, is a sophisticated "biocomputer" that can process vast information in parallel with a high efficiency and an ultralow power consumption, which strikes the inspiration for the development of brain-like computing. [4,5] Note that biological neurons with fault tolerance and logic functions are the computational engines of the brain, enabling to independently perform a variety of computing tasks. [6][7][8][9][10] Recently, neuron-like devices that integrate neuromorphic and logic functions have attracted considerable attention since they can complete various computation tasks, especially spatial-temporal processing and logic operations, in a single device, which markedly reduces the computational time and space complexity. [11,12] However, the absence of memory function in these devices results in the ambiguous short-term plasticity (STP)/long-term plasticity (LTP) signals, and frequent data exchanges between computation and storage units incur inevitable cost in computing time and energy. [13][14][15] Consequently, in the vital stage of the development of brain-inspired computing systems, it is indispensable to explore novel neuron-like devices that integrate memory, neuromorphic, and logic functions within one single device.
In this study, we propose an electrolyte-manipulated ferroelectric organic neuristor with in-plane-gate architecture using ferroelectric polymers. By mimicking the functionalities of biological neurons, our neuristors achieve the integration of neuromorphic and reconfigurable logic-in-memory operations. A bimodal STP-LTP functionality is attained through the interfacial coupling of ions and ferroelectric dipoles. In particular, due to lateral capacitive coupling, the neuristor with multiple in-plane gates exhibits heterosynaptic plasticity. We demonstrate the feasibility of our device for neuromorphic computing through a speech recognition simulation. A high accuracy of 93.7% and robust recognition ability are achieved. Furthermore, our neuristor realizes reconfigurable logic-in-memory operations (OR and AND) in a single device. Therefore, our work holds important implications for developing highly energy-efficient computing systems in the future.

DOI: 10.1002/aisy.202200434
The rapid development of digital technology results in a tremendous increase in computational tasks that impose stringent performance requirements on nextgeneration computing. Biological neurons with fault tolerance and logic functions exhibit powerful computing capacity when facing complex real-world problems, which strikes the inspiration for the development of highly energy-efficient brainlike computing. Herein, a novel device architecture, an electrolyte-manipulated ferroelectric organic neuristor, which emulates biological neurons to perform both neuromorphic and reconfigurable logic-in-memory operations in a single cell, is proposed. The interfacial coupling of ions and dipoles in the neuristor contributes to the tunable synaptic behaviors of short-to long-term plasticity. Notably, by virtue of lateral capacitive coupling, the neuristor is effectively controlled by multiple in-plane gates to achieve heterosynaptic plasticity. An artificial neural network exhibits robust recognition ability with high accuracy of 93.7% in speech recognition, further demonstrating the feasibility of the neuristor for neuromorphic computing. Additionally, reconfigurable logic-in-memory operations (OR and AND) are successfully demonstrated in a single device. Therefore, the devices shed new light on the development of more brain-inspired computing systems in the era of big data.

Device Structure and Film Characterizations
Biological neurons can integrate and process all signals from different pre-synapses through synaptic connections. [12,16] By utilizing the communication mode, the human brain can effectively deal with complex real-world problems with fault tolerance and logic functions (Figure 1a). [17] To emulate biological neurons, devices based on an in-plane-gate configuration were fabricated (Figure 1b). The chitosan layer was deposited on a silicon (Si) substrate by spin-coating, and it exhibited good smoothness with a root-mean-square (RMS) roughness of %0.79 nm (Figure S1a, Supporting Information). Then, a poly(vinylidene fluoridecotrifluoroethylene) [P(VDF-TrFE)] film was prepared by the antisolvent-assisted crystallization technique. [18,19] The P(VDF-TrFE) layer with the thickness of %5.8 nm could be clearly distinguished on the chitosan layer ( Figure S1b,c, Supporting Information). The film with an RMS roughness of %0.91 nm could serve as an ideal platform for the preparation of a high-quality 2D organic semiconductor layer (Figure 1c). N,N 0 -bis(hexyl) naphthalene-1,4,5,8-tetracarboxylic acid diamide (NDI-C 6 ) and poly(methyl methacrylate) (PMMA) buffering layers were subsequently deposited on P(VDF-TrFE). According to our previous results, The PMMA buffering layer can smooth the surface of ferroelectric layer, suppress the gate leakage current by filling the voids in the P(VDF-TrFE), and reduce the polarization fluctuation at the channel/ferroelectric interface, which significantly enhances the charge transport. [20,21] The channel and ferroelectric layers were characterized by the X-ray diffraction (XRD) ( Figure S1d, Supporting Information). The XRD pattern of NDI-C 6 film exhibits a typical reflection peak at 2θ = 4.88°with a high intensity, indicating a good crystallization. [22] The reflection peak at 2θ = 19.6°represents the P(VDF-TrFE) film, showing a low peak intensity. [23] The ferroelectric properties were further characterized by piezoresponse force microscopy (PFM) and ferroelectric analyzer. We observed a typical butterfly-like amplitude shape and anticlockwise hysteresis with an %180°phase contrast, indicating that the P(VDF-TrFE) film possessed good ferroelectricity ( Figure 1d). [24,25] Moreover, a square with upward polarization was defined by scanning the grounded atomic force microscopy (AFM) tip with voltages of AE10 V applied to the ferroelectric film, exhibiting a clear phase shift ( Figure S2a,b, Supporting Information). According to the polarization-voltage (P-V ) hysteresis loops, stronger polarization of ferroelectric domains is clearly observed along with the increase of gate voltage, contributing to a larger hysteresis loop ( Figure S2c, Supporting Information). [26] It has been reported that a tradeoff between the polarization and leakage current commonly occurs during P-V loop measurements. Considering the issue, an Al 2 O 3 layer was introduced between P(VDF-TrFE) and bottom Si to suppress the interference from the leakage current. Then, transferred Au pads were used as source, drain, and gate electrodes (detailed fabrication process flow shown in Experimental Section). The gate-to-channel distances of Gate 1 , Gate 2 , and Gate m are 50, 50, and 100 μm, respectively. The length and width of the channel are 10 and 90 μm, respectively ( Figure S3, Supporting Information). Each gate electrode, representing a pre-synapse, could form a complete artificial synapse with the channel. Furthermore, cycle-to-cycle variations in the transfer curves exhibited negligible shifts in the threshold voltage and anticlockwise hysteresis (Figure 1e and S4a, Supporting Information). [27] Moreover, when the voltage was applied on different gates, the transfer characteristics of the devices showed almost overlapping curves, further demonstrating the operational stability of our neuristor ( Figure S4b, Supporting Information).

Working Mechanism and Synaptic Behaviors
A cross-sectional view of the neuristor with one in-plane gate is shown in Figure 2a. Note that the gate modulated channel conductance through two gate capacitors (C 1 and C 2 ) in series by the bottom conductive layer ( Figure S5a,b, Supporting Information). [28] The lateral capacitive coupling in the neuristors was studied (Figure 2b,c). Initially, the ions in chitosan were in equilibrium. When a small gate bias (V g ) was applied on the gate electrode, electric-double-layer (EDL) capacitance was induced by the accumulation of cations at the interface of P(VDF-TrFE)/ chitosan, and it played a dominant role in determining the channel conductance. After the spike voltage was removed, the cations gradually drifted back to equilibrium positions, resulting in a transient current relaxation or STP (left panel of Figure 2c). As V g increased, more cations could accumulate at the interface to generate a larger EDL capacitance, contributing to the polarization switching of partial ferroelectric dipoles and nonvolatile currents. The current could be maintained for a long time after removing the spike, which was regarded as typical LTP (middle inset of Figure 2c). At the moment, a prolonged spike width triggered more ferroelectric dipoles. Thus, the channel current could be maintained at a higher level, indicating that multilevel LTP could be obtained by increasing the spike widths (right inset of Figures 2c and S5c, Supporting Information). Then, we studied the changes in the channel current duration by applying gate voltages with different amplitudes (3-8 V) to further demonstrate the transition from STP to LTP (Figures 2d and S5d, Supporting Information). The devices exhibited STP induced by ionic relaxation when the spike voltage was below 6 V. The behavior of LTP, arising from ferroelectric polarization, could be observed as the spike voltage exceeded 7 V. Consequently, the neuristors achieved a bimodal STP-LTP functionality and multilevel LTP, which was crucial for the emulation of biological synaptic characteristics. Biological synapses are the bridges of communication between neurons, playing a pivotal role in information processing. [16] It is of great importance for neuromorphic computing to implement synaptic plasticity in electronic devices. Therefore, we explored the synaptic behaviors of the neuristors. In our experiments, gate voltage simulated pre-synaptic input and the channel current was considered as excitatory post-synaptic current (EPSC). In biology, paired-pulse facilitation (PPF) could illustrate the change in EPSC in response to two consecutive spikes, representing typical short-term synaptic plasticity. [29] Our devices mimicked PPF behavior by applying two successive pre-synaptic spikes (5 V, 50 ms) (Figure 2e). If the time interval of the two spikes was shorter than the relaxation time of the ions, some ions evoked by the first spike could not return to their equilibrium positions before the arrival of the second spike. In this case, the ions triggered by the second spike were augmented and enhanced the channel conductance due to the presence of residual ions. [12] The PPF ratio is the ratio of the second EPSC (A 2 ) to the first EPSC (A 1 ). The fitting curve of the time intervaldependent PPF ratio (PPF ratio versus Δt, as shown in the inset of Figure 2e) followed a biexponential equation [30] PPF ratio where Δt is the time interval between the pair of spikes, τ 1 and τ 2 are the characteristic relaxation times of the two phases, C 1 and C 2 are the initial facilitation values of the rapid and slow phases, respectively. We extracted C 1 = 0.427, C 2 = 0.128, τ 1 = 137 ms, and τ 2 = 2478 ms by fitting Equation (1). The obtained short and long relaxation times were similar to those in biological synapses. The PPF behaviors demonstrated the time-dependent plasticity characteristics of our neuristors.
Another synaptic behavior related to information processing is called spike-rate-dependent plasticity. [31] A series of pre-synaptic trained spikes with different frequencies (1, 2, 5, 10, 13, and 20 Hz) were applied on the gate to evaluate the EPSC. Each stimulus train contained 10 consecutive spikes with identical amplitudes and widths (4 V, 50 ms) (Figure 2f ). The gain of EPSC is defined as A 10 /A 1 , where A 1 and A 10 denote the EPSC after the first and tenth spike stimulation, respectively. Notably, the gain increased from 1.05 to 2.29 with increasing frequency. The gain was plotted as a function of spike frequency (inset in Figure 2f ), which exhibited high-pass filter characteristics. The LTP and long-term depression (LTD) characteristics of a neuromorphic device are regarded as the most crucial functions for the realization of neuromorphic computing. Therefore, we studied the LTP/LTD behaviors of our neuristors by adjusting the excitatory/inhibitory spike sets. The devices exhibited optimum performance regarding their numbers of conductance states (25), dynamic ranges (%520 pS), power consumption level (each excitatory spike of %14 pJ), and nonlinearity (1.18) when the excitatory spikes with 7 V of amplitude and 25 ms of duration were applied (see details in Experimental Section and Figures S6-S8, Supporting Information). [32,33] A statistical study of LTP/LTD was performed, and the results exhibited relatively reliable conductance modulation with slight offset (Figure 2g). www.advancedsciencenews.com www.advintellsyst.com In biological systems, an individual neuron contains numerous synaptic connections. The synaptic activity between a pair of pre-and post-neurons can be modulated by another synapse. So-called heterosynaptic behavior has been widely observed in biological nervous system and considered as an important function for sensory perception, associative learning, and spatiotemporal information processing. Advanced neuromorphic devices with multiple terminals or physical mechanisms are widely utilized to mimic the heterosynaptic behavior. [34,35] By virtue of effective gate capacitor coupling, our devices with multiple inplane gates could simulate biological neurons to perform computing tasks in a single cell (Figure 3a). Heterosynaptic plasticity can be achieved by integrating stimuli from different gates. By applying voltage spikes on one gate, the neuristor could give a current output with a frequency consistent with that of the input voltage ( Figure 3b). Specifically, when two voltage spikes with different frequencies were applied to two gates simultaneously, the channel current was comparable to the superposition of the currents resulting from a bias voltage applied to two individual gates (Figure 3c). We found that the neuristor received stimuli from two gates and generated a current with two frequencies corresponding to those from the two gates through the Fourier transform ( Figure 3d). In addition, we studied the channel current when the two inputs were identical ( Figure S9, Supporting Information). The enhanced EPSC could be clearly observed, which could be considered as spatial PPF. Therefore, the realization of heterosynaptic facilitation in our devices indicates their capability to process spatiotemporal information.

Neuristor for Neuromorphic and Reconfigurable Logic-in-Memory Operations
The ability to recognize objects through vision and hearing is a critical function of human beings. We fabricated a simulated neural network to demonstrate the feasibility of the neuristors for neuromorphic computing. For the simulation task, the free spoken digit dataset with 2400 training and 600 inference audio files was prepared. The audio files, including different people and numbers, were classified into 60 categories (Table S1, Supporting Information). Additionally, the audio files with different signal-to-noise ratios (SNRs) (20 and 0 dB) were recognized and classified to verify the robustness of the speech recognition systems ( Figure S10, Supporting Information). During the speech processing stage, the time domain signals were converted into Mel spectra through a series of treatments (Figures 4a and S11, Supporting Information). Then, we defined a single-layer fully connect artificial neural network (ANN) containing 1200 input neurons, 60 output neurons corresponding to 60 categories of the audios (Figure 4b). The detail information about the process of speech processing and simulation is presented in Experimental Section. Mel spectra were fed into ANN for training and learning. Figure 4c exhibits the architecture of the hardware neural network comprising the neuristors, emulating the consensual neuron-synapse structure in the brain. During the simulation, we trained three neural networks for recognizing audio signals containing different noise levels through 200 training epochs (Figure 4d). To match the available www.advancedsciencenews.com www.advintellsyst.com conductance with trained weights, the square mapping error (SME) was utilized as the mapping function SME ¼ min where λ is the mapping coefficient, G is the differential conductance, and W is the trained weight. The optimal λ minimizing SME was introduced to complete the mapping process. [36,37] As shown in Figure 4e, the maximum recognition rate was 93.7% for the raw audio based on the LTP/LTD behaviors of our neuristor. In the noisy environment, the recognition rates comparable to the trained results could reach 90.5% (SNR = 20 dB) and 83.5% (SNR = 0 dB), indicating the robustness of the ANN in speech recognition applications. Our neuristors successfully demonstrated the potential for neuromorphic computing.
Logic-in-memory operations are of great significance for building highly energy-efficient computing systems that perform reasoning tasks. In particular, the achievement of logic-in-memory operations at the individual device level has great potential to process massive amounts of data with a high-speed stream. Ferroelectric materials possess nonvolatile characteristics, high switching speed, and ferroelectricity with ultralow energy consumption, which is an ideal candidate to build devices integrating memory and computing function. [26,[38][39][40][41] Notably, the physical properties of the neuristor inspired by biological neurons are not limited to be applied in neuromorphic computing.
Logic-in-memory operations can be performed employing a single neuristor due to the multi-terminal architecture and nonvolatile ferroelectric polarization, which surpasses the performance of conventional logic devices. As a logic-in-memory device, the retention characteristic of the channel current was first explored by applying spikes (10 V) with different widths (0-400 ms) (Figure 5a). Note that for ferroelectric materials with thicknesses of several or tens of nanometers, the diminished long-range Coulomb coupling and strengthened depolarization field can lead to ferroelectric instability. [42,43] This phenomenon could be found in the ferroelectric transistors based on silicon oxide substrates ( Figure S12, Supporting Information). Notably, benefiting from the ions in chitosan coupling with ferroelectric dipoles at the interface, our neuristors exhibited multilevel storage capabilities and retention times of 10 3 s, laying the foundation for the realization of logic-in-memory operations. To exclude the influence of electrochemical doping on memory function, we fabricated neuristors without ferroelectric layer or with a non-ferroelectric poly(vinylidene fluoride) replacing the ferroelectric P(VDF-TrFE) layer, which all exhibits transient relaxation behavior (Figures S13 and S14, Supporting Information). Figure 5b presents a schematic of the neuristor for logic operations, where Gate 1 and Gate 2 serve as the input terminals, and Gate m serves as the modulatory terminal. Logic inputs with values of 0 or 1 indicated 0 or 10 V (100 ms), respectively. The post-synaptic current was measured as the logic output represented by 0 (low-level current) or 1 (high-level current). www.advancedsciencenews.com www.advintellsyst.com By using our neuristors instead of conventional logic devices, the primary logic-in-memory operations (OR and AND) of an integrated circuit can be realized in a single device. The logic behaviors of the devices were studied under different modulation voltages. When V G,m was 0 V, the channel current was mainly controlled by input terminals, similar to double-gate logic devices. Either Gate 1 or Gate 2 could generate the accumulation of sufficient cations under the channel to induce ferroelectric polarization, enabling the switching of the neuristor from the off state (%10 À12 A) to on state (%10 À9 A) and generating a nonvolatile current. Hence, a single device could provide a logic function of OR (Figure 5c). Note that the OR logic function could be switched to an AND logic function by applying a negative voltage (-5 V) to the Gate m (Figure 5d). Such an interesting phenomenon could be attributed to the fact that the negative V G,m neutralized the influence of a single input terminal on the channel. If any input terminal (V G,1 or V G,2 ) delivered a high input (1), the negative V G,m attracted cations and reduced the accumulation of cations under the channel. This phenomenon resulted in a transient channel current relaxation, indicating that the device was always in the off state. Only when the two logic inputs were 1, more cations could accumulate under the channel to induce the polarization switching of ferroelectric dipoles and nonvolatile current (on state). Therefore, reconfigurable logic-in-memory operations (OR and AND) can be achieved in the same device with effective modulation of Gate m , which further improves the computational performance of electronic devices. Consequently, the neuristor successfully demonstrates the integration of neuromorphic computing and logic-in-memory operations, presenting promising application prospects in the development of high-performance computing systems. www.advancedsciencenews.com www.advintellsyst.com

Conclusion
In summary, we have demonstrated the integration of neuromorphic and reconfigurable logic-in-memory operations in our organic neuristors. The structure and functionality of biological neurons are successfully emulated based on the multiple in-plane-gate structure. Our devices exhibit tunable synaptic behaviours from STP to LTP by combining ionic relaxation and ferroelectric dipole polarization. Moreover, by taking full advantage of lateral capacitive coupling, heterosynaptic plasticity is achieved in our device with multiple gates. We further demonstrate the feasibility of our neuristor for neuromorphic computing by the speech recognition simulation. A high recognition rate of 93.7% and robust recognition capability are obtained. In addition, we achieve the reconfigurable logic-in-memory operations (OR and AND) in a single unit. Therefore, these satisfactory results present a bright future for the development of more brain-like computing systems that integrate data storage, neuromorphic computing, and logic operations.

Experimental Section
Fabrication Process Flow of the Electrolyte-Manipulated Ferroelectric Organic Neuristor: The n-type heavily doped Si substrate was treated with UV ozone for 5 min. Then, chitosan solution (2 wt%) was spin-coated on Si at 500 rpm for 10 s and at 2000 rpm for 20 s, and the sample was baked at 50°C for 10 min under ambient conditions. P(VDF-TrFE) (the ratio between VDF and TrFE was 70:30) was dissolved in a mixture of N,N-dimethylformamide and the antisolvent p-anisaldehyde (%5 mg mL À1 ). Then, a droplet of the P(VDF-TrFE) solution was drop-cast onto the sample. A mechanical pump with a pumping speed of %7 L min À1 generated airflow that dragged the droplet for rapid movement on the sample. An ultrathin P(VDF-TrFE) film was formed within several seconds. We dissolved NDI-C 6 (0.5 wt%) and PMMA (0.1 wt%) in a mixed solvent of anisole (98.9 wt%) and p-anisaldehyde (0.5 wt%). The NDI-C 6 film was deposited on the surface of P(VDF-TrFE) as a conducting channel for the neuristors under ambient conditions by using the antisolvent-assisted crystallization method mentioned earlier. Finally, Au pads with thicknesses of approximately 100 nm and sizes of 100 Â 80 μm were transferred onto the sample as the gate, source, and drain electrodes.
Characterizations and Electrical Measurements of Electrolyte-Manipulated Ferroelectric Organic Neuristor: For regular AFM and PFM, characterizations were performed with an Asylum Research Cypher scanning probe microscope under ambient conditions. P-V hysteresis loops were performed with a PREMIER II ferroelectric analyzer. XRD measurements were performed by D/MAX-uL TIMA3 X-ray diffractometer. Electrical measurements were taken with a semiconductor parameter analyzer (Agilent B1500) in a closed-cycle cryogenic probe station with a vacuum condition of 10 À2 Torr. The device was placed on a slide (%1 mm thick) to insulate it from the metal substrate while performing electrical measurements.
Power Consumption and Nonlinearity Calculation: The power consumption is directly proportional to the spike width and drain current values, which could be expressed as follows where U d (1 V) is the drain voltage, I d is the current flowing through the drain, and t is the spike width applied on the gate. We calculated the nonlinearity value by normalizing the measured curve. The nonlinearity value of the normalized curve was calculated using the following equation where G is the conductance value, P is the number of applied spikes, A p is a parameter representing nonlinearity, and B is a fitting constant used to normalize the conductance range. The A p value was extracted from the experimental data using Origin. Detailed Flow of Speech Processing: First, the audio files were transformed into time domain signals. The second step was to apply a preemphasis filter on the time domain signals to amplify the high-frequency region. After pre-emphasis, we split the signal into short-time frames with frame sizes of 20 ms. After slicing the signal into frames, we applied a Hamming window to each one. Then, we conducted short-time Fourier transform on each frame to obtain the frequency spectra and computed the power spectra. The final step to computing filter banks was to apply triangular filters. After applying the filter banks to the power spectra of the signal, we obtained the Mel spectra, which could be used for recognition and classification. All the aforementioned methods were implemented in Python.
Simulation of Speech Recognition Process: The entire simulation process involved loading the dataset, training the neural network, mapping the weights, and testing the mapped network. We uploaded the image dataset that was converted from the audio files and trained the neural network in Python. Then, we extracted the trained weights and mapped them to differential conductance values with the SME function. When we obtained the minimum value of the SME through the optimal mapping coefficient λ, we plugged λ into the SME function to map the weights and obtained the mapped network by replacing the trained weights with the mapped ones. Afterward, the simulation was completed by uploading the test dataset. The process of mapping weights was implemented by MATLAB, but the other processes were performed in Python.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.