Analog Ion‐Slicing LiNbO3 Memristor Based on Hopping Transport for Neuromorphic Computing

Inspired by human brain, the emerging analog‐type memristor employed in neuromorphic computing systems has attracted tremendous interest. However, existing analog memristors are still far from accurate tuning of multiple conductance states, which are crucial from the device‐level view. Herein, a reliable analog memristor based on ion‐slicing single‐crystalline LiNbO3 (LNO) thin film is demonstrated. The highly ordered LNO crystal structure provides a stable pathway of oxygen vacancy migration, which is contributed to a stable Mott variable‐range hopping process in trap sites. Excellent analog switching characteristics with high reliability and repeatability, including long retention/great endurance with small fluctuation (fluctuated within 0.22%), a large dynamic range of two orders of magnitude, hundreds of distinguishable conductance states with tunable linearity, and ultralow cyclic variances for multiple weight updating (down to 0.75%), are realized with the proposed memristor. As a result, a multilayer perceptron with a high recognition accuracy of 95.6% for Modified National Institute of Standards and Technology dataset is realized. The proposed analog memristive devices based on ion‐slicing single‐crystalline thin films offer a novel strategy for fabricating high‐performance memristors that combined linear tunability and long‐term repeatability, opening a novel avenue for neuromorphic computing application.


Introduction
The rapid development of artificial intelligence (AI) applications, such as natural language processing, [1] data-intensive image processing, [2] and big data analysis, [3] desires continuous hardware progress in a high-speed and energy-efficient manner.However, the conventional computing paradigm with von Neumann architecture leads to high energy consumption and latency due to data transfer between the separated memory unit and the processing unit, which is called the "memory wall". [4]he neuromorphic computing architecture, inspired by human brain, has been considered as a promising computing paradigm for breaking this bottleneck. [5,6]ecently, the emerging analog-type memristor-based in-memory architecture can store information in the form of multilevel conductance states and closely resembles the plasticity of biological synapses, which have been widely demonstrated as a natural candidate to implement the neuromorphic hardware architectures. [7,8]n a memristive neuromorphic computing system, the key switching characteristics of analog memristor, including large dynamic range, multilevel conductance states, weight update linearity and symmetry, and spatiotemporal variability with fluctuation, are crucial to system performances. [8,9]A dynamic range is the ratio between the maximum conductance (G max ) and minimum conductance (G min ), which generally represents the mapping capability of the weight in algorithms to the device conductance. [10]The multilevel states refer to the intermediate conductance states available within the dynamic range and more multilevel states (e.g., over hundreds of levels) are expected to translate into better learning abilities of the memristive neural network. [8]However, only limited improvements have been made for a considerable dynamic range with sufficient intermediate states, showing a dynamic range typically less than 10 in the analog switching region. [7][13] In this case, poor linearity and symmetry which are associated with internal dynamics in memristors are inevitable. [7,14]Hence, the memristor with a linear multiple conductance update and a large dynamic range is yet highly challenging to implement. [15]In addition, low spatiotemporal variability with sufferable fluctuation is also a key index for the implementation of memristive neural network. [8,16]owever, the existing analog memristors still suffer from large device and cyclic variations, which significantly decreases the precision of weight updating. [9,17,18]For example, the migration of oxygen vacancies (V o s) or metal ions in a memristor based on amorphous switching oxides is stochastic due to a large number of disorders and defect clusters in amorphous oxides. [10,19,20]nfortunately, these intrinsically random defects are formed unavoidably during common oxide film growing processes, such as layer deposition and magnetron sputtering. [21]erein, we prepared a high-quality single-crystalline LiNbO 3 (LNO) thin film via crystal ion-slicing (CIS) technique. [22][24] LNO crystal is a trigonal system of ilmenite type, in which oxygen octahedra are stacked in the form of coplane to form stacks, and further connected in the form of octahedral coedge to form crystals.The niobium atoms (Nb) and lithium atoms (Li) are then packed into these oxygen octahedra at intervals (as shown in Figure S1, Supporting Information). [25,26]Such stable crystal structure provides favorable conditions to achieve uniform analog switching. [27,28]urthermore, in order to modify device switching characteristics, we conducted Ar þ beam irradiation to deliberately introduce a V o -enriched layer as the defect reservoir. [29]32] In this work, we designed and fabricated a reliable analog memristor by using the 30 nm ion-slicing single-crystalline LNO thin film.The highly ordered and periodic lattice arrangement of the ion-slicing LNO layer provides a stable pathway of oxygen vacancy migration from the defect reservoir, thus promoting a stable electron hopping process.Thanks to this, the proposed LNO memristor exhibits extremely stable analog switching characteristics.Long retention/great endurance with small fluctuation, large dynamic range with tunable linearity in conductance update, and ultralow cycle-to-cycle variances for multiple conductance states are realized with the proposed memristor.Furthermore, a multilayer perceptron (MLP) with a high recognition accuracy of 95.6% for the Modified National Institute of Standards and Technology (MNIST) dataset was realized, which is comparable to a simulation baseline of 95.9%.

Reliable Switching Characteristics of the Ion-Slicing LNO Memristor
Figure 1a illustrates the fabrication process of the ion-slicing LNO memristor.A buried damaged layer was created in a 500 μm-thick Z-cut single-crystalline LNO wafer via high-energy He þ deep-ion implantation.After implantation, a Cr/Pt/Cr (10/ 100/30 nm) multilayer, as the bottom electrode, was sputtered on the implanted wafer.Then, SiO 2 bonding layers (about 2 μm) were deposited on the implanted wafer and another pristine single-crystalline LNO wafer (as substrate).After this, the two single-crystalline LNO wafers were directly bonded together at room temperature, and the exfoliated LNO layer was split.Thus, a typical thickness (about 300 nm) of the single-crystalline LNO thin film was fabricated after high-temperature thermal annealing and fine chemical mechanical polishing (CMP).And then, the single-crystalline LNO thin film was further irradiated by Ar þ beam with an irradiated angle of 0°(θ = 0°).Due to the etching effect of Ar þ beam irradiation, the thickness of LNO thin film reduced from 300 to 30 nm.At last, the memristive device with a structure of Au/LNO/Cr/Pt/Cr was formed after sputtering the Au top electrode with a thickness of 200 nm (inset of Figure 1b; for more details about CIS and Ar þ beam irradiation, see Experimental Section).
Figure 1b presents the typical electroforming process and consecutive I-V sweeps for the LNO-based devices.After electroforming (V forming < 3 V), the device shows analog switching behavior.For comparison, the device current of pristine devices based on 300 nm LNO thin film (without irradiation) is very low (<10 À9 A), and there is no resistive switching behavior in spite of the sweeping voltage up to 30 V (Figure S2, Supporting Information).This indicates that the pristine ion-slicing single-crystalline LNO layer has high dielectric property (resistivity = 2.6 Â 10 11 Ω cm, measured at 0.5 V).On the other hand, undergoing Ar þ beam irradiation enables the device to acquire switching characteristics and significantly reduces the operating voltage.Figure 1c plots the endurance property of the LNO memristor.Results show that the reliable endurance characteristic is maintained over 5 Â 10 5 cycles.More detailed cyclic switching analyses are plotted in Figure 1d and S3, Supporting Information.The cyclic conductance states demonstrate that the device effectively switches in every cycle without stuck at any state.Furthermore, ultrasmall stochastic fluctuations change within 0.22% (4.13 AE 0.04 μS) for low resistance state (LRS) and a value of 0.051 AE 0.015 μS for high resistance state (HRS) (Figure S3, Supporting Information), indicating the device possesses reliable switching characteristics.In terms of retention performance, the device outstands in the data retention performance over 27.7 h at room temperature (Figure 1e).More importantly, the conductance with only 0.74% decay process undergoes about 16.7 h (about 60 000 s) after programming the device to a high conductance state (i.e., LRS), and then it remains stable without any degradation (Figure 1f ).Hence, based on above quantitative analysis, it is reasonable to speculate that the device retention lifetime at room temperature can be up to 10 years (Figure S4, Supporting Information).Besides, the high reliability at multiple conductance levels (16 distinguishable states) of LNO memristor was also demonstrated for weight updating in artificial neural network (Figure 4h), which is discussed later.

Microstructure and Chemical Composition Analysis of the Ion-Slicing LNO Memristor
In order to reveal the microstructure, interface, and crystal composition of the ion-slicing single-crystalline LNO thin film, a series of material characterizations are performed on films after subjecting them to Ar þ beam irradiation.Figure 2a displays the cross-sectional transmission electron microscopy (TEM) image of the LNO memristor.The memristor is configured in a vertical Au/LNO/Cr/Pt/Cr structure, in which a 30 nm LNO thin film is used as the switching layer.The scanning transmission electron microscopy (STEM) image and energy-dispersive X-ray spectroscopy (EDS) in Figure S5, Supporting Information, further confirm the memristor structure.For investigating the influence of Ar þ beam irradiation, an atomic force microscopy (AFM) study of the surface topography is conducted.Figure 2b,c illustrates the 2D and 3D surface topography of the pristine LNO thin film (without irradiation) and irradiated one, respectively.In terms of pristine LNO thin film, the values of root mean square (RMS, R q ) and mean value roughness (R a ) are 0.298 and 0.246 nm, manifesting the highly planar surface after finer chemical polishing process.It is worth noting that the fine scratches are left by polishing particles (Figure 2b).After Ar þ beam irradiation, the LNO surface topography becomes smoother (Figure 2c).Smaller values of R q (0.219 nm) and R a (0.186 nm) indicate that the irradiation process reduces overall surface roughness.Furthermore, the detailed height profile also shows that Ar þ beam irradiation reduces peak-to-valley height values (R y ) (Figure 2d).The surface topography of more samples confirms this flattening effect (Figure S6 and S7, Supporting Information).Notably, the ultrasmall R q , R a , and R y values are close to the interatomic distances of LNO single crystals where Nb-O is 2.11 Å, Li-O is 2.24 Å, and O-O is 2.72 Å. [33,34] A uniformly smooth surface enables the formation of homogeneous interfaces of metal-semiconductor contact, whether it forms Ohmic contact or Schottky barrier, which helps regulate the resistive switching characteristics. [35,36]Furthermore, it also contributes to reducing the spatiotemporal variations of the device switches driven by a uniform electric field, especially for conductive-bridge memristors. [37,38]urther, to visualize the interfaces of LNO layer and metal electrodes, we performed a high-resolution TEM imaging of the Ar þ -irradiated LNO-based devices.As shown in Figure 2e, a uniform amorphous LNO layer is formed at the top electrode interface (Au/LNO interface, compared with pristine device, i.e., without irradiation (Figure S8, Supporting Information)).The thickness of the amorphous layer is about 4 nm and the interface between the amorphous and preserved monocrystalline LNO is sharply defined.Two well-defined lattice planes observed in the monocrystalline LNO region can be ascribed to lattice spacing of 0.23 and 0.26 nm, corresponding to the (006) and (110) planes of the rhombohedral phase of LNO, which indicates a good single-crystalline feature after irradiation (inset of Figure 2e).The lattice fringes in the fast Fourier transform, which derives from the high-resolution TEM image, further verify the welldefined amorphous LNO layer and monocrystalline LNO layer (inset of Figure 2e).In addition, the clearly defined bottom electrode interface (LNO/Cr interface) is also displayed in Figure 2f.More devices randomly selected on the wafer possess uniform interface structures, including uniform amorphous LNO layer and well-defined top/bottom electrode interfaces, as well as amorphous/monocrystalline interfaces (Figure S9, Supporting Information).
The chemical composition of the LNO thin films without/with irradiation was further investigated by X-ray photoelectron spectroscopy (XPS) (Figure 2g,h and S10, Supporting Information).For pristine LNO sample, an unambiguous doublet peak at 207.11 and 209.82 eV (Figure 2g) is ascribed to Nb 5þ 3d 5/2 and Pd 5þ 3d 3/2 with a peak spacing of %2.7 eV and intensity ratio of 0.67.This result indicates that ion-slicing LNO thin film maintains high-quality single-crystalline feature without other mixed valence compounds.However, the appearance of two new doublet peaks at 204.59/207.30eV and 205.71/208.42eV (Figure 2h) after irradiation implies the formation of Nb 4þ and Nb 2þ in the suboxides, i.e., oxide reduction. [39]Such contribution of lower Nb valences also can be verified by the O 1s spectrum (Figure S10c,d, Supporting Information) where a new peak at 531.89 eV is formed associated with V o s.Peak assignments for the fitted XPS spectra indicate that the amorphous layer-enriched V o s is achieved under Ar þ beam irradiation, which corresponds to n-type doping and for regulating device switching characteristics (Table S1, Supporting Information).Based on above analysis, it manifests that the CIS technique and Ar þ beam irradiation process used in this work are stable and reliable, and can yield a unique structure of the memristive layer in which a preserved single-crystalline layer as the bulk layer and a defect layer as the modified interface.

Conduction Mechanism Analysis of the Ion-Slicing LNO Memristor
To understand especially the interplay of such bulk layer and modified interface on the conduction mechanism of Ar þ -irradiated ion-slicing LNO memristor, we carried out temperature-dependent I-V measurements in a wide temperature range (80-315 K). Figure 3a,b shows the semilogarithmic current density-voltage ( J-V ) plots of HRS and LRS under positive sweeps, respectively.The J-V properties show that device current is related to both temperature and electric field intensity, and the trajectory transition occurs under different temperature regions, indicating a distinct conduction crossover (Figure 3a).In order to decipher device switching mechanisms, we evaluated the possible mechanisms of both interface-(or electrode-) limited conduction mechanisms and bulk-limited conduction  S11a, Supporting Information). [40]Based on all the possible electron conduction processes in n-type oxides (Figure S11b, Supporting Information), we further excluded the mechanisms of Schottky emission, Fowler-Nordheim (F-N) tunneling, direct tunneling, Poole-Frenkel (PF) emission, and space-charge-limited current (SCLC) conduction (detailed analysis is discussed in Figure S12, Supporting Information).Although trap-controlled SCLC mechanism was used extensively to explain the conduction properties of switching oxides (Figure S12f, Supporting Information, presents the temperature-dependent logarithmic plot of the I-V curves), [41,42] in fact, trap-controlled SCLC is an oversimplified physical mechanism, it generally includes contributions from Ohmic conduction, PF, and hopping, and it is a condition or threshold for behavior when all of these contributors reach a certain magnitude. [43]Hence, the finely defined conduction mechanisms need to be carefully investigated.

mechanisms (Figure
In the case of HRS (Figure 3a), the device current is almost independent of the sweeping voltage at a low-temperature range (80-140 K), and this dominant current only appears at a lower voltage region as the temperature increases.This current contribution can be attributed to the leakage current (I R L ) and is expressed by [44,45] where the resistance denoted as R L limits the Ohmic part of the leakage current.An outstanding model fitting with experimental data is performed in Figure S13, Supporting Information.[46][47] Similarly, at LRS, the contribution of the leakage current is also observed at low-temperature region (Figure S14, Supporting Information).With the increase in temperature, the conduction mechanism gradually transitions to another one which is strongly dependent on temperature.Such temperature-dependent current contributor is more prominent at LRS than at HRS.Given the introduced V o reservoir at the top electrode interface of the 30 nm LNO memristor, we speculate that this mechanism might be a bulk-limited trap-assisted conduction mechanism, i.e., hopping transport.The electrical conductivity in any hopping regime follows a temperature dependence of the type [48][49][50][51] σðTÞ where T 0 is the characteristic temperature, σ 0 is the conductivity for T !∞, and the electrical conductivity (σ) can be calculated by IL VS .I is the device current, and V is the applied voltage.The L and S represent film thickness and device area, respectively.The p is an exponent that depends on the specific type of hopping mechanism.For the nearest-neighbor hopping (NNH) mechanism, p = 1. [51]All variable-range hopping (VRH) mechanisms obey p < 1, where the Efros-Shklovskii VRH mechanism (ES-VRH) is characterized by p = 1/2 [50] and the Mott-VRH mechanism exhibits p = 1/4 for the 3D system. [48,49]igure 3c-e shows the plots of ln J as a function of T À1 , T À1/2 , and T À1/4 for the LNO-based device, respectively.The Arrhenius plot (Figure 3c) displays the deviation of the data from linear relation, indicating that the transport mechanism is not NNH, while thermally activated band conduction can also be excluded (expressed as σðTÞ ¼ σ 0 exp ½À E a k B T , [52][53] where E a is the activation energy and k B is the Boltzmann constant).For the VRH mechanisms, the electric field dependence of linear relation obeyed with ln J versus T À1/4 further confirmed the conduction mechanism is Mott-VRH rather than ES-VRH behavior (Figure 3d,e).Driven by the electric field, the V o migration along oxygen octahedra induces defect redistribution in the LNO layer, which promotes electron hopping transport.In this manner, the Mott-VRH process also dominates the current transport of HRS at a higher temperature region (235-315 K) (Figure S15, Supporting Information).When a reverse bias is applied, the V o s moves toward the top electrode interface and the corresponding electron hop to the anode.The Mott-VRH also dominates at reverse bias, while leakage current is still the main contributor under low-temperature region (Figure 3f,g, and S16, Supporting Information).
The above results can be summarized in the following scenario as plotted in Figure 3h,i.Overall, the current transport in our LNO memristor is dominated by Mott-VRH conduction, despite the contribution of leakage current at low-temperature region (Figure 3h).Notably, at HRS/LRS or different polarity bias, the crossover at the temperature region and electric field intensity dominated by Mott-VRH are inequable; it might be due to the field-driven differential distributions of V o s and defect density in the LNO layer. [43]This electron transport feature can also be evaluated from the hopping parameters (Table S2, Supporting Information and Experimental Section).At LRS, the density of states (DOS) at Fermi level (N (E F ) % 8.32 Â 10 16 eV À1 cm À3 ) is higher over an order of magnitude than that of HRS and reverse bias.Meanwhile, the average hopping energy (Δ hop ) with a value of 0.26 eV at 300 K guarantees the electron hopping over a smaller hopping distance (R hop ), whereas higher hopping energy is required for HRS (0.53 eV) and reverse bias (0.49 eV).Benefiting from the highly ordered crystal structure of ion-slicing single-crystalline LNO layer, the field-driven hopping transport process (Mott-VRH) has high stability and repeatability during bipolar voltage sweeping, which promotes the uniformity of device switching.
Figure 3i illustrates the V o migration scenarios in the proposed device.First, a V o -rich amorphous layer is formed on the surface of single-crystalline LNO thin film by Ar þ beam irradiation, which acts as a defect reservoir.The introduction of high-density V o s is equivalent to N-type heavy doping, [54] and Ohmic contact is formed at top electrode interface, while a nonideal Schottky diode is formed at the bottom electrode interface due to metal-semiconductor contact . [55]The consistent electroforming processes and I-V sweeps of the Ar þ -irradiated LNO-based devices show the independence of top electrodes (Au, Cr, Pt, and Ti) which further verify the formation of Ohmic contact at the top electrode interface (Figure S17, Supporting Information).Such special interfacial MIM structure was also realized in Au/SrTiO 3 /Au memristor by fine-tuning the doping concentration in SrTiO 3 . [56]After the device is reset to HRS, V o s migrates under forward bias, and Mott-VRH conduction gradually becomes the major contributor to device current when the temperature is up to 235 K (Table S2, Supporting Information).In contrast, at LRS, a higher defect density distributed in the LNO layer facilitates the electron hopping process, allowing hopping transport to dominate at a relatively lower temperature (160 K).At reverse bias, the V o s migrates toward the top electrode interface, and the Mott-VRH conduction is clamped by the interfacial barrier of bottom electrode interface, resulting in the self-rectifying characteristics of the Ar þ -irradiated LNO-based device (Figure 1b and S17, Supporting Information).

Analog Switching Characteristics of the LNO Memristor for Neuromorphic Computing
Based on the repeatably field-driven hopping transport mechanism, we investigated the analog switching characteristics of the ion-slicing LNO memristor for neuromorphic computing.Figure 4a displays the amplitude-dependent long-term potentiation (LTP) and long-term depression (LTD) characteristics which were measured with identical set/reset pulses.The write pulse sequence consists of 200 set pulses and 200 reset pulses.The result confirms that analog switching characteristics of the LNO memristor can be realized with ultrasmall fluctuation.
Furthermore, the memristor realizes an extremely high analog dynamic range (G max /G min ) with a value of 115.5 (AE2.5 V, 2 ms), along with a reliable conductance update (Figure 4b).Meanwhile, the analog dynamic range increases with the programmable pulse amplitude (AE2.7 V, G max /G min = 152.9;AE2.9 V, G max /G min = 180.4).Intriguingly, as the number of programmed pulses increases to 10 3 , the analog dynamic range with highly linear conductance potentiation can reach 592.5, demonstrating the great potential of the LNO memristor to access luxuriant synaptic weight values in neural network algorithms (Figure S18, Supporting Information).In addition, the uniformity of device-to-device dynamic range in possession of an average G max /G min of 114.7 further manifests that the conductance can be gradually updated by more than two orders of magnitude (Figure S19, Supporting Information).
In terms of linearity and symmetry, our LNO memristor shows highly linear analog conductance states in potentiation process, while the weight updates in an asymmetry manner due to the device conductance abruptly decay at the start of LTP process.Here, the abrupt depression feature might be ascribed to the rectification characteristic of our LNO memristor because the interface barrier at the bottom electrode interface forces a conductance drop when applied a negative voltage pulse (discussed in Figure 3).[62] Therefore, this exactly reflects the tradeoff among these nondesired device characteristics in existing emerging memristive devices for achieving the optimal scheme in a particular neuromorphic system. [7]In order to improve the linearity of conductance update, the programmable pulse scheme has been verified as an effective strategy. [10]Herein, an amplitudeincremental pulse scheme is employed to improve LTP linearity (Figure S21b, Supporting Information, potentiation: identical pulses; depression: incremental pulses).As presented in Figure 4c, it is shown that the programming scheme can significantly improve linearity and maintain an impressive analog dynamic range.Figure 4d plots the quantified nonlinearity of Reliable analog switching characteristics for neuromorphic computing.a) Amplitude-dependent LTP and LTD with identical pulse sequence consisted of 200 set pulses (amplitudes of 2.5, 2.7, and 2.9 V, the width of 2 ms) followed by 200 reset pulses (amplitudes of À2.5, À2.7, and À2.9 V, the width of 2 ms).The read pulse amplitude in this work is 0.5 V, and the pulse width is 50 μs.b) The analog dynamic ranges of different programming voltage amplitudes.The minimum conductance (G min ) corresponds to the conductance value after the first pulse stimulation and the maximum conductance (G max ) corresponds to the conductance value after the 200th pulse stimulation.c) Amplitude-dependent LTP and LTD with amplitude-incremental pulse scheme consisted of 200 set pulses (potentiation: identical pulses, amplitudes of 2.5, 2.7, and 2.9 V, the width of 2 ms) followed by 200 reset pulses (depression: incremental pulses, increasing pulse amplitudes from 0 to À2.5, À2.7, and À2.9 V, the width of 2 ms).d) Quantified nonlinearity of potentiation process and depression process with both identical pulse scheme and amplitude-incremental pulse scheme.e) Reproducible and uniform analog switching behavior over multiple cycles under identical pulse scheme.f ) Reproducible and uniform analog switching behavior over multiple cycles under amplitude-incremental pulse scheme.g) Level-to-level variations in LTP/LTD process, i.e., every intermediate state's variance, extracted from (f ).The average variations (Δ avg ) represented the overall variations in LTP/LTD process.The variation (Δ) is calculated as the standard deviation-to-mean.h) Retention performance of 4-bit distinguishable intermediate states.i,j) The device's environmental stability with repetitive LTP/LTD characteristics during a total of 4000 programming pulses after a month.k) A three-layer MLP neural network consists of 28 Â 28 input neurons, 300 hidden neurons, and 10 output neurons.l) Evolution of accuracy with training epochs for the memristive neural network based on ideal devices and LNO memristors (under identical pulse scheme and amplitude-incremental pulse scheme).m) Simulation results of the RCE as a result of fluctuations (σ).Here, σ is the standard deviation of standard normal distribution in terms of the percentage of actual conductance values and is added to actual conductance values of the LNO memristor, which represents the dispersion degree of the conductance value drift caused by fluctuations.n) Confusion matrix of the recognition results of ten handwritten digits.Color bar: normalized probability of each predicted result under the correct output.
potentiation/depression process with both identical pulse scheme and amplitude-incremental pulse scheme (nonlinearity is calculated by Equation ( 5)- (7) in Experimental Section).As a result, a more symmetric conductance modulation (γ D = 3.51 for LTD) with nearly linear potentiation (γ P = 0.02 for LTP) is achieved.The marked improvement of LTD linearity is also demonstrated with amplitude-dependent incremental pulse scheme (Figure S22, Supporting Information).
As switching in the intermediate conductance state is a critical physical process during in-memory learning operations, the crucial performances of intermediate states beyond dynamic range, number of conductance states, and linearity and symmetry, including endurance (repeated switching between intermediate states), level-to-level variation, multilevel retention, and environmental stability, are the key measurements for the reliability of a memristive device. [8,10]As exhibited in Figure 4e,f, the LNO memristor is tested with repeated LTP/LTD processes through a total of 4000 programming pulses (identical and incremental pulses), demonstrating excellent repeatability of the analog switching behavior.Meanwhile, the low level-to-level variations in LTP/LTD process along 4000 programming pulses are quantitatively displayed in Figure 4g and S23, Supporting Information.Interestingly, when the device is at high conduction state, the variations gradually decrease to 1.10% (for LTP) and 0.75% (for LTD), demonstrating extremely stable conductance updating.In terms of retention performance, our LNO memristor demonstrates high stability of 4-bit ( 16) distinguishable intermediate states without overlapping, ensuring the weight update during network training (Figure 4h).In addition, the device's environmental stability with a 1 month elapsed time is also evaluated by repetitive switching operations between the LTP/LTD process (Figure 4i,j).The excellent stability and long-term repeatability of multilevel switches indicate promising prospects for practical analog neuromorphic computing applications.The performance comparisons with other LNO-based memristors and state-of-the-art oxide-based memristors are presented in Table S3 and S4, Supporting Information, respectively.
On the basis of measured analog switching characteristics of LNO memristor, a three-layer artificial neural network is simulated with the MNIST handwritten recognition dataset.The MLP consists of 28 Â 28 input neurons, 300 hidden neurons, and 10 output neurons, as shown in Figure 4k.To train the MLP, we used electrical pulses with various numbers to represent the different pixel values in a grayscale image.The actual conductance values of the LNO memristor are adopted to represent the weights of neural networks, and the nonideal factors (e.g., nonlinearity, asymmetry, fluctuation, and variation) are taken into consideration.For an evaluated baseline, the simulation using the weights with ideal device characteristics is also conducted.During training, we use Sigmoid and SoftMax activation functions in the hidden and output layer, respectively.The network is trained on 3 million patterns randomly selected from 60 000 training images with a minibatch size of 500, and the 10 000 test images are used for the inference (for detailed information, see Experimental Section).Figure 4l presents the evolution of recognition accuracy for the LNO-based devices (including identical pulse scheme and amplitude-incremental pulse scheme) compared with the ideal devices.The simulation confirms that the LNO-based memristive neural network can achieve a recognition accuracy of 95.6% following the software baseline closely, with only a consistent 0.1-0.3%gap.Intriguingly, despite the significant nonlinearity of the depression process for identical pulse scheme which results in an obvious asymmetry of weight update, the recognition rate of the neural network is still up to 93.8%.This mainly attributes to the large analog dynamic range of two orders of magnitude and the abundance of intermediate states (several hundreds) for the LNO memristor, which effectively reduces the harmful influence of nonlinearity. [8,10]Furthermore, the ultralow state fluctuation and level-to-level variance of the LNO memristor ensure that the intermediate states are distinguishable, thus further guaranteeing the operation of weight updating as few times as possible. [9,63]Here, the cycle-to-cycle normal distributions of continuous conductance states after being stimulated by a pulse train (taking 25 voltage pulses as an example) are investigated, indicating that the LNO memristor only requires at least oneand up to three-time weight update operations to achieve almost distinguishable state updating (Figure S24, Supporting Information).The poorer relative convergence efficiency (RCE, the ratio of the number of iterations required to achieve stable recognition accuracy (N) to the optimal result) [8] resulting from a larger fluctuation is also indicated that fluctuation is an important effect on weight updates during neural network training (Figure 4m). [15]Otherwise, more learning, which means more time, and greater energy consumption are needed to make up for large fluctuations and to achieve a relatively stable convergence. [7,8]Figure 4n displays the confusion matrix showing the simulated recognition results from the LNO-based memristive neural network versus the correct outputs.Excellent recognition rates (92.6% as a minimum and 98.0% as a maximum) are achieved, demonstrating the potential of the proposed ion-slicing LNO memristor for high-performance neuromorphic computing.

Conclusion
To sum up, we have demonstrated a reliable analog memristor based on ion-slicing single-crystalline LNO thin film.Relying on the highly ordered oxygen octahedra of LNO single crystal, the reversible Mott-VRH conduction dominates the device switching behavior and guarantees excellent analog switching characteristics with high stability and repeatability.The proposed memristor exhibits ultralow cyclic variances for multiple weight updating (down to 0.75%) and long-term data stability (only 0.74% conductance decay over 27.7 h), as well as great endurance with small fluctuation (fluctuated within 0.22% over 5 Â 10 5 cycles).Besides, the dynamic range of two orders of magnitude and hundreds of distinguishable intermediate states guarantee high-efficiency weight updating in neuromorphic computing.A high recognition accuracy of 95.6% for the MNIST dataset is realized with a two-layer perceptron simulation.The proposed analog memristive devices based on ion-slicing single-crystalline thin films offer a novel strategy for fabricating high-performance memristors that combined linear tunability and long-term repeatability, opening a novel avenue for neuromorphic computing application.

Figure 1 .
Figure 1.The fabrication process and switching characteristics of the ion-slicing LNO memristor.a) Schematic of the fabrication process of the ionslicing LNO memristor, including CIS and Ar þ beam irradiation.b) Typical electroforming process and subsequent I-V curve.Inset is the cross-sectional diagram of the memristor with a structure of Au/LNO/Cr/Pt/Cr.c) Properties of device endurance over 5 Â 10 5 cycles with a switching window of 80. d) Detailed statistical endurance analysis of LRS fitted by Normal distribution function.The device effectively switches with ultrasmall fluctuations in every cycle, demonstrating excellent reliability.The variations (Δ) are calculated as the standard deviation-to-mean (δ/μ).e) Retention test over a long period of 10 5 s.f ) Detailed retention analysis of LRS over 10 5 s.The conductance decay process only undergoes about 16.7 h (about 60 000 s) after programming the device to high conductance state (i.e., LRS), and then it remains stable without any degradation.

Figure 2 .
Figure 2. Microstructure and chemical composition analysis of the ion-slicing LNO memristor.a) Cross-sectional transmission electron microscopy image of the LNO memristor with a vertical Au/LNO/Cr/Pt/Cr structure.Scale bar: 50 nm.The 2D and 3D atomic force microscopy images of b) pristine ion-slicing single-crystalline LNO thin film (without irradiation) and c) the Ar þ -irradiated LNO thin film.Scale bar: 1 μm.Both RMS (R q ) and mean value roughness (R a ) are presented to evaluate the LNO surface topography.d) Detailed height profile of the Ar þ -irradiated sample.The scan route corresponds to the yellow line in (c).e) High-resolution transmission electron microscopy image of the region near the Au/irradiated LNO interface (deep-yellow dotted box in (a)).Scale bar: 2 nm.A sharply defined amorphous layer is formed on the single-crystalline LNO thin film.The inset is an enlarged micrograph in Region 2 and the corresponding fast Fourier transform patterns of Region 1 and Region 2. Scale bar: 1 nm.f ) High-resolution transmission electron microscopy image of the region near the Cr/monocrystalline LNO interface (blue dotted box in (a)).Scale bar: 2 nm.X-ray photoelectron spectra of Pd 3d g) for the pristine single-crystalline LNO thin film (without irradiation) and h) for the Ar þ -irradiated LNO thin film.a.u., arbitrary units.

Figure 3 .
Figure 3. Conduction mechanism analysis based on temperature-dependent I-V characterization.The J-V measurements are conducted in a wide temperature range (80-315 K).Temperature-dependent semilogarithmic J-V plots of the LNO memristor when the device is a) at HRS and b) at LRS. c) Arrhenius plot of ln J as a function of T À1 for different values of applied voltages.d) Values of ln J as a function of T À1/2 for different values of applied voltages.e) Values of ln J as a function of T À1/4 for different values of applied voltages.Inset is the schematic of the Mott-VRH model.E T , trap energy level; E v , valence band; E c , conduction band.f ) Temperature-dependent semilogarithmic J-V plots when the device is at reverse bias.g) Values of ln J as a function of T À1/4 when the device is at reverse bias.h) Schematic of a crossover of conduction mechanisms in the LNO memristor.Mott-VRH conduction dominates the device current transport, despite the contribution of leakage current at the low-temperature region.i) V o migration scenarios in the proposed device under initial state and different sweeping voltages (at HRS/LRS under forward bias and under reverse bias).The top columns are the corresponding equivalent circuit diagram.Ohmic contact forms at the top electrode interface because of the introduction of a V o -rich amorphous layer by Ar þ beam irradiation.The LNO layer is represented as a serial bulk resistor.In addition, a nonideal Schottky diode is formed at the bottom electrode interface.

Figure 4 .
Figure 4. Reliable analog switching characteristics for neuromorphic computing.a) Amplitude-dependent LTP and LTD with identical pulse sequence consisted of 200 set pulses (amplitudes of 2.5, 2.7, and 2.9 V, the width of 2 ms) followed by 200 reset pulses (amplitudes of À2.5, À2.7, and À2.9 V, the width of 2 ms).The read pulse amplitude in this work is 0.5 V, and the pulse width is 50 μs.b) The analog dynamic ranges of different programming voltage amplitudes.The minimum conductance (G min ) corresponds to the conductance value after the first pulse stimulation and the maximum conductance (G max ) corresponds to the conductance value after the 200th pulse stimulation.c) Amplitude-dependent LTP and LTD with amplitude-incremental pulse scheme consisted of 200 set pulses (potentiation: identical pulses, amplitudes of 2.5, 2.7, and 2.9 V, the width of 2 ms) followed by 200 reset pulses (depression: incremental pulses, increasing pulse amplitudes from 0 to À2.5, À2.7, and À2.9 V, the width of 2 ms).d) Quantified nonlinearity of potentiation process and depression process with both identical pulse scheme and amplitude-incremental pulse scheme.e) Reproducible and uniform analog switching behavior over multiple cycles under identical pulse scheme.f ) Reproducible and uniform analog switching behavior over multiple cycles under amplitude-incremental pulse scheme.g) Level-to-level variations in LTP/LTD process, i.e., every intermediate state's variance, extracted from (f ).The average variations (Δ avg ) represented the overall variations in LTP/LTD process.The variation (Δ) is calculated as the standard deviation-to-mean.h) Retention performance of 4-bit distinguishable intermediate states.i,j) The device's environmental stability with repetitive LTP/LTD characteristics during a total of 4000 programming pulses after a month.k) A three-layer MLP neural network consists of 28 Â 28 input neurons, 300 hidden neurons, and 10 output neurons.l) Evolution of accuracy with training epochs for the memristive neural network based on ideal devices and LNO memristors (under identical pulse scheme and amplitude-incremental pulse scheme).m) Simulation results of the RCE as a result of fluctuations (σ).Here, σ is the standard deviation of standard normal distribution in terms of the percentage of actual conductance values and is added to actual conductance values of the LNO memristor, which represents the dispersion degree of the conductance value drift caused by fluctuations.n) Confusion matrix of the recognition results of ten handwritten digits.Color bar: normalized probability of each predicted result under the correct output.