Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

Charge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal–oxide–semiconductor logic process exhibit ≈2,000× lower on‐current (Ion) and ≈3,000× lower off‐current (Ioff) than CT‐MOSFETs, rendering them suitable for high‐accuracy large‐scale neuromorphic systems. According to the experimental and simulation results, CT‐TFETs outperform CT‐MOSFETs in terms of more accurate analog vector‐matrix multiplication than that of CT‐MOSFETs due to the following two reasons: first, CT‐TFETs feature a lower voltage (IR) drop resulting from lower Ion than that of CT‐MOSFETs. Second, the former is more robust to the IR drops than the latter due to weak channel length modulation. For example, unlike CT‐MOSFETs, the proposed CT‐TFETs exhibit ignorable weight degradation in spite of the 1 Ω wire resistance. CT‐TFET arrays show ≈700× lower power consumption and ≈10% higher MNIST classification accuracy than CT‐MOSFET arrays, making CT‐TFET arrays promising for extensive and versatile neuromorphic computing applications.


Introduction
To meet the growing demand for high computing performance and large memory capacity, the sizes of metal-oxidesemiconductor field effect transistors (MOSFETs) are continually reduced.Downscaling boosts logic performance and memory capacity.However, as the amount of processed data is increasing exponentially owing to the advent of artificial intelligence, the von Neumann bottleneck between computing and memory parts is aggravated. [1]o address this issue, neuromorphic hardware architectures, which combine the computing and memory components into synaptic arrays, have been proposed.The synapse array performs analog vector-matrix multiplication (VMM) based on Kirchhoff's current law using various types of nonvolatile memory (NVM) devices such as flash memory, resistive randomaccess memory (RAM), phase-change RAM, and ferroelectric field effect transistors (FETs). [2]However, the implementation of large-scale synapse arrays is challenging because of the voltage (IR) drops and weight degradation, which originate from the high on-current (I on ) and finite output resistance of NVM devices. [3]Thus, ideal NVM arrays require two important characteristics, i.e., a low I on and cell current saturation, to overcome the IR drop, as illustrated in Figure 1.The low I on is required to prevent the IR drop when a large-scale array is configured, as shown in Figure 1a.Saturation of the cell drain current (I D ) over the drain voltage (V D ) is essential for providing IR drop immunity in a large-scale array, as shown in Figure 1b.To date, because of the lack of these two characteristics, most implemented NVM-based neuromorphic systems comprise a group of small-sized subarrays (128 Â 128) to manage power consumption and IR drop. [4]However, this approach degrades the power, energy, and area efficiency of neuromorphic systems, and limits the applicability of analog VMM owing to the large number of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs).Consequently, an ideal NVM memory requires low I on and good current-saturation characteristics.
Tunnel FETs (TFETs) are known to exhibit lower on-current (I on ) and off-current (I off ) than MOSFETs, making them less suitable for high-performance logic applications. [5,6]However, the low I on is crucial for the low-power and high-accuracy inference operation of large-scale neuromorphic arrays.[9] Moreover, TFETs can have superior IR drop immunity compared with MOSFETs owing to their better drain current saturation. [10,11]Consequently, TFETs are powerful devices capable of enabling low-power, large-array configurations.
This study proposes a novel neuromorphic system using low-power complementary metal-oxide-semiconductor (CMOS) logic-process-compatible charge-trapping TFETs (CT-TFETs) for large-scale VMM operation, as shown in Figure 1c.A charge-trap transistor (CTT) structure based on the high-k metal gate (HKMG) process, which is fully compatible with the conventional CMOS logic process, is used for the TFET memory.Because of its low operating voltage, good retention characteristics, and poor endurance characteristics, [12] the CTT is suitable for performing inference operations in off-chip-trained neuromorphic hardware.
Our key contributions to this study include the novel CT-TFET-based neuromorphic array design and detailed analysis of its performance characteristics, demonstrating significant improvements in power efficiency, low IR drop, IR drop immunity, and configurability compared to the existing NVM-based neuromorphic systems.Using HSPICE [13] circuit simulation, the IR drop immunity and VMM accuracy were evaluated in CT-TFETs.In addition, the maximum configurable array size according to the parasitic wire resistance (R wire ) was addressed.

Device Characteristics
Structures of CT-TFETs and charge-trapping MOSFETs (CT-MOSFETs) are compared, as shown in Figure 2.Both CT-TFETs and CT-MOSFETs are based on silicon-on-insulator structure, which eliminates junction leakage and enables CT-TFETs to achieve extremely low I off . [14]CT-TFETs are fully compatible with conventional HKMG CMOS processes because the only difference between CT-MOSFETs and CT-TFETs is the source doping type. [14]The cross-sectional transmission electron microscopy (TEM) images of the fabricated CT-TFETs and their gate stacks are shown in Figure 2c,d.The channel length (L ch ), SiO 2 , and HfO 2 layer thicknesses were 500, 1.74, and 6.33 nm, respectively.A thin SiO 2 tunneling layer is located between the HfO 2 layer and silicon channel for high Fowler-Nordheim (FN) tunneling efficiency and low interface trap density.Reliable charge storage can be achieved without a blocking oxide because electrons are stored in the deep traps of the HfO 2 layer. [12,15]For comparison, CT-MOSFETs were cointegrated with CT-TFETs.
The hysteretic characteristics and gate leakage were measured prior to validating the synaptic operation, as shown in Figure 3. Due to the thick tunneling layer and charge trap layer, only ignorable hysteresis and gate leakage were observed in the low gate voltage range (À2 to 2 V) corresponding to read operation in the case of both CT-TFETs and CT-MOSFETs.In contrast, when the gate voltage is swept in a higher gate voltage range (À4 to 4 V) corresponding to program and erase operation, hysteresis behavior, and gate leakage appear in both kinds of devices owing to FN tunneling.Thus, both CT-TFETs and CT-MOSFETs can function as synaptic devices and stable VMM operation is feasible within the read gate voltage range.It should be noted that the currents of CT-TFETs and CT-MOSFETs at negative gate voltage stem from the ambipolar behavior of TFETs [16] and the gate-induced drain leakage of MOSFETs, [17] respectively.
The measured transfer curves of the CT-TFETs and CT-MOSFETs after the program/erase operation are shown in (TE) rates in CT-MOSFETs, which induces transconductance switching between the erased and programmed state.It is observed that CT-TFETs exhibit low I on (100 nA) and I off (1 pA), whereas CT-MOSFETs exhibit high I on (100 μA) and I off (3 nA).CT-TFETs have lower I on due to the probabilistic nature of BTBT as opposed to TE. [6] Additionally, the indirect bandgap of silicon degrades BTBT current. [18]In the case of I off, CT-TFETs rarely exhibit leakage current owing to extremely low reverse-mode p-i-n diode leakage in the off-state.In contrast, CT-MOSFETs suffer from significant TE-induced subthreshold leakage in the off-state. [6]Furthermore, it is well-known that TFETs can have lower subthreshold swing than MOSFETs. [19]onsequently, CT-TFETs are more suitable for large-scale neuromorphic arrays than CT-MOSFETs owing to their extremely low power consumption and low IR drop.Furthermore, considering the speed requirements of the control circuitry, I on of CT-TFETs aligns well with the optimal range for ADCs in neuromorphic hardware systems. [3]o implement the CT-TFET in an off-chip trained neuromorphic system, the program/erase pulse schemes and their corresponding weight (drain current) update results as functions of the pulse number are shown in Figure 5.When incremental step pulse programming (ISPP) is used to fine-tune the weights, [20] both CT-TFETs and CT-MOSFETs exhibit linear and gradually changing symmetric weight updates.Among the weight values, four fine-tuned weights (that is current levels) were selected to implement a quantized neural network (QNN), which is commonly utilized to evaluate the synaptic performance of various  devices such as resistive RAM and flash devices. [21,22]Note that the ISPP scheme was used for fine-tuning operations rather than for on-chip learning operations.As shown in Figure 6, both CT-TFETs and CT-MOSFETs were trained to have four fine-tuned weights to implement the QNN.For a fair comparison, both devices were operated within the same overdrive voltage (V OV ) range (V OV = 0.7-1 V).In addition, both devices operated in the linear region at 1 V or less because their V ov ranges were the same.Although operating in the subthreshold region can reduce I on , [23] both devices operate in the linear region because of the sensitivity of the subthreshold region to noise effects [24] and changes in the trap density.CT-TFETs exhibit a better channel length modulation parameter (λ) than CT-MOSFETs with the same device dimensions, which is essential for the implementation of large-scale neuromorphic arrays with IR drop immunity.λ was calculated by using the two-point extraction method at the saturation region. [25]Moreover, TFETs exhibit superior saturation behavior compared to MOSFETs, even in the case of short channels (e.g., L ch = 20 nm [10] ), enabling further scaling of CT-TFETs.CT-TFETs show excellent data retention characteristics for the four fine-tuned weights (Figure S1a, Supporting Information) because they use the same storage mechanism as the CT-MOSFETs which are reliable in terms of data retention. [15]For HSPICE circuit simulation of large-scale neuromorphic arrays, compact models of 500 nm CT-TFETs and CT-MOSFETs were calibrated through measurements.CT-TFETs were calibrated using Notre Dame TFET compact model, [26] and CT-MOSFETs were calibrated using PTM models, [27] respectively.

Neuromorphic Hardware Application
A QNN with a two-bit quantized weight and activation in all the layers (convolutional layer 1: 5 Â 5 Â 20, convolutional layer 2: 5 Â 5 Â 50, fully connected layer 1: 800 Â 800, and fully connected layer 2: 800 Â 10) was adopted for MNIST data classification to compare the analog VMM accuracy and power consumption of the CT-TFET and CT-MOSFET arrays.The QNN was trained using a quantization-aware training method [28] achieving a software accuracy of 97.3% for 28 Â 28 Â 1 MNIST pattern data.For an intuitive comparison of the analog VMM operation between CT-TFET and CT-MOSFET arrays, they were applied to fully connected (FC) layer 2. (10-40 μs), as shown in Figure 7b.First, the BL voltage (V BL ) was set as 1 V to evaluate the effects of I on on the inference performance without considering the saturation characteristics.Subsequently, the output was calculated using the sum of the currents at each pulse (I 0 -I 3 ), as shown in Figure 7c.MNIST data classification was performed to evaluate the VMM accuracy of the CT-TFET and CT-MOSFET arrays.Table 1 presents an overall performance comparison between CT-TFET and CT-MOSFET arrays when applied to FC layer 2. For a simple comparison, the output neuron with the largest current sum was treated as the correct answer.CT-TFET arrays achieved the same accuracy (98%) as the software, whereas CT-MOSFET arrays exhibited degraded accuracy (89%) when 100 randomly selected patterns were applied.Moreover, owing to their low I on , CT-TFET arrays demonstrate %700Â lower power consumption than that of the CT-MOSFET arrays.In addition, the excellent retention characteristics of CT-TFET assure high MNIST data classification accuracy for an extended period of time (Figure S1b, Supporting Information).
Figure 8 shows the cases where the MNIST pattern "5" was applied to both CT-TFET and CT-MOSFET arrays to compare the VMM accuracy and IR drop.CT-TFET arrays demonstrated software-level accuracy, whereas CT-MOSFET arrays exhibited %60% VMM error and incorrectly identified the patterns "5" as "3".Furthermore, CT-MOSFET arrays failed to correctly compute the output "6", indicating that IR drop not only degrades the current sum but also significantly lowers the VMM accuracy.Thus, NVMs with high I on are unsuitable for large-scale arrays.Figure 9a provides a detailed examination of the VMM operation in the CT-MOSFET array.It illustrates the sum of currents for each cell when I 0 is calculated with pattern inputs of "5".
As shown in Figure 9a, CT-MOSFET arrays show severe sum current degradation, indicating that the IR drop compromises the VMM accuracy.In addition, compared with the target current, CT-MOSFET arrays exhibited a lower current sum in BL3 than in BL5, leading to incorrect classification.As shown in Figure 9b, this is because the majority of high-value VMM operations occur in the upper cells of BL3, resulting in a relatively lower sum weight degradation effect than in BL5.On the contrary, CT-TFET arrays exhibit no IR loss and weight degradation owing to their low I on characteristics.Consequently, CTFET arrays have a distinct advantage over CTMOSFET arrays in large-scale high-precision VMM operations.
In this section, the VMM accuracies of CT-TFETs and CT-MOSFETs are compared when the same IR drop occurs using the current saturation mode (V BL = 2 V) rather than the linear current mode (V BL = 1 V). Figure 10a demonstrates that both CT-TFETs and CT-MOSFETs exhibit IR drop immunity when operating in the current saturation mode versus the current linear mode.Additionally, CT-TFETs are expected to exhibit superior IR drop immunity owing to their lower λ. Figure 10b compares the IR drop immunity of CT-TFET and CT-MOSFET arrays in both current linear and saturation modes.Compared to the current linear mode, the current saturation mode exhibited greater immunity to the same IR drops.This suggests that despite an increase in power consumption owing to a higher V BL , more precise operation of the VMM can be achieved by employing the current saturation mode rather than the linear current mode.Figure 10c compares the accuracy of the VMM in the current linear and saturation modes using the previous MNIST input.R wire was set to generate 1 V drop equally in CT-TFET and CT-MOSFET arrays with V BL = 2 V, respectively.Both CT-TFET and CT-MOSFET arrays exhibited lower VMM errors in the current-saturation mode than in the current-linear mode.Notably, CT-TFET arrays, with near-zero λ, exhibited <1% VMM error, enabling five-bit VMM precision.Consequently, CT-TFET arrays provide more precise VMM operations and larger-area configurations than CT-MOSFET arrays when operating in current saturation mode.In conclusion, the current saturation mode improves the overall performance of CT-TFET  arrays more than that of CT-MOSFET arrays in terms of VMM accuracy and configurability.
Finally, the maximum configurable array sizes for CT-TFET and CT-MOSFET arrays were compared in both the current linear and saturation modes, depending on the R wire .Because inputs may not be applied simultaneously in applications, such as spiking neural networks, [29] or may have a large number of zero values, [30] the maximum configurable array sizes for both 100% and 25% activity levels were determined.Figure 11 demonstrates that CT-TFET arrays can be configured up to %50Â larger than CT-MOSFET arrays in the current linear mode owing to their low I on .Furthermore, CT-TFET arrays can be configured %72Â larger in the current saturation mode than CT-MOSFET arrays owing to their lower λ.Consequently, with R wire = 1 Ω, CT-MOSFET arrays struggle to satisfy even the simple MNIST FC size requirements, [31] whereas CT-TFET arrays can accommodate the more complex VGG FC-4096 size requirements. [32]This indicates that CT-TFET arrays can operate at extremely high TOPS/W, [3] making them more energy-efficient for large-scale neuromorphic applications.Furthermore, this result implies that even if CT-MOSFET arrays are scaled, larger metal features must be used to minimize the effects of the parasitic resistance components, [4] which would limit the array density.

Conclusion
This study proposes low-power and CMOS logic processcompatible CT-TFET neuromorphic arrays for accurate largescale analog VMM operations.Based on the experimental and simulation results, CT-TFET neuromorphic arrays demonstrated lower IR drop and greater robustness to IR drop than CT-MOSFET arrays.When applied to FC layer 2, CT-TFETs achieved the same level of accuracy as the software, while consuming lesser power than CT-MOSFETs.Additionally, CT-TFETs can also be applied to large and complex neural networks.Therefore, devices with low I on current and λ characteristics are essential for performing VMM on a large scale with high precision and low power consumption.To the best of our knowledge, CT-TFETs are the only existing CMOS logic processcompatible devices with these characteristics.

Figure 4 .Figure 1 .
Figure 1.a) Comparison between conventional and ideal NVM arrays.While conventional NVM arrays suffer from IR drop and weight degradation owing to high I on , no IR drop occurs in an ideal NVM array.b) Effects of saturation characteristics on IR drop immunity.c) Proposed large-scale neuromorphic system using CT-TFET arrays.Low power consumption can be achieved by using a few DACs/ADCs.

Figure 3 .
Figure 3. Measured hysteretic transfer curves of CT-TFETs when gate voltage sweeps a) between À2 and 2 V (read operation) and b) between À4 and 4 V (program and erase operation).Measured hysteretic transfer curves of CT-TFETs when gate voltage sweeps c) between À2 and 2 V (read operation) and d) between À4 and 4 V (program and erase operation).

Figure 4 .Figure 5 .
Figure 4. Measured transfer curves of a) CT-TFETs and b) CT-MOSFETs under the erased and programmed state.CT-TFETs feature low I on and I off while CT-MOSFETs feature high I on and I off .The subthreshold swings of CT-TFETs and CT-MOSFETs are 260 mV dec À1 (10-100 pA) and 303 mV dec À1 (0.1-1 μA), respectively.

Table 1 .
Performance summary of neuromorphic arrays in FC layer 2 application.