Ultralow‐Power Compact Artificial Synapse Based on a Ferroelectric Fin Field‐Effect Transistor for Spatiotemporal Information Processing

Artificial synapses are key elements in building bioinspired, neuromorphic computing systems. Ferroelectric field‐effect transistors (FeFETs) with excellent controllability and complementary metal oxide semiconductor (CMOS) compatibility are favorable to achieving synaptic functions with low power consumption and high scalability. However, because of the only nonvolatile ferroelectric (Fe) characteristics in the FeFET, it is difficult to develop bioplausible short‐term synaptic elements for spatiotemporal information processing. By judiciously combining defects (DE) and Fe domains in gate stacks, a compact artificial synapse featuring spatiotemporal information processing on a single Fe–DE fin FET (FinFET) is proposed. The devices are designed to work in a separate DE mode to induce short‐term plasticity by spontaneous charge detrapping, and a hybrid Fe–DE mode to trigger long‐term plasticity through the coupling of defects and Fe domains. The capability of the compact synapse is demonstrated by differentiating 16 temporal inputs. Moreover, the highly controllable static electricity of advanced FinFETs leads to an ultralow power of 2 fJ spike−1. An all Fe–DE FinFET reservoir computing (RC) system is then constructed that achieves a recognition accuracy of 97.53% in digit classification. This work enables constructing RC systems with fully advanced CMOS‐compatible devices featuring highly energy‐efficient and low‐hardware systems.


Introduction
Artificial neural networks (ANNs) exhibit great promise for next-generation computing with high efficiency.3][4][5][6][7] Specific functional requirements for artificial synapses depend on the architecture of neural networks.10][11][12] Given the potential in encoding and processing complex spatiotemporal information, [10][11][12] it is essential to develop compact artificial synapses for constructing low-power RC Artificial synapses are key elements in building bioinspired, neuromorphic computing systems.Ferroelectric field-effect transistors (FeFETs) with excellent controllability and complementary metal oxide semiconductor (CMOS) compatibility are favorable to achieving synaptic functions with low power consumption and high scalability.However, because of the only nonvolatile ferroelectric (Fe) characteristics in the FeFET, it is difficult to develop bioplausible short-term synaptic elements for spatiotemporal information processing.By judiciously combining defects (DE) and Fe domains in gate stacks, a compact artificial synapse featuring spatiotemporal information processing on a single Fe-DE fin FET (FinFET) is proposed.The devices are designed to work in a separate DE mode to induce short-term plasticity by spontaneous charge detrapping, and a hybrid Fe-DE mode to trigger long-term plasticity through the coupling of defects and Fe domains.The capability of the compact synapse is demonstrated by differentiating 16 temporal inputs.Moreover, the highly controllable static electricity of advanced FinFETs leads to an ultralow power of 2 fJ spike À1 .An all Fe-DE FinFET reservoir computing (RC) system is then constructed that achieves a recognition accuracy of 97.53% in digit classification.This work enables constructing RC systems with fully advanced CMOS-compatible devices featuring highly energy-efficient and low-hardware systems.[15] Despite that compact synapses featuring both short-term plasticity (STP) and long-term plasticity (LTP) have been achieved in emerging devices [3,13,[16][17][18][19][20][21] and been demonstrated to emulate versatile biosynapses functions (Figure 1a-c), [5,13] high electroforming voltage, limited reproducibility, and poor complementary metal oxide semiconductor (CMOS) compatibility are still problems.
[24][25] This device resembles the conventional transistor except for a Fe layer inserted into the gate stack, which gives the FeFET excellent CMOS compatibility and scalability.Furthermore, FeFETs have proven favorable for achieving complicated artificial neural functions with low power consumption, owning to three-terminal structure.Given these advantages, there is increasing interest in the FeFET-based RC system for ultralow power consumption.[29] However, LTP performance which depends on stable Fe polarization may be deteriorated by the dynamic polarization switching which is introduced in the film intentionally for STP realization, making it challenging to establish compact synapses.Another problem is that the STP performance of such devices may decline because of the reduced number of domains and fewer interactions between domains in a smaller area; therefore, device scalability is also challenging.FeFET-based compact synapses have been attempted by introducing organic materials; [30] however, CMOS incompatibility hinders the development of devices for neuromorphic computing.
Here, we present a compact artificial synapse based on an advanced CMOS fin FET (FinFET) with an inserted Fe Hf 0.5 Zr 0.5 O 2 (HZO) film with defects (DE) (Fe-DE FinFET).Besides fundamental LTP operation via stable Fe polarization, this compact synapse can process spatiotemporal information with volatile STP via spontaneous charge detrapping.Fe-DE FinFET devices can therefore bioplausibly emulate various kinds of synaptic signals governed by hybrid mechanisms.We also design a homogeneous RC system with all synapses constructed from the Fe-DE FinFETs.This system uses STP to extract and LTP to classify features and simulates a highly efficient ANN.The system can perform classification tasks with low power consumption and hardware cost.

Concept of Compact Artificial Synapses Based on a Single Fe-DE FinFET
The compact artificial synapses are designed by inserting an HZO film with Fe domains and oxygen vacancies (V o ) into a FET, as shown in Figure 1d.While the Fe polarization is nonvolatile, charge trapping/detrapping caused by V o is a naturally dynamic process inducing a volatile process.Both Fe polarizations and charge trapping/detrapping can modulate electronic carriers in the underlying semiconductor, thereby introducing multifield effects in a device.Because of the unique properties of Fe materials, the natural coercive voltage (V c ) can be adopted as a threshold for Fe and DE behaviors.Therefore, changing the amplitude of the gate voltage (V GS ) causes the compact synapse to switch between two modes to produce LTP and STP.In the separate DE mode, a positive V GS bias under V c stressing causes electrons to be trapped in gate stacks and an electric field to be established, thereby changing the channel conductance.After the V GS removal, there is no restraint from the external gate electric field, and trapped charges gradually drift back to the channel under the upward Fe polarization (from the channel to the gate) induced repulsive electric field, inducing current relaxation or STP (Figure 1e).As V GS exceeds V c and the devices work in the hybrid Fe-DE mode, the Fe polarizations switch to downward.In this condition, the switched polarizations remain stable after the V GS removal (Figure 1f ), and the electric field induced by the stable downward domains can keep the trapped charges avoiding charges drifting back to the channel, thereby leading to LTP.The compact synapses feature with both STP and LTP characteristics are suitable for spatiotemporal data processing.For example, in an RC system, the decay of STP can nonlinearly transform sequential inputs into a highdimensional space.Subsequently, the generated spatiotemporal patterns can be analyzed in the readout with LTP characteristics.

Characterizations of the Fe Phase and Oxygen Vacancy DE
To investigate Fe and DE effects in the HZO films, we fabricated capacitors with multilayer stacks of W/TiN/9-nm HZO/TiN/Si on 8-12 Ω cm Si substrates.In addition to measurements of remnant hysteresis and the C-V curve (Figure S1, Supporting Information), high-resolution transmission electron microscopy (TEM) and X-ray diffraction (XRD) were also performed to characterize the thin HZO film.O-phase grains along the [100] and [001] zone axes, regarded as the origin of ferroelectricity, are confirmed in the crosssectional high-angle annular dark field scanning transmission electron microscopy (STEM-HAADF) images in Figure 2a.The existence of the o-phase in the HZO films is also confirmed by grazing incidence X-ray diffraction (GIXRD), as shown in Figure 2b.The diffraction peaks at 2θ values of %30°and 35°s uggest that HZO films in the devices were crystallized.Furthermore, the existence of V o was also confirmed with electron energy loss spectra (EELS), as shown by analyzing the plasma peaks in Figure 2c.33] The Fe-DE FinFETs were subsequently fabricated using traditional metal gate all-last FinFETs and inserting the HZO films into the gate stacks.Fabrication of the Fe-DE FinFETs was similar to that in previous work on FinFETs, [34,35] apart from the multilayer gate stacks, exhibiting excellent compatibility with mainstream CMOS technology.The interfacial layer (IL) was formed by ozone oxidation.In the metal gate replacement, a 9 nm HZO film was deposited via atomic layer deposition.The cross-sectional bright-field TEM image of an Fe-DE FinFET is shown in Figure 2d.Corresponding energy-dispersive X-ray spectroscopy maps of Si, O, N, Zr, Hf, and Ti are shown in Figure 2e, which verify the good compositional uniformities of the ultrathin Si fin channels and conformal multilayer SiO 2 /HZO/TiN/TaN/TiN/W stacks.

STP and LTP Realization on a Compact Artificial Synapse
Different from the traditional FeFET, the devices exhibit a slight anticlockwise hysteresis (as shown in Figure S2, Supporting Information), which indicates strong charges trapping effect.Subsequently, Fe and DE processes in the devices were investigated and confirmed by threshold voltage (V T ) shifts under different program voltages.Figure 2f,g shows transfer curves (I DS -V GS ) of the p-type Fe-DE FinFETs.The inserted image in Figure 2f shows the applied sequential V GS waveforms, which included an initial pulse (V Ini ), a program voltage pulse (V Pro ), and a voltage sweep to monitor the evolution of the V T state.Subsequently, retention characteristics of those |V T | states were investigated by reading the states under different V Pro values at different times.Figure 2h confirms Fe-induced long-term memory and DE-induced short-term memory behaviors.As the program voltage increases, the retention characteristics of the corresponding memory states improve.In the separate DE mode with V Pro = 2 V, the programmed drain current decays to a fresh state within 1000 s.Although the retention characteristics improve with V Pro = 3 V, obvious current decay also occurs because of charges detrapping.Notably, in the hybrid Fe-DE mode with V Pro = 5 V, the drain current remains in the programmed state without decay for 1000 s.The realization of both short-and long-term memory behaviors in single Fe-DE FinFETs provides possibilities for achieving a compact synapse.
The compact synaptic behaviors of the Fe-DE FinFETs were studied via pulse measurements.Figure 2i shows the response current when a 1.5 V voltage pulse with a width of 10 ms and an interval of 10 ms was applied to the gate terminal.The conductivity of the channel was read with a low V DS bias of À0.1 V and a V GS bias of À0.8 V.It is seen that I DS abruptly increases when the gate pulse is applied.Subsequently, the current gradually decays after the gate voltage is removed and returns to the initial state within approximately 20 s.This behavior is similar to that of biological synapses. [36,37]With sequential V GS pulse stressing, electrons tunnel into gate stacks, and channel conductivity increases continuously.After V GS stress removal, electrons quickly leak back to the channel, and channel conductivity decreases.The relaxation time scale of a few seconds suggests STP, which is important for processing temporal information on the relevant time scales.
When a higher voltage pulse was applied to the gate, a transition from STP to quasi-LTP occurred, as confirmed in Figure 2j.In this condition, voltage pulses with amplitudes of 2.5 V were applied to the gate terminal.Owning to the V GS pulse which is higher than that in Figure 2i, more electrons tunnel into the gate stack layers and are trapped in there.Although I DS still relaxes with time because of partial electron leakage, the channel conductance cannot recover to the initial state within a few seconds owing to excessive trapped charges in gate stacks (like the retention state under 3 V voltage pulses in Figure 2h).A residual current (I res ) can be observed after I DS relaxation for 20 s, implying a quasi-LTP with a larger time scale. [37]s higher voltage pulses (>V c ) are applied to the gate, ferroelectrically induced LTP is observed in Figure 2k.In this case, voltage pulses with amplitudes of 3.5 V were applied.With sequential stressed V GS pulses, Fe polarization switching occurs and channel conductivity decreases continuously.After V GS stress removal, Fe polarization remains and so does the channel conductive state.Because of the higher potential barrier induced by switched polarization, electrons cannot leak into the channel, thereby a residual current, implying ferroelectrically induced LTP.

First-Principles Calculation of the Fe-DE Coupling Effect
Systematic atomic-level first-principles calculations are performed to gain better insight into the Fe-DE coupling effect.First, we construct a gate stack model with the structure Si/SiO 2 /Hf 0.5 Zr 0.5 O 2 /TiN, which is connected by stacking orthorhombic Hf 0.5 Zr 0.5 O 2 and α-quartz SiO 2 on a Si (001) surface.The slab models are relaxed via first-principles calculations, and H atoms are applied to provide an insulating electronic structure without midgap states.We choose the orthorhombic phase of Hf 0.5 Zr 0.5 O 2 as the Fe origin, and the V o s are considered the origins of DE in this model. [38]ext, we theoretically investigate the electronic states of the SiO 2 /Hf 0.5 Zr 0.5 O 2 heterostructure with both the separate DE mode and hybrid Fe-DE working mode as our devices.

Dynamic and Nonvolatile Memory States for the RC System
The Fe-DE FinFET working in DE mode can be further used to construct the reservoir of RC system.The state of the reservoir is decided by the channel conduction of the Fe-DE FinFET.
Once the bit-coded pulse streams are applied to the reservoir input, the state of the reservoir is dependent on the input patterns and can be used to analyze the input.Subsequently, we analyze the state of the devices upon application of a pulse train.In case 1, we apply two pulses in the first and second time frames consecutively and check the state of the channel conductance at the read time frame.A few electrons are still trapped in gate stack layers, and the conductivity is relatively low (Figure 4a).In case 2, when we apply two pulses in the first and third time frames, more electrons reside, indicating a higher conductivity (Figure 4b) than that in the former case.When we apply two pulses in the first and fourth time frames, more electrons reside, indicating a very high conductivity (Figure 4c).These scenarios are akin to what happens in the case of a recurrent node with a recurrent weight having a magnitude less than 1. [39] By the read time frame, the read node states decrease once and twice in the second and first cases, respectively.In the third case, the read node returns to the original state by a pulse in the fourth time frame, thereby there is no reduction.
Next, we devised experiments to test the response of the Fe-DE FinFET-based reservoir to 4-bit patterns.The 4-bit patterns were encoded into a program voltage (V Pro ) pulse stream, where the high bits are represented by a high pulse of 2 V with a program pulse width (t Pro ) of 100 ms and low bits are represented by 0 V.The state of the device is read after the application of the encoded pulse stream through a À0.1 V read voltage (V Re ) with a 10 ms pulse width (t Re ).Subsequently, the dynamic states of 28 devices with 16 different program sequences were extracted, as shown in Figure 4d, indicating distinguishable reservoir states and good uniformity distribution.The coefficient of variation (CV) shown in Figure S3, Supporting Information, can also confirm the good uniformity of the device-to-device variation and cycle-to-cycle variations. [40]Next, 16 dynamic states of the devices were investigated with different pulse widths.As the V Pro /V Re pulse width decreased to 100 μs/10 μs (Figure S4, Supporting Information), distinguishable reservoir states were also achieved (Figure 4e).A minimum ultralow energy consumption of %2 fJ per synaptic spike was achieved for V DS = À0.1 V with a 10 μs read pulse and drain current of %2 nA (Figure S4, Supporting Information).Furthermore, good cycle-to-cycle uniformity within 10 5 cycles due to DE helps to eliminate the error source in an RC system (Figure 4f ).
Next, we investigated the characteristics of the devices in the hybrid Fe-DE model for the readout layer in the RC system.We adopted V Pro = þ4 V/1 μs and À3 V/1 μs and V Re = À0.1 V/1 μs to ensure Fe polarization switching.As shown in Figure 4g, the device conductivity increases gradually with a series of positive V GS pulses, indicating LTP.Furthermore, the device conductivity decreases gradually with a series of negative V GS pulses, indicating LTD.This indicates the successful construction of LTP and LTD functions in biosynapses with the hybrid Fe-DE mode in the devices.Sequential V GS pulses with various V Re amplitudes were adopted to optimize the linearity.Figure 4h shows how the synaptic weights are updated with a different set of programmed and read conditions in the devices.The nonlinearity (NL) of the weight update is defined as [41,42] NL ¼ where G p (n) and G d (n) are the conductances after the nth potentiation pulse and nth depression pulse, respectively.A low NL value of 0.1 is achieved at À0.35 V Re for LTP and À0.55 V Re for LTD for devices operating with pulses AE4 V/1 μs.Such a small asymmetry will effectively improve the online learning accuracy of the device.Reliable four-level conductance states were measured in the devices.Figure 4i shows the distribution of four distinct Fe-FinFET states within 10 4 cycles with a large read noise margin.The horizontal axis represents the device conductivity, which is in the form of the sensed current under a À0.1 V-read voltage, and the vertical axis represents the count.This graph shows nonoverlapping conductance distributions between the four states and indicates the good multilevel performance of the fabricated devices.Notably, a higher weight can be achieved in a long-term memory cell with multiple devices.

Homogeneous RC System Based on Fully Fe-DE FinFETs
Next, we constructed and simulated an RC system consisting entirely of Fe-DE FinFETs based on the aforementioned observations.Figure 5a shows a typical RC network that consists of an input, reservoir, and readout layers.Figure 5b shows the data flow and network schematic for an MNIST handwritten digit classification task, which consists of a reservoir computing layer and readout layers.Twenty-eight different Fe-FinFETs are used for the reservoir in parallel for the high-dimensional feature space.The reservoir output is transferred to a readout layer with 10 Fe-DE FinFETs.Each MNIST handwritten digit image has 28 Â 28 pixels.The original 28 Â 28 image is binarized and cropped to a size of 1 Â 28 before being divided into seven columns that are sequentially joined with each other.Before classification, each frame of the handwritten digit in the MNIST dataset is preprocessed into voltage pulse sequences, which are fed into the reservoirs in parallel.The dynamics of the devices enable the reservoir to faithfully extract critical features from the inputs without extra training.The extracted features are inherently encoded in the form of a voltage that is then provided to the Fe-DE FinFET-based readout layer.A supervised learning algorithm, linear regression, was used to train the readout functions for classifying. [10]fter the training, the network correctly classified 97.53% of the MNIST test set.The corresponding loss is shown in Figure 5d, indicating converged network weights after 200 epochs.The experimental recognition accuracy of the Fe-FinFETs in the RC system reaches 97.53%, showing the potential application of this compact and homogeneous system.Table 1 compares the performances of the Fe-DE FinFET-based RC network with those in other reports in terms of device type, energy, and CMOS compatibility.The versatility of the compact synapses provides a more competitive approach to building highly efficient RC neuromorphic hardware systems with lower power consumption and lower hardware cost.

Conclusions
We have proposed a compact artificial synapse based on a single versatile Fe-DE FinFET.With inherent film properties of Fe domains and oxygen vacancies, compact artificial synapses featuring both STP and LTP were simultaneously realized in a single Fe-FinFET.An ultralow energy consumption of %2 fJ per synaptic spike was realized, thus enabling strong control of static electricity of advanced CMOS FinFETs, which makes them compatible with their biological counterparts.Furthermore, a homogeneous RC system was constructed whose synapses all consisted of such Fe-DE FinFETs.This system achieved increased recognition accuracy (97.53%) for digit classification with lower hardware cost.This work is meaningful for constructing an energy-efficient RC system with low hardware cost in the future.

Experimental Section
Device Fabrication: Fe-DE FinFETs were fabricated on 200 mm Si (100) wafers.Self-aligned double patterning was used to form an ultrathin fin with a relaxed pitch.Conventional shallow trench isolation (STI) and punch-through stop doping were performed on the fin.Amorphous-Si dummy gates with gate lengths of 500 nm were fabricated through a direct-write electron beam and dry etching.Dummy gate planarization and removal were performed after the deposition of an interlayer dielectric (ILD).After the IL formation, a sequential atomic layer deposition (ALD) of multilayer Hf 0.5 Zr 0.5 O 2 /TiN/TaN/TiN/W was performed, where the Fe Hf 0.5 Zr 0.5 O 2 material replaced the normal high-κ HfO 2 film, and the metal gate remained the same.The IL was formed by O 3 oxidation with high passivation.A uniform 9 nm-thick Hf 0.5 Zr 0.5 O 2 film was deposited by alternately introducing Hf-and Zr-based organic precursors.Subsequently, an SD metal contact with the W-plug and alloy was formed.
Electrical Measurements: The P-V curves were measured with a Fe analyzer (TF Analyzer 3000).The C-V and I DS -V GS curves were measured with a semiconductor parameter analyzer (Keithley 4200 A-SCS).The V GS pulses were generated by an Agilent B1500 module, and the subsequent I DS -V GS curves and transit I DS -t curves were measured with an Agilent B1500 semiconductor parameter analyzer.
Fe-FinFET-Based Reservoir Computing: The RC system was tested with in-house python codes using the PyTorch package.A handwritten MNIST digit dataset with 50 000 training images and 10 000 test images was rearranged from 28 Â 28 pixels into 196 voltage pulses of 4-bit signals.
The input pulses were transferred to 5488 output features through 28 different Fe-FinFET reservoir nodes.These features were fed into an LTP-synapse-based readout layer constructed with ten transistors using a simple linear regression algorithm.Stochastic gradient descent (SGD) optimization was applied with a learning rate of 0.02.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.Table 1.Benchmarks of our RC system with those of other works.

Figure 1 .
Figure 1.a) Schematic of multifunctional biosynapses.b) Influx of Ca 2þ through N-methyl-D-aspartate receptor (NMDAR) and extrusion via Ca 2þ -ATPase (PMCA) in STP.c) Accumulation of Ca 2þ inside the postsynaptic membrane and modification of synaptic strengths by changing the number and/or conductance of α-amino-3-hydroxy-5-methyl-4-isoxazole-propionic acid receptors (AMPAR).d) Diagram of the proposed compact Fe-DE Fe fin FET (FinFET) synapses, which can work in e) separate DE mode with 0 < V GS < V C for STP and f ) hybrid Fe-DE mode with V GS > V C for LTP.

V
Ini was set to À5 V to saturate the initial polarization states and charges.The delay between the write and read pulses was approximately 1 s.To avoid sweeping-voltage effects on Fe and DE states, the sweep voltages had smaller absolute values than those of V Pro .The I DS -V GS curves were measured under various V Pro amplitudes (2-5 V with a 1 V step and 100 ms pulse width).The decrease in |V T | as V Pro increases from À5 to 3 V indicates electron trapping in the gate stacks under positive V Pro .The subsequent increase in |V T | with increasing V Pro indicates Fe polarization switching, which compensates for the electric field produced by trapped charges.The V T values are extracted at a fixed I DS of 1 μA.

Figure 2 .
Figure 2. a) STEM-HAADF image of the m-phase inside an o-grain projected along the [010] direction.b) GIXRD spectra collected from the HZO films with reference patterns for the o-, t-, and m-phases of HZO.c) EELS plasma spectrums show the existence of DE (V o ).d) TEM image of an Fe-DE FinFETand corresponding e) energy-dispersive X-ray spectroscopy maps for Si, O, Zr, and Hf for a p-type Fe-DE FinFET.f ) I DS -V GS characteristics of a Fe-FinFET after an initial V GS application of À5 V at different V Pro amplitudes.g) Extracted V T s from (f ).h) Retention characteristics of multistates induced by the charge trap and Fe domain switch corresponding to (f ).i) Stimulating the device with a 1.5 V pulse with a constant width of 10 ms produces a DE-induced short-term potentiation.j) Stimulating the device with a 2.5 V pulse causes a transition from the DE-induced short-term to the DE-induced long-term potentiation.k) Stimulating the device with a 3.5 V pulse produces an Fe-induced long-term depression.
Figure 3a,d shows the projected density of states (PDOS) of the slab model working in the separate DE mode with original polarization and the hybrid Fe-DE coupling mode with switched polarization, respectively.The bandgaps of Si and SiO 2 are found to be approximately 1.1 and 9 eV, respectively, and the band edge of the Hf 0.5 Zr 0.5 O 2 zone is different owing to the opposite polarization.Because the Fe polarizations are different, the fully relaxed interfaces between Hf 0.5 Zr 0.5 O 2 and SiO 2 are not the same.Therefore, to investigate the Fe-DE coupling, different V o s are adopted in the devices under different working modes.For the interface, two types of V o s (O 1 , O 2 ) are assumed in the hybrid mode (as shown in Figure 3b), while three types of V o s (O 1 , O 2 , O 3 ) are assumed in the separate DE mode (as shown in Figure3e).

Figure 3 .
Figure 3. Atomic-level first-principles simulations of a Si/SiO 2 /Hf 0.5 Zr 0.5 O 2 /TiN stack.a,d) Projected density of states (PDOS) of a TiN/HZO/SiO 2 /Si gate stack with different Fe polarizations; the Heyd-Scuseria-Ernzerhof level is adapted in the calculations.b,e) Side views of SiO 2 /Hf 0.5 Zr 0.5 O 2 interfaces with two different Fe polarizations; the oxygen vacancies around the interface are marked.c,f ) Formation energy of oxygen vacancy DE.

Figure 4 .
Figure 4. Schematic of the set waveforms.A 10 ms, 2 V pulse signifies 1, whereas a 0 V pulse signifies 0. The 4-bit patterns are encoded in the form of four pulses.After the pulse pattern is applied with a 4-bit pattern encoded, the memristor state is read with a À0.8 V pulse.The top panel shows the pattern.The bottom panel shows the current responses of the reservoir to the applied bit patterns.The applied bit patterns are a) 1100, b) 1010, and c) 1001.d) Distribution of current responses of 28 devices corresponding to all possible 4-bit inputs, showing good uniformity.e) Cycle-to-cycle uniformity of 10 5 cycles for 16 Fe-DE FinFET-based reservoir states.f ) Distribution of current responses of a chosen device with pulse widths of 10, 1 ms, and 100 μs.g) Analog synaptic behaviors of the Fe-DE FinFET in Fe mode: gradual tuning of channel conductance under þ4 and À3 V at 100 ms pulses for (left) potentiation and (right) depression operations.h) Synapse weight tuning using voltage pulses of AE4 V/1 μs.i) Distributions of the four distinct conductance states.

Figure 5 .
Figure 5. Schematic of the Fe-DE FinFET-based dynamic reservoir for classifying MNIST-based temporal sequences.a) Schematic of an RC network.b) The original 28 Â 28 image is binarized and cropped to a size of 1 Â 28 before being divided into five columns that are sequentially joined with each other.The resultant input of 196 is then converted to 4-bit temporal voltage patterns as inputs to the readout layer.The current responses of the are used to in situ train the Fe mode readout c) Training loss and d) accuracy as of training epoch based on simulation of the RC system.