Experimental Simulation of Topological Quantum Computing with Classical Circuits

The key obstacle to the realization of a scalable quantum computer is overcoming environmental and control errors. Topological quantum computation attracts great attention because it emerges as one of the most promising approaches to solving these problems. Various theoretical schemes for building topological quantum computation have been proposed. However, experimental implementation has always been a great challenge because it has proved to be extremely difficult to create and manipulate topological qubits in real systems. Therefore, topological quantum computation has not been realized in experiments yet. Herein, the first experimental simulation of topological quantum computation with classical circuits is reported. Based on the proposed new scheme with circuits, not only Majorana‐like edge states are simulated experimentally, but also T junctions are constructed for simulating the braiding process. Furthermore, the feasibility of simulated topological quantum computing through a set of one‐ and two‐qubit unitary operations is demonstrated. Finally, the simulation of Grover's search algorithm demonstrates that simulated topological quantum computation is ideally suited for such tasks. The developed circuit‐based topological quantum‐computing simulator can provide important references for developing future topological quantum circuits.


Introduction
[3][4][5] Building a practical quantum computer has always been the goal of people.However, it is notoriously hard to build such a device due to the ubiquitous decoherence of quantum states and error rendering.At present, there are two propositions to solve these problems.8][9][10][11][12][13][14] Such a scheme is extremely difficult to implement because it requires a lot of additional resources for quantum circuits.Another way is to perform a topological quantum-computing scheme.
[17][18][19] Majorana-like zero modes are experimentally the simplest realization of anyons that can nontrivially process quantum information.Based on the scheme of Majorana-like zero modes, some potential realizable systems have been analyzed theoretically, such as superconductor and fractional quantum Hall liquid, [20][21][22][23][24][25][26][27] semiconducting heterostructures and wires, [28][29][30][31][32][33] photonic networks, [34][35][36] electric circuits, [37] and so on.However, the experimental implementation has encountered great challenges, although some simulations of braiding zero modes can be accomplished in acoustics and photonic systems experimentally. [38,39]The simulation of topological quantum computation requires to braid zero modes many times, which is beyond the capability of these physically classical simulators.In addition, according to the circuit scheme as described in ref. [37], not only do the variable capacitor and inductor need to be precisely regulated at the same time, but also the whole braiding operation needs to be completed in a very short time.This is because the input signal decays quickly due to the loss of circuit components.Therefore, it is very difficult to accomplish in experiments.How to simulate topological quantum computation experimentally is still an open problem.
In this work, we propose a new classical circuit scheme to overcome the problems of the previous schemes.We construct a resistor-capacitor (RC) circuit instead of an inductor-capacitor (LC) circuit.In our designed RC circuits, the task can be DOI: 10.1002/aisy.202300354 The key obstacle to the realization of a scalable quantum computer is overcoming environmental and control errors.Topological quantum computation attracts great attention because it emerges as one of the most promising approaches to solving these problems.Various theoretical schemes for building topological quantum computation have been proposed.However, experimental implementation has always been a great challenge because it has proved to be extremely difficult to create and manipulate topological qubits in real systems.Therefore, topological quantum computation has not been realized in experiments yet.Herein, the first experimental simulation of topological quantum computation with classical circuits is reported.Based on the proposed new scheme with circuits, not only Majorana-like edge states are simulated experimentally, but also T junctions are constructed for simulating the braiding process.Furthermore, the feasibility of simulated topological quantum computing through a set of one-and two-qubit unitary operations is demonstrated.Finally, the simulation of Grover's search algorithm demonstrates that simulated topological quantum computation is ideally suited for such tasks.The developed circuit-based topological quantum-computing simulator can provide important references for developing future topological quantum circuits.completed only by adjusting the resistance, without precise adjustment of capacitances and inductances at the same time.Based on such classical circuits, we simulate both theoretically and experimentally Majorana-like edge states and construct T junctions for simulating braiding process.In addition, we use segmented fixed resistances to replace variable resistances, which allows the whole braiding process to be completed before the signal is attenuated.A set of one-and two-qubit unitary operations is simulated experimentally by the braiding operations.Furthermore, we fabricate integrated circuits for the simulation of topological quantum computation to simulate Grover's search algorithm.

Classical-Circuit Simulation of Non-Abelian Braiding of Majorana-Like Edge States
Constructing Majorana-like zero modes and braiding process are the key steps to realize topological quantum computation.[25][26][28][29][30][31][32][33][34][35][36][37] The Kitaev model is the fundamental 1D model hosting Majorana-like zero modes.The Hamiltonian of the Kitaev model is expressed as where t, μ, ϕ 0 , and Δ represent the hopping amplitude, chemical potential, superconducting phase, and gap parameters, respectively.It is well known that the system is topological for jμj < j2tj and trivial for jμj > j2tj.A pair of topological zero-energy states emerges at the edges of a topological phase according to the bulk-edge correspondence.They are protected by particle-hole symmetry.Their properties are identical to Majorana zero modes in p-wave superconducting.The theoretical correspondence is shown in Section S1, Supporting Information.Now, we discuss how to design the classical circuit to simulate such a model.The designed classical circuit network can be described with the help of Figure 1a. Figure 1a shows the classical circuit with two units simulating the Kitaev model, each unit cell contains four circuit nodes (A-D).42][43][44][45][46][47][48][49][50][51] The blue and red lines in Figure 1a represent the connections between nodes in two units, which simulate two kinds of intercell couplings.The detailed connection modes are described in Figure 1b.The blue and red arrows in Figure 1b  with the resistance R c is shown in the green box of Figure 1c.The red and blue dots on the green lines in Figure 1a are switches that can determine whether the coupling exists or not, which are displayed in the black box of Figure 1c.In addition, proper grounding elements should be connected to each node.Details of the grounding parts are shown in Section S2, Supporting Information.For the aforementioned circuit network, we can derive a circuit Laplacian by Kirchhoff 's law where , and C is capacitance connecting to the ground.Here, ϕ is circuit phase which determines the change of variable resistor, simulating the "superconductor phase ϕ 0 " in the Kitaev model.If we choose the parameters to be Laplacian J can be obtained as corresponds exactly to the form of the Kitaev lattice model.In the methods of Experimental Section, we give the detailed demonstration of such a correspondence.However, in the following analysis, we consider J instead of J K k ð Þ.This is mainly due to two reasons.On the one hand, J contains all the information of J K k ð Þ.The initial state and evolution equation of J can be derived with the help of J K k ð Þ (see the methods in Experimental Section); on the other hand, it is convenient to implement experimentally.In contrast to J K k ð Þ, which has complex parameters, J only has real parameters.In this case, all coupling terms in J can be controlled by only regulating the resistances.
Based on such correspondence, we can simulate Majoranalike zero modes in the Kitaev model using classical circuits.Because the resistance R c in the circuits corresponds to the parameter μ in H K k ð Þ, we can generate a circuit segment with topological or trivial phase by only controlling R c .If 4R c < R b , the circuit segment has the trivial phase.If there is no intracell coupling, it has the topological phase.For the circuit network with topological and trivial phases, a topological edge state can emerge at the boundary between the trivial and the topological segment by feeding an external current to the network.By switching on the intracell coupling in the adjacent unit cell, a topological edge state is shifted to the adjacent unit cell.That is, we can move a topological edge state freely along the circuit network.
For example, we consider a classical circuit network with 10 units, which are labeled from 1 to 10. From 3 to 8, all units have topological phases, the units from 1 to 2 and 9 to 10 have trivial phases as shown in Figure 1d (see top marks).To see the evolution of electrical signals in such a structure, we input positive voltage to node C in unit cell 3, and nodes A and B in unit cell 8.The negative voltage is input to node D in unit cell 3.The rest of the nodes are connected to the ground.The voltage excitations simulate the initial state in the lattice model.Detailed discussion is given in the methods of Experimental Section.After the voltages are excited, we immediately disconnect the input voltages simultaneously and measure the voltage distributions at various nodes.The simulation results are shown in Figure 1d.Here, the evolution 6 ms is taken before the signal decays.It is seen clearly that a pair of topological edge states emerge at the edge of the topological segment (units 3 and 8), which corresponds well to the distribution of edge states in the lattice model.Furthermore, we fabricate the corresponding circuit network, which its photograph is shown in Section S3, Supporting Information.Figure 1e shows the experimental result of voltage distribution.For comparison, we find that the experiment and simulation results are basically identical.The differences between them come from the loss of the circuit and the error of components.Furthermore, to eliminate the influence of initial voltage on voltage distributions, we also input corresponding initial voltages to unit cells 2 and 9, the results of voltage distributions are exhibited in Section S4, Supporting Information.The edge states also emerge at the edge of the topological segment.This means that Majorana-like zero modes are successfully simulated in our designed circuit.
Based on the aforementioned edge states, we can simulate a braiding process by employing a T junction [29] as shown in the left panel of Figure 2a.The T junction provides the simplest wire network that enables the meaningful adiabatic exchange of Majorana-like zero modes.It has three legs (1-2, 2-3, and 2-4) made of Kitaev chains.The blue and brown colors correspond to topological and trivial segments, respectively.Such a T junction model can also be simulated by designing the circuit.The designed circuit network is shown in the red box of Figure 2a.The marks (1, 2, 3, and 4) in the circuit network correspond to those in the T junction model one by one.Legs 1-2 and 2-3 have the same structure as the circuit network in Figure 1a, in which the circuit phase is taken as ϕ ¼ 0. The leg (2-4) has a variable phase ϕ.In the leg (2-4), there are four units and three kinds of intercell couplings (purple, red, and brown lines).The couplings marked by red are identical to those in Figure 1b.The detailed connections for the other couplings (purple and brown lines) are shown in the right panel of Figure 2a.Their corresponding structures of arrows are given in Figure 2b.Unlike the others, the connection represented by the purple arrow contains two INICs.This is because they correspond to variable resistances R a cos À1 ϕ with ϕ from 0 to π.When the ϕ changes from 0 to π=2, the upper INIC works.For the case from π=2 to π, the lower INIC works.In addition, proper grounding elements should be connected to each node.Details of the grounding parts are shown in Section S5, Supporting Information.For such a circuit network, we can also demonstrate that its Laplacian corresponds to the Hamiltonian of Kitaev chain with a variable phase ϕ, which a detailed description is also given in the methods of Experimental Section.Furthermore, we also fabricate the corresponding circuit network, whose photograph is shown in Section S6, Supporting Information.
From the circuit T junction, the designed braiding process is shown in Figure 2c.The simulated braiding process which contains state transfer and phase rotation for two edges includes eight steps from I to IX.Before starting the braiding process, we set the initial state by regulating the switches in intracell couplings.The legs from 1 to 2 and 2 to 3 have topological phases.From 2 to 4, the leg has a trivial phase.The edge states appear at 1 and 3.In addition, we set ϕ ¼ 0 in all legs.Then, we make the edge states evolve with time by regulating the switches.For example, in the step from I to II, the edge state moves from 3 to 2 by gradually closing the switches on the leg 2-3.In such a case, leg 1-2 (2-4) remains topological (trivial) segment, but leg 2-3 becomes a trivial segment.The edge states appear at 1 and 2. In the step from IV to V, the phase of leg 2-4 is from ϕ ¼ 0 to ϕ ¼ π.In the steps from I to IV and V to VIII, edge states transfer with time.From IV to V and VIII to IX, the phase rotation is performed.A detailed description of all steps and voltage evolution can be seen in the methods of Experimental Section.After eight steps, the braiding process is achieved with the result ) represents voltages at the marked positions (1 and 3) in the T junction.The green and blue cylindrical lines in Figure 2c display recorded positions of edge states at each step, where the transfer (braiding) process for two edge states is clearly shown as a function of time.
To quantitatively describe the aforementioned simulated braiding process, we calculate the energy eigenvalue of the circuit T junction in eight evolution steps.The results are plotted in the upper panel of Figure 2d.It shows that the energy of the edge states remains zero during the process and they are well separated from all other states, which means the adiabatic evolution of the whole braiding process.The most important property of the topology is that it is robust against perturbation.To demonstrate this effect, we construct 10% coupling randomness.The corresponding energy eigenvalue is shown in Section S7, Supporting Information.The energy of the edge states is also well separated from the bulk spectrum, which indicates that the braiding process is robust against perturbation.In addition, in the down panel of Figure 2d, we plot ϕ as a function of evolution steps.The purple line and the red marks are theoretical and experimental results, respectively.The phase rotation from ϕ ¼ 0 to ϕ ¼ π is observed in the steps from IV to V, which corresponds to the case of state transfer as shown in Figure 2c.
To better describe the simulated braiding process, we measure the braiding matrix.The braiding matrix has the form e iπ=4 in the qubit representation, which indicates the braiding for zero modes γ 0 i and γ 0 j .It exhibits a function of a π=2 phase gate.In Section S8, Supporting Information, we give a detailed description of the braiding matrix under the framework of quantum theory.In fact, the corresponding braiding matrix can also be obtained in the circuit.If we define  V 1 þ iV 3 !j0Þ and V 1 À iV 3 !j1Þ to represent the initial states, which correspond to j0i and j1i in the qubit representation, the derived braiding matrix in the circuit corresponds exactly to the form of the matrix under the framework of quantum theory.The detailed derivation is given in Section S9, Supporting Information.Here, the states in the article are described by a slightly modified version of the familiar bra-ket notation of quantum mechanics.The real and imaginary parts of output voltages V j0Þ and V j1Þ in the experimental braiding matrix are shown in Figure 2e.
Þindicates the output voltage after the braiding matrix acts on the initial state jiÞ.The parameters in the experiment are identical with aforementioned in Figure 1e.It is clearly seen that indeed the input states for j0Þ and j1Þ are successfully transformed into 1= ffiffi ffi , respectively.It corresponds to the result of π=2 phase gate.To further quantify the experimental result, we calculate the fidelity of the braiding matrix, which is expressed as F H ¼ j ϕjM th M exp jϕ À Á j 2 with M th and M exp being the theoretical and experimental results for matrixes and jϕÞ is defined as state j0Þ or j1Þ.A high fidelity with F ¼ 0:98 AE 0:0069 is obtained, which clearly confirms that our implementation of the braiding process has a good performance.

The Simulation of Single-Qubit Unitary Operations
Based on the T junction and braiding process simulated earlier, we can perform basic gate operations for simulating topological quantum computation.It has been demonstrated that the combination of some single-qubit and two-qubit gates can generate any unitary transformation. [52,53]In this section, we first discuss the circuit simulation of the single-qubit unitary operations.Hadamard (H) gate, X gate, and Z gate are the basic single-qubit gates.According to the theory of topological quantum computing, two pairs (four) of Majorana-like zero modes are required to construct a qubit.For example, the left panel in Figure 3a shows the theoretical scheme of the H gate based on four zero modes, which are marked as γ Such a scheme for the H gate can also be simulated by designing the electric circuit.The designed circuit is shown in the right panel of Figure 3a, in which two pairs (four) of edge states simulating Majorana-like zero modes γ 1 , γ 2 , γ 3 , and γ 4 are used.The braiding of these edge states also needs three exchange operations using T junctions, which correspond to the case in the left panel of Figure 3a one by one.Detailed theoretical descriptions of the correspondence between the quantum scheme and circuit theory for the H gate are shown in Section S10, Supporting Information.In addition, we find that two kinds of braiding processes are needed to construct an simulated H gate operation: braiding two edges across a topological segment (from γ 1 to γ 2 and from γ 3 to γ 4 ) and a trivial segment (from γ 2 to γ 3 ).The braiding across a topological segment is identical with the aforementioned in Figure 2c.In the methods of Experimental Section, we describe all steps of the braiding across a trivial segment.
Furthermore, we fabricate the corresponding circuit network to measure matrix of output voltages for the simulated H gate in the experiment.The measured results for the real and imaginary parts of output voltages are given in Figure 3b.The parameters are identical with the aforementioned in Figure 2e.It is clearly seen that the input states for j0Þ and j1Þ are successfully transformed into j0Þ þ j1Þ and j0Þ À j1Þ, respectively, which corresponds to the result of the H gate in the quantum scheme.The fidelity for the measured matrix can be obtained as F ¼ 0.9875 AE 0.0083.Such a high fidelity further indicates that the function of the H gate is well implemented.Detailed experimental data for the simulated H gate are also given in Section S10, Supporting Information.
We also exhibit the braiding for the simulated Z gate in Figure 3c.The theoretical scheme in the left panel indicates that  two exchange operations are needed to braid the Z gate.The right panel of Figure 3c shows the designed circuit, in which the braiding of edge states corresponds to the theoretical scheme.In addition, the results of the measured matrix for the simulated Z gate in the experiment are shown in Figure 3d.It can be seen that the input states for j0Þ and j1Þare successfully transformed into j0Þ and Àj1Þ, respectively, in which the fidelity is F ¼ 0.9410 AE 0.0102.This means that the Z gate is also successfully simulated in our circuit experiment.The detailed theoretical descriptions and experimental results for the simulated Z gate are given in Section S11, Supporting Information.In addition, we also design and measure the simulated X gate in the circuit.The experimental results also correspond well with the theoretical scheme.The details can be seen in Section S12, Supporting Information.

The Simulation of Two-Qubit Gates Unitary Operations
We now provide the circuit design to simulate two-qubit unitary operations.Two basic two-qubit gates are considered: the CNOT gate and the gate.Three pairs (six) of Majorana-like zero modes are required to realize two-qubit operations.The left panel of Figure 4a shows the theoretical scheme for the CNOT gate, in which the Majorana-like zero modes are marked as γ The results of the measured output voltage matrix for the simulated CNOT gate in the experiment are shown in Figure 4b.The parameters are identical with the aforementioned, in Figure 3b.We use , and V γ 1 À iV γ 2 ⊗ V γ 5 À iV γ 6 !j11Þ to represent the initial states, which correspond to j00i, j01i, j10i, and j11i in the quantum scheme.It is clearly seen that the input states for j00Þ, j01Þ, j10Þ, and j11Þ are successfully transformed into j00Þ, j01Þ, j11Þ, and j10Þ respectively.The fidelity of the simulated CNOT gate can be obtained as F ¼ 0.9089 AE 0.0107, indicating a nice performance of the CNOT function.Detailed experimental data for the simulated CNOT gate are also shown in Section S13, Supporting Information.
Figure 4c displays the theoretical scheme and designed circuit for the simulated CZ gate.The simulated braiding of edge states in our designed circuit as shown in the right panel corresponds well to the theoretical scheme in the left panel, both of them include three exchange operations.From the experimental results of the measured output voltage matrix for the simulated CZ gate, as shown in Figure 4d, it is seen clearly that the input states for j00Þ, j01Þ, j10Þ, and j11Þ are successfully transformed into j00Þ, j01Þ, j10Þ, and Àj11Þ, respectively.The fidelity for such an operation reaches F ¼ 0.9409 AE 0.0076, indicating that the CZ gate can be successfully simulated in our circuit experiment.The detailed theoretical descriptions and experimental results for the simulated CZ gate are given in Section S14, Supporting Information.After the single-qubit and two-qubit operations have been simulated in the designed circuits, we next discuss how to perform simulated quantum algorithm based on these gate operations.

The Simulation of Grover's Search Algorithm
Grover's search algorithm is an important algorithm in quantum computation. [5]It is proved more efficient than the best classical algorithm and can solve difficult problems.The goal of Grover's search is to identify one out of N elements of a database.The success probability to find the desired outcome is 1=N with one random guess in classical strategy.So, the average time of queries in finding the desired outcome is N=2.But, inputs of Grover's search can be processed simultaneously in superposition.It enhances the probability of finding the desired outcome in only ο ffiffiffiffi N p À Á , which shows quadratic speedup to the fastest classical algorithm in searching unsorted databases.Such an algorithm is extremely important, both from fundamental and standpoints.[3] Here, we demonstrate the simulation of Grover's fast quantum search using the braiding process in the classical circuit.
The universal quantum route diagram for the two-qubit Grover's search algorithm is shown in Figure 5a.It contains four parts: input, black box, inversion, and readout.The input qubits prepared as j0ij0i j00 ð iÞ.When they pass through two H gates, a superposition of four basis states j00i, j01i, j10i, and j11i appears.One of which can be marked under the CZ and single-bit rotation gates (R z Àa ð Þ a ¼ α, β ð Þ ) in the black box, α and β represent the rotation angles.If αβ are taken as 00, 0π, π0, and ππ, the corresponding marks in the black box are j00i, j01i, j10i, and j11i, respectively.In principle, the marked state remains hidden.The goal of Grover's search is to identify the marked state by the inversion part.The inversion part inverts the amplitudes for each state about the mean value which can amplify the labeled amplitude and reduce the rest.After it, the marked state can be read out with probability 1 in theory.It indicates that Grover's algorithm needs only one calculation to identify the hidden marked state in the black box, whereas three evaluations are needed in the worst case for the classical search scheme, and 2.25 evaluations are needed on average.
The corresponding braiding process we designed for simulating the two-qubit Grover's search algorithm is shown in Figure 5b with αβ ¼ 0π.Other cases (00, π0, and ππ) are described in Section S15, Supporting Information.Such a scheme for the topological quantum computation corresponds to the universal quantum route diagram as shown in Figure 5a  ) and braiding process are used in the topological quantum computation scheme.The detailed theoretical descriptions for such a scheme are also given in Section S15, Supporting Information.
Furthermore, we design and fabricate circuit networks to implement such a scheme.In Section S16, Supporting Information, we provide the photograph of designed and fabricated circuits to simulate the scheme as shown in Figure 5b.Our fabricated circuit corresponds to the theoretical scheme.Five T junctions are used to construct three pairs (six) of Majorana-like zero modes.By regulating the switches of resistances, we achieve the function of braiding process for edge states.After the whole braiding process, we measure the voltage of each node in T junctions.Using these voltages, we obtain the evolution in the circuit for Grover's search algorithm based on the braiding theory in Section S9, Supporting Information.When they act on the initial state after normalization, the output is shown in Figure 5c for various marked states of Grover's search algorithm.Here, the parameters are taken identically with those in Figure 4b.The corresponding circuit theory and experimental data are given in Section S17, Supporting Information.The bottom in Figure 5c marks four states, j00Þ, j01Þ, j10Þ, and j11Þ, which

Marked states in black box
The ratio of voltage correspond to the cases with αβ ¼ 00, 0π, π0, and ππ in the black box, respectively.Different colors of square cylinders represent the ratio of the four states in the input and output with only one evolution.For example, if we set αβ ¼ 00, which indicates that the marked hidden state is j00Þ, the four square cylinders in the input are equally high which indicate the superposition of four basis states j00Þ, j01Þ, j10Þ, and j11Þ.But the red square cylinder in output that represents the output probability of j00Þ is extremely higher than the others.It clearly shows that the amplification of the marked state is amplified.So, we need only one evolution to identify the hidden marked state in the black box, whereas classically three evaluations are needed in the worst case, and 2.25 evaluations are needed on average.In addition, the ratio of the correct outcome is above 90% in the present cases.These high-fidelity results constitute, to our knowledge, within the theoretical scheme of topological quantum computation, the first simulation of a quantum search algorithm using an electronic circuit-based physical classical simulator.In addition, although only two-qubit Grover's search is achieved in experiment, according to our scheme, we can achieve Grover's search with any qubit using more Majorana-like zero modes.

Discussion and Conclusion
We have provided a new circuit scheme to simulate topological quantum computation.Based on such a scheme, Majorana-like edge states have not only been simulated experimentally, but also T junctions have been constructed for simulating the braiding process.Furthermore, a set of one-and two-qubit unitary operations has been simulated experimentally by the simulated braiding operations.Our final simulation of Grover's search algorithm strongly underlines the feasibility of such a scheme for simulated topological quantum computation.
The reason why we can design the circuit to implement the scheme of the topological quantum computation is that there is a good correspondence between the circuit Laplacian and lattice Hamiltonian.[42][43][44][45][46][47][48][49][50][51] In fact, qubits, unitary transformation, superposition, and entanglement required by quantum computation can also be simulated using the circuit, as we have shown.Although our scheme is regarded as "simulation of topological quantum computing with classical circuits", it has the same advantages as those of quantum computing.From a resource perspective, in the implementation of topological quantum computing, the gate unitary operations can be achieved by the braiding of Majorana zero modes at both sides of the Kitaev chain.However, 2N Majorana zero modes can construct NÀ1 independent quantum bits.Each Kitaev chain can generate two zero energy modes.Therefore, the number of qubits generated is linearly related to the number of zero energy modes on the Kitaev chain.Our electronic-circuit-based physical classic simulator also has such relationship.Moreover, for our simulation of Grover's algorithm, we need only one evolution to identify the hidden marked state in the black box, whereas in an electronic digital computer, three classical evaluations are needed in the worst case, and 2.25 evaluations are needed on average.From a stability perspective, in our electronic-circuit-based physical classical simulator, we use topological edge states to perform the braiding, and then simulate the function of quantum gate in quantum computing.Although disturbances in the Kitaev chain can change the voltages of edge states, they do not affect the existence of edge states.Therefore, the functions of braiding process and the corresponding quantum gate operations cannot be affected.For example, when 5% error occurs in the Kitaev chain, the edge states at both ends of a circuit-based classical simulator change.However, after the braiding process, a high fidelity with F¼ 0:976 is obtained.When considering an electronic digital computer, we add 5% error when simulating braiding gate, the fidelity becomes 0.898.Obviously, due to the topological characteristics, our circuit-based classical simulator has better stability and can perform quantum-computing tasks more conveniently.Therefore, we can see that the usefulness of our electronic circuit-based physical classical simulator for developing future quantum circuits beyond what could be investigated with an electronic digital computer.
Compared with other schemes, our classical circuit system has the advantage of being relatively small in size.We achieve the braiding process using a 2D circuit structure which is 30 Â 35 cm.The size of 3D structure that achieve braiding in an acoustic system [38] is about 3.6 Â 3.6 Â 180 cm.In addition, although braiding can be simulated in other classical systems, it is difficult for them to achieve quantum gates and quantum computations.In addition, circuit networks possess remarkable advantages of being versatile and reconfigurable, and classical circuit technology is relatively mature.Arbitrary strength and position of coupling only requires adjusting the value and connection way of the component to achieve.So, it is much easier to achieve corresponding coupling than acoustic and optical systems. [38,39]n addition, if topological quantum computation can be simulated using electric circuits, it is expected to avoid some problems faced by the present quantum computation schemes, such as decoherence and scalability.In addition, the energy loss caused by resistances in the circuit network can also be supplemented by connecting to the power.That is, the constructed system can work stably.Thus, our work paves the way for the construction of a practical and robust fast information processing system to serve society.

Experimental Section
Sample Fabrications: We exploited the electric circuits by using PADs program software, where the PCB composition, stackup layout, internal layer, and grounding design were suitably engineered.It was worthy to note that the ground layer should be placed in the gap between any two layers to avoid their coupling.Moreover, all PCB traces had a relatively large width (0.5 mm) to reduce the parasitic inductance and the spacing between electronic devices was also large enough (1.0 mm) to avert spurious inductive coupling.INIC was constructed with the help of opamp, for which the model was LT1013.A relay was used to disconnect the input voltages simultaneously.In addition, we used a pin header to measure the voltage at various nodes.
Circuit Measurements: We used the DC signal source (UTP1306S) to create the required DC voltage signal.The digital storage oscilloscope (Agilent Technologies Infiniivision DSO7104B) was used to measure the voltage signal at each node simultaneously.
Circuit Simulation: Texas Instruments official Spice model of the opamp was used in the circuit simulation, and LTspice was used for numerical simulations.
Methods-The Correspondence Between the Kitaev Lattice and Our Designed Circuit: In this section, we give a detailed correspondence of the eigen-equation between the Kitaev lattice model and our designed circuit.Because the circuit structure in Figure 1a is a special case of Figure 2a with ϕ ¼ 0, in the following, we discuss the correspondence based on the circuit structure in Figure 2a.According to Kirchhoff 's law, the relation between the node current and voltage should satisfy the following equation where I m and V m are the net current and voltage of node m, respectively.
V n is the voltage of node n which is connected to the node m.R g and C g are the resistance and capacitance between the node m and ground.The R inter is the resistance between the node m and n. <n> indicates that the summation is limited within connected nodes.According to the circuit in Figure 2a, we can write the currents that flow into each node as where I n i and V n i are the current and voltage of the node i in the unit n, respectively.We assume that there is no external source, so that the currents flow into each node are zero.In this case, Equation (3) becomes We can write Equation (4) in the matrix form where Equation ( 6) can further be written as Equation ( 1).If we choose the parameters to be R can have the form as H K k ð Þ, which corresponds exactly to the form of the Kitaev lattice model.In the circuit of Figure 1a, red and blue couplings only exist.So, the circuit Laplacian can be written as which is Equation (1) with ϕ ¼ 0. Methods-The Evolution and Initial Voltage Excitation of the Circuit: We first discuss the evolving relationship between the circuit and lattice model.The evolution of the circuit's initial state V 0 0 ð Þ with time satisfies the equation where J is identical with Equation (1).We make a similar transformation on the matrix The relationships of the initial state and the finial state between J and J 1 can be written as To simulate Hamiltonian in the lattice model, we set the initial state of J 1 to be where V 2 0 ð Þ is the initial state of J K k ð Þ.We make V 2 T ð Þ be the projection of V 1 T ð Þ on 1 0 ð Þ⊗ I N , and get which corresponds to the evolution of the wave function in the lattice model.
We next discuss the initial state of the design circuit.It can be seen in Equation (1) that J contains real and imaginary parts of J K k ð Þ.After combining Equation ( 5) and ( 6), we get So, voltages in nodes A and B (C and D) in the designed circuit are the real (imaginary) parts of voltages in H K k ð Þ.We define the initial voltage V 0 0 ð Þ be where a (b) is the real (imaginary) part of the initial voltage.According to Equation ( 5) and ( 6), we have The initial state of So, we get the initial state of the design circuit where Θ ¼ 0, • • • , 0 ð Þ T .In our designed circuit, nodes A and B (C and D) are the real (imaginary) parts of the signal.So, for the circuit with ten units, we input positive voltage to node C in unit cell 3 and nodes A and B in unit cell 8.We input negative voltage to node D in unit cell 3.
Methods-Detailed Description on the Simulated Braiding Process: The whole simulated braiding process can be achieved by eight steps from I to IX as shown in Figure 2c.We now explain the eight steps from I to IX in detail.
where Θ ¼ 0, • • • , 0 ð Þ T .After the simulated braiding process I-IX, we find that these two eigenstates satisfied It has the same form as the non-Abelian statistics which is realized by the braiding process of Majorana-like zero modes.In fact, we can calculate the evolution of two simulated edge states in the simulated braiding process.For a time-dependent Schrödinger equation in the circuit If the evolution is slow enough, the adiabatic approximation can guarantee V β t ð Þ satisfies the time-independent Schrödinger equation where ε is the eigenvalue of the system.U βα is the element of multilevel Berry phase matrix where A is Berry connection matrix Berry phase matrix U is only related to Γ λ ð Þ.For our simulated braiding process I to IX, we can divide the path into k parts.The phase matrix can be expressed as where . Since our simulated braiding process is a closed path, the corresponding U is gauge invariant.For our braiding process, we can get Combined with Equation ( 20), we get the evolution results

Figure 2 .
Figure 2. The circuit design and results for the braiding process.a) Illustrations of a classical circuit for a T junction.The right panel shows the detailed connections of intercell couplings (purple and brown).The red and blue intercell couplings are identical to Figure 1b.b) The schematic diagrams for the construction of the arrows.c) The diagram of the braiding process with eight steps from I to IX.The red and black balls are the ends of the three legs in T-junction (1, 2, 3, and 4), where red balls represent the appearance of topological edge states at the ends of the legs, while black balls correspond to the case of topological trivial phase.By regulating the switches in resistances, the edge states evolve with time.d) Evolution of the energy and the variation of phase in eight steps from I to IX.We choose R a ¼ 1 kΩ, R b ¼ 1 kΩ, and R c ¼ 100 Ω. e) The output voltages of the braiding matrix.
. The scheme exhibits the braiding process as shown by the red lines, which includes three exchange operations among γ 0

Figure 3 .
Figure 3.The circuit design and results for the single-qubit computations.a,c) The left panel illustrates the theoretical scheme for the H gate and the Z gate; the right panel shows the circuit designs and transform of edge states.b,d) Output voltages of measured matrices for the H gate and the Z gate, respectively.
. The braiding process is shown by the red lines, which includes seven exchange operations.The designed circuit to simulate such a gate is shown in the right panel of Figure4a, in which three pairs (six) of edge states simulating Majorana-like zero modes γ 1 , γ 2 , γ 3 , γ 4 , γ 5 , and γ 6 are used.The simulated braiding of these edge states corresponds to the theoretical scheme in the left panel in Figure4aone by one.Detailed theoretical descriptions of the correspondence between CNOT gate in the quantum scheme and circuit theory are shown in Section S13, Supporting Information.

Figure 4 .
Figure 4.The circuit design and results for the two-qubit computations.a,c) The left panel illustrates the diagram of the CNOT gate and the CZ gate; the right panels shows the simulated braiding process.b,d) Output voltage matrices of the simulated CNOT gate and the CZ gate, respectively.
one by one.The difference is that six Majorana-like zero modes

Figure 5 .
Figure 5.The circuit design and results for Grover's search algorithm.a) The quantum diagram implementing Grover's search algorithm for two qubits.b)The theoretical scheme of Grover's algorithm with αβ ¼ 0π.c) The inputs and outputs of Grover's algorithm.The symbols "Re" and "Im" represent real and imaginary parts of j00Þ, j01Þ, j10Þ and j11Þ, which are represented as the marked state in black box, respectively.