Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Spiking neural networks (SNNs) have been researched as an alternative to reduce the gap with the human brain in terms of energy efficiency, due to their inherent spare event‐driven characteristics from a hardware implementation perspective. However, they still face significant challenges in learning, compared to artificial neural networks (ANNs). Recently, several algorithms have been developed to narrow the performance gap between SNNs and ANNs, including features in spiking neurons that can reduce information loss in the membrane potential. Inspired by these advancements, the current study designs and measures a neuron circuit using 180 nm complementary metal‐oxide‐semiconductor (CMOS) technology to address this information loss. The proposed circuit successfully implements these features, and their performance is validated through simulation based on the measured data.

[14][15][16][17] In SNNs, information is encoded in the form of spikes, which are discrete events that transmit information in both space and time, and the neurons communicate through these spikes. [18,19]When the membrane potential of a neuron accumulates over time, and reaches a certain threshold, it generates a spike, which is propagated to other neurons through synapses, as shown in Figure 1a.This behavior closely resembles the way biological neurons function, allowing SNNs to better mimic the processing capabilities of the brain.One of the key advantages of SNNs lies in their event-driven processing nature, which results in reduced power consumption and improved efficiency compared to traditional ANNs that rely on computations of continuous values. [20]Additionally, SNNs have shown promise in implementing various neural information processing tasks, such as pattern recognition, associative memory, and temporal processing.
Due to the utilization of discrete spikes in computations, SNNs demonstrate temporal integration, a feature that is absent in traditional ANNs.As a result, important considerations have arisen when designing neuron circuits for high-performance SNNs, particularly concerning overthreshold potential and underflow. [7,9]s shown in Figure 1b, overthreshold potential refers to the excessive accumulation of membrane potential when the weighted sum of incoming signals from presynaptic neurons momentarily exceeds the neuron's threshold.If the membrane potential is reset to the resting potential after spike generation, the overthreshold potential is lost.This indicates that the neuron may fire less frequently than expected, leading to degradation in performance.On the other hand, underflow occurs when the weighted sum of incoming signals from presynaptic neurons is negative, causing the membrane potential to dip below the resting potential (see Figure 1b).This phenomenon is frequent in neural networks due to the presence of both positive and negative weights.If the lower boundary of the neuron circuit's membrane potential is set to the resting potential, underflow can effectively raise the membrane potential.It means that the neuron may fire more frequently than expected, resulting in performance degradation.[10] To demonstrate the validity of the neuron circuit with softreset and UFA, we conducted simulations of SNN applications such as pattern recognition using PyTorch ver.1.12.Based on conventional nonspiking ANNs, we initially trained a fully connected neural network with 784 neurons in the input layer, 200 neurons in the hidden layer, and 10 neurons in the output layer using the Modified National Institute of Standards and Technology (MNIST) dataset.As for the CIFAR-10 dataset, we used a VGGNet-7 structure with 3C128-3C128-AP2-3C256-3C256-AP2-3C512-3C512-AP2-FC10, where nCm represents m convolution kernels with a size of n Â n, APn denotes n Â n average pooling, and FCn indicates a fully connected layer with n neurons. [21]After training the networks, we achieved an accuracy of 98.41% and 90.28% for the MNIST and CIFAR-10 test images (for detailed information on the training procedure, please refer to Experimental Section).Subsequently, we transformed the trained networks into SNNs using the ANN-to-SNN conversion method and examined their performance on the test dataset, considering the presence or absence of soft-reset and UFA. [22,23]s illustrated in Figure 2a, the results for the MNIST dataset revealed that there was little difference in the accuracy regardless of the application of soft-reset and UFA functions.In the figure, the term "reference neuron" refers to the neuron where both soft-reset and UFA are not applied.Based solely on these results, the significance of soft-reset and UFA in the spiking neurons may appear diminished.However, as observed in Figure 2b, in the case of SNN classification using VGGNet-7 with the CIFAR-10 dataset, the application of either soft-reset or UFA alone led to significant improvement in the accuracy compared to the reference.Moreover, the results approached the baseline accuracy of 90.28% when both were applied.It demonstrates that for more complex SNNs with deeper layers, the presence or absence of soft-reset and UFA functions profoundly affects performance.This is due to the accumulation of errors in deeper layers when soft-reset and UFA are not applied. [7,9]n order to analyze the effects of soft-reset and UFA more comprehensively, raster plots were extracted for two test samples in VGGNet-7.Figure 2c,d shows raster plots for a sample horse image, comparing neuron models with both soft-reset and UFA applied to a model with only soft-reset (UFA disabled).When the output neuron #7 shows the highest firing rate, the image is Unlike non-SNNs, information is conveyed through spikes, and spatio-temporal integration takes place.b) Changes in the membrane potential during synaptic integration.Overthreshold potential occurs when a neuron fires, and underflow can occur when a significant amount of presynaptic input is applied to negative weights.
correctly classified, as shown in Figure 2c.However, when UFA is not applied, it is revealed that neuron #4 fires more frequently than # 7 [see Figure 2d].It is due to the restriction of underflow, leading to an undesired increase in firing rates for certain neurons.Raster plots for a sample ship image are shown in Figure 2e,f, comparing neuron models with both soft-reset and UFA applied and a model with only UFA (soft-reset disabled).If it is correctly classified, the output neuron #8 should fire the most frequently, as illustrated in Figure 2e.However, when soft-reset was disabled, the loss of information caused by discarding over-threshold potential led to less firing in the output neurons than expected, resulting in misclassification [see Figure 2f].
As modern ANN models adopt deeper and more complex architectures for intricate applications, implementing soft-reset and UFA into neuron circuits becomes crucial to achieving high-performance SNNs.

180 nm CMOS I&F Neuron Circuit
Figure 3a presents the block diagram of the proposed I&F neuron circuit.The circuit comprises an integrator, comparator, one-shot pulse generator, and current source.The integrator is composed of an operational amplifier (op-amp) and a capacitor (C mem ), where presynaptic inputs are integrated to form the membrane potential.The op-amp is introduced to stabilize the bitlines of a synapse array utilizing its characteristic known as a virtual short.Without this stabilization, when the bitlines are directly connected to the membrane capacitors, the voltage of the bitlines fluctuates based on the integrated charge in the membrane capacitor. [24]onsequently, such fluctuations result in computational errors during the multiply and accumulation (MAC) process, even for identical inputs and weights.Thus, ensuring the stability of the voltage in the bitlines becomes crucial to the proper functioning of the I&F neuron circuit.The comparator compares the membrane potential (V mem ) and the threshold voltage (V th ) and triggers the one-shot pulse generator when V mem becomes lower than V th .Subsequently, the one-shot pulse generator generates an output spike, which propagates to the next layer.Presynaptic input currents are integrated into the membrane capacitor, so V mem , the output node of integrator, is changed by Equation ( 1), which is given as where V ref represents the resting potential of the membrane.When inputs coming from synapses with negative weights dominate, I in becomes negative, causing V mem to increase.Under such circumstances, underflow can occur depending on the state of V mem .In previous studies, the membrane capacitor was typically connected to ground, preventing any possibility of underflow, as V mem could not go below 0 V. [25,26] However, in the proposed I&F neuron circuit, underflow is naturally allowed due to the fact that both electrodes of the membrane capacitor are not connected to 0 V but to V ref in the initial state.As a consequence, when a negative value of I in is applied, V mem becomes higher than V ref , which corresponds to the operation of UFA.
In addition, we designed the I&F neuron circuit that has two modes for choosing whether to retain overthreshold potential or not so as to investigate the differences between them.When the soft-reset function is turned off, we refer to this mode as the zero-reset mode. [7]In Figure 3a,b, the circuit connections are illustrated to show the changes that occur in the circuit when switching between the soft-reset and zero-reset modes, respectively.We can change the mode by the 1-to-2 decoder's control signal.In the zero-reset mode, the charge stored in C mem is discharged to V ref when the neuron fires; in the soft-reset mode, on the other hand, a fixed amount of charge Q is discharged from C mem by I reset , which is expressed as , we can assert that the circuit is operating in accordance with the ideal soft-reset condition.
In the proposed circuit, we have the flexibility to adjust I reset in accordance with the varying magnitudes of V th.Based on the different V th , the Con_I reset signal in the reset current generation part chooses one of the ground-connected switches, tapping the different nodes between the series-connected resistors comprising R reset .That is, I reset is modulated based on the resistance between the p-type metal-oxide-semiconductor (PMOS) fieldeffect transistor of the current mirror and ground.Figure 3c presents a micrograph image of the fabricated chip, which was implemented using the 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC).The core area of the I&F neuron circuit occupies 12 975 μm 2 , and the membrane capacitance is 5 pF.
The timing diagram of the I&F neuron circuit operating in the soft-reset mode is dipicted in Figure 4a.When a sufficiently positive I in is applied, causing V mem to become smaller than V th , the output node of the comparator (V com ) transitions from 0 V to V DD .Once V com reaches V DD , the one-shot pulse generator activates, generating an output spike in the form of a square pulse.This output spike serves not only as presynaptic spikes for neurons in the next layer but also as an input to reset the accumulated charges in the membrane capacitor.Specifically, the output spike triggers a switch between the reset current source (I reset ) and the membrane capacitor.While the switch is turned on, I reset discharges the membrane capacitor accordingly.
Above all, we conducted measurements to verify whether the fabricated circuit performs basic I&F operation.Figure 4b presents the output characteristics of the I&F neuron circuit in the zero-reset mode, with V ref set to 1.1 V, when subjected to a spike input of 200 kHz.In this experiment, we adjusted V th to 0.98, 0.95, and 0.92 V to observe the differences in the circuit's output behavior.As a result, it was observed that periodic output spikes were generated, and the firing rate of the output also varied with changes in V th .As V th decreased, the neuron needed to integrate more charge from V ref , leading to a slower firing rate of the output spikes.
Next, in the zero-reset mode, we conducted measurement to observe changes of the output spike pattern by adjusting I in while keeping V ref and V th at 1.1 and 0.9 V, respectively.This experiment emulates a scenario where the neuron receives a large input all at once.As shown in Figure 4c, we experimentally verified that as the input current is increased to 0.5, 0.8, and 1.2 μA, the firing rate of the output spikes also increases.
As mentioned earlier, in order to guarantee the soft-reset operation under various V th conditions, we designed the circuit to control I reset .Figure 4d shows the measurement results in the soft-reset mode comparing the firing rates of the output spikes with respect to synaptic input current and I reset , while V th is maintained at 0.9 V. We observed that as I reset increases, the firing rate of output spikes decreases for the same synaptic input current.This is due to a larger amount of charge being subtracted by I reset , which requires more charge accumulation for the next spike generation.By increasing the synaptic input current, we verified that the overall firing rate increases, but still confirmed that the firing rate consistently decreases as I reset is increased in all cases.Consequently, it is evident that the proposed circuit can achieve the ideal soft-reset operation through precise adjustments of I reset .

System-Level Evaluation
In order to precisely assess the system-level performance and validate the efficient preservation of overthreshold potential in the circuit's characteristics, it is essential to incorporate the measurement results.Nonetheless, due to the unfeasibility of measuring the membrane potential in the test chip, we established a SPICE simulation environment based on the measurement results to accurately emulate the chip.Following that, we utilized the SPICE results to derive the soft-reset performance of the circuit, which was then integrated into the high-level simulation using PyTorch.Since the UFA is inherently integrated into the circuit's design, situations where it is disabled were excluded from consideration.
Figure 5a depicts the firing rate of the neuron in response to variations in the input synaptic current and I reset at a V th of 0.9.The symbols represent the measured results, whereas the lines represent the data obtained through SPICE simulations.In the zero-reset mode, at low input currents, both input and output demonstrate relatively linear characteristics, attributed to a minimal amount of overthreshold potential during synaptic integration.However, as the input current increases, the output characteristics exhibit nonlinear changes.As mentioned in the previous section, this phenomenon arises as the neuron fires at a rate lower than expected due to the loss of overthreshold potential.In the soft-reset mode, measurements were conducted accurately by systematically varying I reset to accurately determine the conditions for lossless soft-reset operation.Even under low synaptic current conditions, the input-output relationship exhibits a nearly linear behavior regardless of I reset .Moreover, at an I reset value of 4.86 μA, a remarkably linear input-output relationship is observed even under high synaptic current conditions, indicating that soft-reset operates most optimally and closely aligns with the desired state.
Using SPICE simulations, we verified the amounts of overthreshold potential just before the neuron fires and the retained overthreshold potential after firing at I reset values of 4.86, 5.39, and 5.98 μA.As shown in Figure 5b, when I reset is 4.86 μA, there exists a significant correlation between the amounts of overthreshold potential before and after firing.However, for I reset values of 5.39 and 5.98 μA, it becomes evident that I reset results in excessive subtraction from the membrane potential, leading to overthreshold potential loss.Notably, in cases with low overthreshold potential, underflow is induced by I reset .The root mean square error values between the amounts of overthreshold potential before and after firing were 0.497, 20.45, and 43.29 mV for I reset values of 4.86, 5.39, and 5.98 μA, respectively.
By incorporating these characteristics into the PyTorch highlevel simulation, we conducted an evaluation of the classification accuracy in VGGNet-7, as extracted in Figure 5c.The results showed that I reset at 4.86 μA achieved an accuracy of 90.25%, closely approaching the baseline accuracy of 90.29%.Despite a slight reduction in the accuracy of the soft-reset mode, I reset values of 5.39 and 5.98 μA still demonstrated significantly improved results, with maximum recognition accuracies of 90.11% and 89.41%, respectively, when compared to the zeroreset mode.

Comparison to Previous Studies
Table 1 presents a comparison between the proposed I&F neuron circuit and previously reported ones.[28][29][30][31] However, through careful circuit optimization in simulation, we achieved a remarkable reduction of %47.2% in the neuron's area and an impressive 90% decrease in energy consumption per spike.
In addition, what distinguishes our proposed circuit from others is its distinctive implementation of soft-reset and UFA functionalities, enabling high performance in SNN applications.In most of previous studies, the neuron circuits were found to reset their membrane potential to a predetermined voltage after firing.This indicates that none of the circuits could retain the overthreshold potential through soft-reset.29][30][31] However, there were no mentions or analyses of the significance of this functionality.While the proposed circuit was implemented using a 180 nm CMOS technology, we anticipate that even more significant reductions in both the area and energy consumption per spike can be achieved using more advanced CMOS processes.These advancements in fabrication technology hold the potential to further enhance the overall efficiency and performance of our proposed I&F neuron circuit.

Conclusion
In this study, we designed and implemented an I&F neuron circuit with the soft-reset and UFA functionalities by TSMC 180 nm CMOS tehcnology, specifically designed for hardware-based SNNs.When a neuron receives a large positive presynaptic input all at once, the amount integrated above the threshold is referred to as overthreshold potential.Conversely, when a neuron is driven below the resting potential by significant negative presynaptic inputs, the quantity integrated in this direction is termed underflow.The retaining of overthreshold potential and allowing underflow processes are crucial in enhancing the performance of SNNs by preventing information loss.Initially, we demonstrated the significant benefits of applying soft-reset and UFA in complex neural network applications through simulations.Subsequently, we measured the characteristics of the proposed circuit using the fabricated chip.By connecting the membrane capacitor to V ref instead of ground, UFA was naturally implemented.Moreover, we controlled the magnitude of I reset , a current responsible for resetting the membrane potential upon neuron firing, to precisely retain the overthreshold potential.We validated the accurate functioning of soft-reset and UFA by calibrating the neuron's output characteristics using SPICE simulations.Furthermore, we incorporated these characteristics into high-level simulations by PyTorch ver.1.12 and achieved a remarkable classification accuracy of 90.29% in VGGNet-7 for CIFAR-10 dataset.Consequently, through experiments and simulations, we were able to demonstrate that soft-reset and UFA are essential in the design of neurons when implementing high-performance hardware SNNs.

Experimental Section
Neural Networks Details: Initially, the MNIST dataset was trained using a fully connected neural network with 784 neurons in the input layer, 200 neurons in the hidden layer, and 10 neurons in the output layer.Dropout with a probability of 50% was applied, and the adaptive learning rate was adjusted by multiplying 0.1 after 60, 100, and 140 epochs, starting with an initial value of 1 Â 10 À3 .We optimized the weights using Adam with an L2 decay parameter of 5 Â 10 À5 .After training, the model achieved a test accuracy of 98.41%.
For the CIFAR-10 dataset, we trained it using the VGGNet-7 architecture.The adaptive learning rate was adjusted by multiplying 0.5 after 80, 140, and 200 epochs, with an initial value of 2 Â 10 À4 .We utilized the Adam algorithm for optimization with an L2 decay parameter of 7.5 Â 10 À5 .During the training process, we applied data augmentation techniques, such as random crop with a padding of 4 and horizontal flip.As a result, the classification accuracy for the test dataset reached 90.29%.
System-Level Simulation: In this article, all SNN simulations were performed using the ANN-to-SNN conversion method. [22,23]We used the conventional nonspiking ANN approach to train ANNs first and then normalized the trained weights appropriately to achieve optimal performance through threshold balancing. [23]The weight normalization was adjusted to match the threshold values that can be implemented in the designed circuit.In the system-level simulation, we assumed that the trained weights could be ideally transferred to the hardware.Then, we incorporated the measurement results into the neuron model to emulate the soft-reset mode.
Measurement Setup: The digital signals used to control the chip were generated by an FPGA (VCU-118) using Vivado 2021.2 and Xilinx Vitis 2021.2.Specifically, in Vivado 2021.2, we synthesized our own register transfer level design with MicroBlaze, which was provided by Xilinx.By controlling MicroBlaze with Xilinx Vitis 2021.2, based on the Cþþ language, we applied input signals to the chip and processed the output signals from it.For supplying DC voltages, we used a power supply (E36312A) and a waveform generator (33600A).Additionally, an oscilloscope (DSOX1204G) was employed to monitor the signals applied to the chip.In order to facilitate the connection of the fabricated chip to other equipment, we designed a PCB module and board to which the chip was attached.The PCB module and board serve as a platform Δ: conditionally possible, but not confirmed.

Figure 1 .
Figure1.a) A schematic diagram of SNNs.Unlike non-SNNs, information is conveyed through spikes, and spatio-temporal integration takes place.b) Changes in the membrane potential during synaptic integration.Overthreshold potential occurs when a neuron fires, and underflow can occur when a significant amount of presynaptic input is applied to negative weights.

Figure 2 .
Figure 2. Simulation results of SNN validation for the necessity of soft reset and UFA.An unmodified neuron model without any effects applied was designated as the "reference neuron."Classification accuracy of a) MNIST and b) CIFAR-10 datasets with the application of soft-reset, UFA, or both.Raster plots for a sample horse image in VGGNet-7 dataset when c) both soft-reset and UFA are applied and d) only soft-reset is applied.Raster plots for a sample ship image in VGGNet-7 dataset when e) both soft-reset and UFA are applied and f ) only UFA is applied.When both soft-reset and UFA are applied, SNN accurately recognizes the correct answers.However, when only one of them is applied, the changes in firing rate led to the incorrect answers.

Figure 3 .
Figure 3. Circuit diagrams of the proposed I&F neuron circuit in the a) soft-reset and b) zero-reset modes.It is designed to switch between these two modes.Presynaptic current is accumulated by the integrator, and the comparator compares V mem and V th to generate an output through the one-shot pulse generator.Through the control signal of the decoder (Con_I reset ) in the reset current generation part, I reset can be adjusted, which is essential for proper soft-reset operation when SNN has various V th values.c) A microscopic image of the test chip fabricated by TSMC 180 nm CMOS technology.

Figure 4 .
Figure 4. a) A pulse timing diagram for the proposed I&F neuron circuit in the soft-reset mode.V refresh can be utilized to initialize the neuron.Measured output characteristics of the proposed I&F neuron circuit in the zero-reset mode to verify the basic operation b) according to the input spikes with a constant firing rate of 200 kHz and c) constant current inputs of 0.5, 0.8, and 1.2 μA.d) Measured output firing rate for presynaptic current input with respect to I reset .The output firing rate decreased as I reset increased, and the soft-reset mode can be optimized by adjusting I reset .

Figure 5 .
Figure5.a) Measurement results of the output firing rate according to presynaptic current inputs.In the zero-reset mode, the output firing rate shows a nonlinear characteristic as the input current increases.With fine tuning of I reset to 4.86 μA, the output response becomes more linear with respect to the input current, approaching an ideal soft-reset operation.b) Extracted retained overthreshold potential with respect to the amount of overthreshold potential by SPICE simulation.c) Classification accuracy of VGGNet-7 for CIFAR-10 dataset incorporated with the measured characteristics of the proposed I&F neuron circuit.By fine tuning of I reset , a high level of accuracy was achieved, which is comparable to the baseline accuracy.