Ferroelectric Field Effect Transistors–Based Content‐Addressable Storage‐Class Memory: A Study on the Impact of Device Variation and High‐Temperature Compatibility

Hafnium oxide (HfO2)‐based ferroelectric field effect transistors (FeFETs) revolutionize the emerging nonvolatile memory area, especially with the potential to replace flash memories for several applications. In this article, the suitability of FeFET memories is investigated, especially FeFET‐based content addressable memory (CAM) cells, as storage‐class memory under junction temperature variations. FeFETs with silicon oxynitride interfacial layer are fabricated and characterized at various temperatures, varying from room temperature to 120 °C. Although the memory window, numbers of programmable states, and endurance deteriorate at high temperatures, FeFETs show excellent robustness in data retention, write latency, and read stability at all temperatures, especially for binary operation. Finally, system‐level simulations using a Simulation Program with Integrated Circuit Emphasis software using experimental data are conducted to gauge the robustness of the data‐search operation using the CAM array under different temperatures. Despite temperature‐variation‐induced changes in FeFET devices, it is observed that binary CAM cells perform robust and unerring search operations for storing and searching data at temperatures up to 120 °C.

especially single-transistor ferroelectric field effect transistors (FeFETs), are promising for application in the next generation of nonvolatile memories.In the hierarchical pyramid, extensive research is underway to accommodate the FeFETs in the SCM space just above the NAND flash memory.][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] Apart from the physical attributes mentioned earlier, the architecture of the memory cell also plays a vital role in securing its place as SCM.Content addressable memory (CAM) cells are a de facto choice for quick search operations, particularly in network routing and CPU caching.However, a more detailed study on computer architecture and memory parameter compatibility must be conducted to cross-verify and solidify this understanding.Any 2D array, linked list, stack, or queue can have its stored data located using CAM cells.Quintessentially, these cells initiate a parallel search operation of the input data in a data structure to find the location of the stored data.[26][27][28][29][30] FeFET-based CAM cells are a serious contender for being deployed as storage-class memory in the memory hierarchy due to fast switching, low-read latency, high density, sufficient read and write endurance, negligible sneak path current, linearity, and high data-retention ability.FeFET-based CAM architecture offers a few hundred nanoseconds write latency, and lowenergy consumption during the data search operation, and recent reports of logic-compatible FeFETs [31][32][33][34] have fueled this concept of FeFET-CAM-based SCM section further.
43][44][45][46] In this work, we focus on evaluating the impact of process and temperature variations on the performance of FeFET-based CAMs and gauging their suitability as SCM.We have fabricated high-k metal gate (HKMG) process-based FeFETs with silicondoped hafnium oxide as the ferroelectric layer on a 300 mm wafer.The electrical characterization and modeling of devices were conducted under different temperatures. [33,34,47,48]The statistical distribution shows that only binary operation is possible with deeply scaled FeFETs amid device and temperature variations.Finally, we have evaluated the prospect of FeFET-based CAM cells as SCM amid device and temperature variations.SCMs require higher speed, lower operating voltage, and lower footprint than traditional flash memories.An increase in the junction temperature is a quintessential phenomenon in computer systems, and therefore, robustness amid temperature increase is an important criterion for SCMs.
Furthermore, we proposed a 1FeFET-1T (1F-1T) structure for the CAM cell (Figure 1), immune to device and temperature variations with proper choice of the read voltage.The 1F-1T CAM array concept was derived from our previous study reported by Masud et.al. [45]The aftermath of device variation, originating from several intrinsic and extrinsic sources, [49][50][51] is reflected in the threshold voltage (V T ) distribution of a programmed FeFET, and the impact is more severe in the low-threshold voltage (LVT) state or ON state.The cascode transistor, biased in the subthreshold regime, acts as a current limiter, reducing the current from the match line (ML) of the CAM cell.Apart from the 1F-1T structure, the choice of read voltage is also important.The read voltage should be high enough to pull the drain current above the subthreshold regime during LVT operation.The same read voltage should also ensure subthreshold operation when the FeFET is programmed to a high-threshold voltage (HVT) state.Therefore, this CAM cell utilizes the FeFET to store the memory states regarding V T .The cascode transistor is used to control the variation by limiting the ON current (I ON ), ensuring robustness. [46,52,53]he article starts by describing the fabrication and characterization of the FeFET devices, which is followed by the design of the CAM cell and CAM array and, finally, an analysis of temperature variation on the search operation CAM array.Temperature variation, especially the increased operating temperature, is essential for computers and automotive applications.There have been several works on estimating the impact of temperature variations in FeFETs, [35,36] but this work is the first one to address the effect on CAM cells.This work does not aim to provide material-level or device-level solutions to overcome the impact of device and temperature variations.Instead, this article offers an operation-level approach for maintaining immunity amid such variation with industry-compatible (GlobalFoundries' 28 nm HKMG) FeFET devices.
Figure 1.Ferroelectric field effect transistor (FeFET)-based content addressable memory (CAM) cell offers low static power consumption, high memory density, and fast search options, essential for storage-class memory applications. [24,59]. Experimental Section

Device Fabrication
The HKMG FeFET devices under test were fabricated on 300 mm wafers using a gate-first integration of standard CMOS process flows.The ferroelectric layer was integrated into the transistor by inserting a ferroelectric thin film of 10 nm, forming a metal-ferroelectric-insulator-semiconductor stack with silicon oxynitride as an interfacial layer (IL).The structural and electrical characteristics of the silicon-doped ferroelectric layer can be found in our previous work. [54]The gate stack was deposited after opening the field oxide via lithography and etching.A thin SiO 2 oxide IL was chemically grown on the channel surface.Afterward, the SiON interface layer was formed by rapid thermal nitridation and subsequent rapid thermal oxidation.Silicon-doped HfO 2 layer was developed by atomic layer deposition at 300 °C with chlorine-based precursors (HfCl 4 in conjunction with SiCl 4 ) at a cycling ratio of 16:1.A 10 nm TiN film was deposited by physical vapor deposition as a capping layer.This was followed by chemical vapor deposition of a 100 nm thick amorphous silicon layer as the gate electrode.Gate stacks were patterned via lithography and subsequent etching, followed by source/drain implantation.Finally, one-step annealing was performed for dopant activation and crystallization via rapid thermal anneal at 1050 °C for 5 s.The device fabrication process flow is reported in our previous study, [37] where we have also observed that FeFETs with SiON interface outperform devices with SiO 2 interfaces in several reliability aspects like device variations, low-frequency noise, endurance, and retention.Therefore, we would only consider devices with SiON interfaces in this study.The schematic illustration and a transmission electron microscopic image of the device cross-section are shown in Figure 2.Although the actual length and width of the devices are not disclosed in this article, it has been noted that device variations, for the device under tests, will significantly increase when the length and width of the FeFETs go below 100 nm.

Operating Principle of CAM Cell
Our proposed 1F-1T CAM design employed a two-step search scheme with FeFETs, allowing the unique identification of the stored V T state.In the first step, a search voltage below V T induced minimal OFF-state current (I OFF ), and in the second step, a search voltage above V T resulted in a high ON-state current (I ON ).The FeFET's V T state was thus exclusively identified when a low drain current (I D ) was sensed in the first search step and a high I D in the second step.By encoding information into the FeFET's V T state and selecting suitable search voltages, we could implement either a binary CAM (BCAM), leveraging the binary state of FeFETs, or a multilevel CAM (MCAM), utilizing the multilevel states of FeFETs.This design enabled efficient and precise querying of specific binary patterns or multilevel information in the memory.As we observed that binary operation held the key to robustness under device and temperature variation, we illustrated the operation principles of BCAM design with 1F-1T structure per cell later.
Figure 3a shows the 1F-1T CAM design schematic and our proposed two-step search scheme for the BCAM search function.Based on the binary-storage characteristics of the device, the FeFET in a CAM cell could be programmed into an LVT state to store bit "1" and an HVT state to store bit "0".The transfer characteristics for the stored bits "1" and "0" are depicted in Figure 3b.These transfer characteristics allowed us to define search bounds for each stored bit.To search for a bit "1", a voltage V SL1 below the LVT is applied at the search line (SL) during the first step, resulting in a low ML current.Subsequently, a voltage V SL2 above LVT was applied at SL during the next step, generating a high ML current.Similarly, a search bound for bit "0" was established by applying V SL2 in the first step and V SL3 in the subsequent step.
In the context of the ML current being sensed in terms of voltage, Figure 3c illustrates a single CAM cell with additional components: a pull-up PMOS device and a pull-down NMOS device connected to ML.During the write operation, the NMOS was activated to pull down the ML voltage and prevent write disturbance.A PMOS device pre-charged the ML.The waveforms of the clock pulse, search pulses, and ML voltages are depicted in Figure 3d for searching bits "0" and "1", where bit "0" was stored in the CAM cell.The ML was precharged during the pre-charging phase (CLK = 0 V) of the clock pulse, and the search operation was carried out during the evaluation phase (CLK = 1.1 V).The ML was precharged during the clock pulse's pre-charging phase (CLK = 0 V), and the search operation occurred during the evaluation phase (CLK = 1.1 V).When searching for bit "1", two steps were involved.In the first step, 0 V was applied to SL, which was below the high V T , causing the ML not to discharge and satisfy the criteria.However, in the second step, applying 1 V to SL was still below the high V T , and the ML did not discharge, indicating a mismatch between the searched data and the stored data.In contrast, when searching for bit "0", in the first step, SL was set to 1 V, and the corresponding ML did not discharge as 1 V was below the high V T .But in the second step, when 2 V was applied to SL, the corresponding ML discharged because the applied voltage was above the high V T .This turned on the FeFET, created a discharging path, and caused the ML to discharge.The search for the bit "0" satisfied both steps, concluding that the search data matched the stored data.Likewise, a similar search procedure for the stored bit "1" could be carried out.The search scheme involved the first step, where the ML would not discharge, and the second, where the ML would discharge.If any of these cases did not meet the criteria, it was concluded that there was a mismatch between the stored data and the data being searched.

Operating Principle of CAM Array
We performed the circuit-level analysis of a CAM array using measured data from FeFET devices and a silicon-based 45 nm CMOS technology for peripheral circuits.The analysis was based on Simulation Program with Integrated Circuit Emphasis simulations using FeFET models and a 45 nm predictive technology model.
To calculate the degree of match in a FeFET CAM array, we conducted the following simulations: The array was a 1 Â 4 CAM, as depicted in Figure 4a.Initially, all CAM cells were programmed to store bit "0".During the simulation, the ML was precharged by activating the PMOS transistor and left floating.
Figure 4b illustrates the ML waveform plotted against the different search patterns during the search operation.It was observed that during the second step of the search process, the rate at which the ML discharged increased proportionally with the number of matched bits in the search pattern.
The 4 Â 2 CAM array operation schematic in Figure 5a showed consecutive storage of "00", "01", "10", and "11" in the first, second, third, and fourth rows, respectively.For the analysis, we applied a search vector of 10 to the search line.During CAM operation, the MLs were initially charged to the supply voltage V DD = 1.1 V.Then, the search data were compared with the stored data using a two-step process in all CAM cells simultaneously on the MLs.The timing diagram of the clock pulse, SL, and ML voltages for the "10" search vectors is shown in Figure 5b.In the first step, the voltages of ML1 and ML3 remained high, while ML2 and ML4 were discharged.As a result, ML2 and ML4 did not satisfy the criteria in the first step.
Consequently, ML2 and ML4 voltage lines were excluded from decision-making in the second step.In the second step, the ML3 voltage line discharges faster than ML1, as shown in Figure 5c.As discussed earlier, a faster discharge rate indicated a higher degree of matching.Therefore, we could conclude that the search vector 10 had the highest degree of matching with the data stored in the third row of the CAM array.The match line (ML) discharge rate will be different depending on the degree of match between the search vector and the stored vector.

FeFET Characterization
Electrical analysis was conducted utilizing a wafer prober and PXI-Express system analyzer.The devices are electrically accessed with a high-temperature compatible probe card for writing and reading the memory state.The in situ ambient temperature control was realized by varying the wafer chuck temperature.The write operation is carried out by applying voltage pulses of 500 ns at the gate while grounding all other terminals.The read operation is performed by sensing the I D during a fast gate voltage (V G ) sweep while the drain voltage is kept at 100 mV.All devices underwent initial preconditioning with 100 bipolar cycles, alternating V G pulses of AE5 V for 500 ns, to ensure a complete ferroelectric wake-up.After preconditioning, the devices were programmed (LVT) and erased (HVT) with incremental positive and negative pulses, respectively, to obtain long-term potentiation (LTP) and long-term depression (LTD) characteristics.Each LTP programming pulse was accompanied by an erase pulse of À5 V amplitude and 500 ns.The erase pulse is used to reset the FeFET into the HVT state.The LTD operation is conducted using the same scheme but of opposite amplitude.A reference reset pulse of 5 V and 500 ns was applied during the LTD operation.Figure 6a shows the waveform used for LTP-LTD operation on the FeFET devices.During the programerase or LTP-LTD operations, the pulse at the gate terminal switches the dipoles in the ferroelectric layer, and the resulting remnant polarization alters the surface charge concentration in the channel, causing a modulation of channel conductance (G ch ) and the V T .In this study, V T is extracted using the standard industrial method at the drain current level of 100 Â W L nA. Figure 6b,c demonstrates the statistical distribution of V T for LTP-LTD operation conducted over 30 different devices of the exact dimensions.Although a single standalone device is characterized as having multiple separate V T states, the write (program/erase) operation variance from device to device prevents multilevel operation in memory arrays.In the presence of variations, the V T states overlap, and the number of possible memory states begins to decline.The ferroelectric switching mechanism, random coercive voltage distribution, ferroelectricdielectric domains, various trapping sites, and surface roughness at the interfaces are significant sources of device-to-device variation.We can observe from Figure 6b,c that only a binary memory level is achievable when device-to-device variation is considered.
Previously, we have considered cycle-to-cycle write variation and read variation.We observed that under the proper choice of read voltage (as mentioned before), the FeFET devices are immune to such variations. [7,37]

Temperature Variation: Read-Write Operation
Further, the impact of temperature variation on the memory window (MW), LTP-LTD characteristics, endurance, and retention was characterized.We observed the MW (Figure 7a) starts to shrink in response to the increasing operation temperature, the highest value being recorded at 25 °C and lowest at 120 °C.This dependence of the MW on operation temperature can be cumulatively attributed to the change in the coercive field (E c ), remanent polarization (P r ), and surface carrier concentration.Although the surface carrier density increases with rising temperature, carrier mobility (μ n,p ), P r , and E c decrease, which results in a decrease in MW.The trend of V T dependency on the temperature during LVT/HVT operation, described in previous studies, [35,36,55] is consistent with this study.This observed shift indicates a decrease in E c with increasing operation temperature.We have also conducted LTP-LTD operations at different temperatures.As the E c reduces with increasing temperature, the MW decreases, and the number of programmable states reduces.Figure 7b shows the number of programming states in LTP-LTD operation at different temperatures.This reduced number of V T states with increased operation temperature results from the cumulative impact of change in E c and P R , eventually leaving only binary operations available for operating the memory.

Temperature Variation: Endurance and Retention
Device data retention and write-endurance characteristics were studied at different temperatures to gauge the reliability performance of the devices at different temperatures.Retention and endurance test sequences were performed for a temperature range of 25-120 °C.Previously, we have observed that in the presence of device variation and temperature variation, only binary states are distinguishable in FeFETs.Hence, the reliability measurements have been conducted only for binary states.
Figure 8a shows the waveform used to measure the retention characteristics.Previous studies have been conducted to capture the mechanism of retention degradation in FeFETs. [37,48,56]n interplay between the charge trapping/de-trapping and polarization switching/relaxation can be attributed to the retention degradation mechanism of FeFETs.However, our study also observed a strong influence of temperature on retention characteristics, which is a direct corroboration of the temperaturedependent behavior of charge trapping and polarization relaxation. [55,57]The hysteresis or the MW in FeFET can be an aftermath of the cumulative impact of trapping/de-trapping and ferroelectric switching-a positive voltage, applied at the gate terminal of the FeFET, can result in electron trapping from the channel side.Similarly, a negative voltage will introduce trapping from the gate side.The trapping from the gate side will engender characteristics similar to ferroelectric switching. [51,58]The trapped charges get de-trapped when the electric field is removed.Henceforth, de-trapping and polarization relaxation are essential in determining retention characteristics.
Figure 8b corroborates the influence of strong de-trapping of electrons over time from the gate side in the HVT state.A negative pulse at the gate can cause electrons to tunnel into the defect sites of the high k or ferroelectric layer.The presence of an electron in the ferroelectric layer will increase the V T value for HVT states, and the de-trapping of the electron toward the gate side will cause a drop inV T values over time.Similarly, a drop in the value of V T for LVT states can result from de-trapping from the channel side.We also observe some sudden increase of V T at some certain point of time in LVT states, which can be attributed to the polarization relaxation over time.However, de-trapping strongly influences the retention degradation mechanism in all temperatures.
While de-trapping and polarization relaxation were essential aspects of retention, charge trapping, and polarization switching are essential for endurance, as measured with field cycling.FeFET was cycled for 10 4 cycles to extract the endurance characteristics with an intermediate readout after each cycling phase.All the aforementioned test sequences were performed for a temperature range of 25-120 °C. Figure 8c,d shows the endurance characteristics of the FeFETs at different temperatures.Trapping from the gate side plays a vital role in the endurance characteristics of the FeFETs.As the temperature increases, the drop in P R and E C and increased trapping, as reported in previous studies, severely degrades the endurance characteristics. [36,55,57]

Impact of Temperature Variations to CAM Array Operations
Previously, we have seen the impact of MW shrinking and reduction of I ON I OFF in FeFETs while the temperature rises.It is crucial to study the robustness of the searching capability of the CAM array, considering these effects in FeFET devices.Figure 4 illustrates the effect of temperature on the searching latency of the CAM.With increasing temperature, the HVT of FeFET devices decreases.Consequently, the latency in the second step of searching for bit "0" reduces, as depicted in Figure 9a, where the stored bit in the CAM cell is "0".Similarly, temperature affects the latency when searching for bit "1" in the CAM cell stored bit "1".However, considering the CAM operation is binary, temperature fluctuations up to 120 °C do not affect the decision-making process for matching stored data with searching data.This is because even if the V T changes, it remains within the searching bound, as shown in Figure 3c.Moreover, for the 1 Â 4 CAM array operation, the discharging time constant for the degree of MLs does not overlap, as shown in Figure 9c.This characteristic enhances the robustness of BCAM operation, especially concerning temperature variations.
We have previously discussed the endurance and retention characteristics of the FeFET.Both retention and endurance have  a severe impact on determining the performance benchmark of CAM cells.Quintessentially, the retention characteristics are much more important than endurance in the CAM application because once the data is stored in the CAM array for a search application, the user will not write the data frequently.The user will only provide search data or read voltage to the search line.So, the search process will be affected if the stored data is in the form of FeFET's V T shift over time.As the temperature increases, the MW decreases.This adversely affects the ML search boundary by inducing variation over the ON-state current in FeFETs.Since we have used a cascaded transistor, the ON-state current of FeFET is limited, making the read current immune to the ON-state current variation caused by temperature or other sources.So, our design shows not only the CAM operation but also mitigates the read current variation sources and makes it useful for CAM operation.

Conclusion
In summary, the study shows the feasibility of FeFET-based CAM cells for SCM under junction temperature variation.SCM is the bridge between flash and dynamic random access memory.This article shows a nonvolatile binary operation with 10 4 write-endurance in FeFETs with 500 ns write-time.Further system-level simulation shows low latency, search energy (0.495 fJ bit À1 ), and robust data search operation with CAM cells up to 120 °C.The impact of temperature on the CAM array's searching capability can be nullified by deploying the binary operation, which holds the key to robustness.Despite temperature-induced changes in FeFET devices, BCAM cells remain robust at temperatures up to 120 °C, ensuring reliable matching between stored and searching data, thus, proving them eligible for SCM applications.Finally, we have benchmarked this work with respect to other works in Table 1.

Figure 2 .
Figure 2. Schematic representation of fabricated FeFETs, process flow, and a transmission electron microscope image of the gate stack cross-section.

Figure 3 .
Figure 3. a) 1FeFET-1T-based ferroelectric CAM (FeCAM) cell.b) Transfer characteristics of FeCAM.A series current limiter limits the FeFET drain current to maintain the same ON current (I ON ) for both states.c,d) Operating principle and transfer characteristics of CAM cells in an array.

Figure 4 .
Figure 4. Simulation-based studies for sensing the degree of match and FeCAM array operation.a) The array prototype we simulated comprises 1 Â 4 FeCAM cells.b) The match line (ML) discharge rate will be different depending on the degree of match between the search vector and the stored vector.

Figure 5 .
Figure 5. a) Schematic of 4 Â 2 FeCAM array where 00,01,10,11 data is stored first, second, third, and fourth row, respectively.b) Timing diagrams of the clock pulse, search line (SL), and ML voltages for the "10" searching scheme.c) ML3 voltage line discharges faster than ML1, which indicates that the stored data in the third row has a higher degree of matching with searching data.

Figure 6 .
Figure 6.a) Waveform used to measure long-term potentiation and long-term depression (LTP-LTD) characteristics.Measured b) LTD and c) LTP characteristics show that amid device variation, the threshold voltage (V T ) of different programming states start to overlap, and only binary operations are possible for system-level applications.

Figure 7 .
Figure 7. a) Measured drain current-gate voltage (I D -V G ) characteristics showing the shift in V T resulting in a change in memory window (MW) associated with temperature increase.Transfer characteristics indicate a strong cumulative impact of the response of P r , E c , and surface charge for temperature.b) An increase in temperature reduces the MW of FeFETs, resulting in a reduced number of programming states and V T range.

Figure 8 .
Figure 8. a) FeFET electrical test sequence for a) retention readout for program/erase (low-threshold voltage/high-threshold voltage (LVT/HVT) stored state.b) FeFET retention dependence on operation temperature.c) FeFET electrical test sequence for endurance using cycling pulses followed by intermediate readout.d) FeFET endurance dependence on operation temperature with LVT/HVT V T evolution with cycling.

Figure 9 .
Figure 9. Temperature effect on the search operation where a) bit 0 and b) 1 are stored in FeCAM cell.c) Temperature effect on the degree of matching of 1 Â 4 array.