Ferroelectric Tunnel Junction Memristors for In‐Memory Computing Accelerators

Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/Hf x Zr1−x O2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at V read = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators.


Introduction
Machine learning by deep neural networks (DNNs) has become a vital technology in recent years due to the ability to gain insights and extract patterns from large and complex datasets.Applications such as simultaneous localization and mapping [1] or natural language processing (NLP) [2] require processing and analysis of large amounts of data accurately and with minimal delay to make real-time predictions and decisions. [3]However, with the extremely rapid development of the machine learning field, DNNs are growing exponentially in size, having trainable parameters skyrocketing far beyond the trillions.The training and use of such huge models thus forces excessive use of the computer memory, creating a fundamental bottleneck for the traditional von Neumann computing architecture that limits further advancements. [4,5]Instead, neuromorphic computing which seeks to physically merge memory and logic functions into the same device (in-memory computing, IMC), emulating the architecture and function of the human brain, has emerged as a potential solution to this bottleneck. [6,7]Figure 1a illustrates one type of IMC implementation, specifically the memristor crossbar array, in which the memristor devices provide programmable conductance states.This particular configuration holds promise for accelerating fundamental operations in neural network training, such as vector-matrix multiplication (VMM) and multiply and accumulate (MAC) tasks.In such a crossbar arrangement, the process of "accumulation" is accomplished by applying Kirchhoff 's law, wherein the currents originating from different word-lines are combined at each bit-line.In contrast, the process of "multiplication" is typically achieved using Ohm's law (I = G Â V ), with I being the current, G being conductance, and V the voltage amplitude.However, this implementation requires that G is a constant with respect to voltage, i.e., an ohmic current-voltage (I-V ) relationship, which is uncommon among memristors, typically only occurring in the high conductance range of memristors, resulting in undesirably high current levels. [8]Additionally, a nonlinear I-V relationship has the added benefit of suppressing sneak currents as will be utilized in this work.As an alternative for non-linear memristors, a commonly employed implementation, seen in Figure 1b, encodes the input x i in the voltage pulse length t n using a constant amplitude V 0 .The resulting added charge, Q, on the bitline is then measured by current integration and used as the result of the MAC operation.By maintaining a constant amplitude, a linear relationship between Q and t n can be established as Q = V 0 GðV 0 Þ Â t n , despite a voltage-dependent conductance. [9][12] For example, a recent design based on 3-bit FeFETs achieved 36.5 TOPS/W efficiency with 8-bit activation and 4-bit weight precision, highlighting the potential of DOI: 10.1002/aisy.202300554Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture.The parallel in-memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption.Key to analog neuromorphic computing hardware are memristors, providing non-volatile multistate conductance levels, high switching speed, and energy efficiency.Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation.In this work, a W/Hf x Zr 1Àx O 2 /TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m À2 at V read = 0.3 V and highly nonlinear current-voltage (I-V ) characteristics (>1100) is experimentally demonstrated.Using a circuit macro-model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved.Finally, the low on conductance in combination with the highly nonlinear I-V characteristics enable the realization of large selector-free crossbar arrays for neuromorphic hardware accelerators.this approach. [11]The fundamental building blocks of analog neuromorphic hardware are the memristor device that can represent the analog conductance states.One such promising technology are ferroelectric tunnel junctions (FTJs) based on hafnium oxide (HfO 2 ). [8]The FTJ is a two-terminal voltagecontrolled memristor.It is comprised of a ferroelectric insulating layer placed between two metal electrodes.The asymmetric screening of polarization charges at the interfaces of these metal electrodes leads to a modification in the effective barrier height.As a result, the probability of charge carrier transmission across the barrier is influenced by the polarization direction.15] Furthermore, despite being a relatively recent device technology, HfO 2 -based FTJs offer several potential advantages over other types of memristive devices, such as stable retention, a 4F 2 cell size and low conductance thanks to its voltage-driven nature.In addition, the nonlinear I-V behavior of the FTJ, relaxes the requirement for an external selector device, opening for integration in very large crossbar arrays.In fact, true FTJ crossbar arrays can potentially be fabricated instead of using pseudocrossbars containing access transistors which significantly increases the processing complexity and on-chip footprint.[17][18][19][20][21][22][23][24][25] However, the typically low oncurrent density of FTJs is considered to be a key challenge for large scale integration as it causes a slow read-out (>10 μs). [8]n issue which is further worsened as the device area is scaled down.To overcome the low on-current density and allow for device scaling, the switching-layer thickness needs to be thinned down, while keeping good memristive properties.Although there have been recent breakthroughs in achieving sub-5 nm HfO 2 -based FTJs, [16,[25][26][27] one group even reporting binary FTJs with 1 nm Hf x Zr 1Àx O 2 , [28] their suitability for hardware accelerators has yet to be thoroughly evaluated.In this work, we fabricate and thoroughly evaluate the properties of ultra-thin 4.5 nm-thick Hf x Zr 1Àx O 2 -based FTJs for their use as analog memristor synapses in neuromorphic hardware.By introducing an ultra-thin ferroelectric Hf x Zr 1Àx O 2 layer, the current density of the FTJ experiences a substantial boost by multiple orders of magnitude, surpassing that of state-of-the-art MFIM bilayer FTJs. [18]This enhancement opens up considerable opportunities for scaling down the device area.Initially, we study the dynamic polarization-electric field response of the device, highlighting the strong ferroelectric response in a sub 5 nm thick Hf x Zr 1Àx O 2 film.Then, by utilizing the partial switching behavior of the ferroelectric Hf x Zr 1Àx O 2 we demonstrate multistate conductance properties and compare both progressive amplitude and pulse width modulation, where good linearity, finely tuned resistance updates (up to 60 individual states), and near symmetric potentiation and depression is achieved.In the final section of the article, we benchmark the system level performance of the FTJs.Classification of the modified nation institute of science and technology (MNIST) dataset using the established MLP þ NeuroSim V3.0 software is performed, [29] achieving a high online learning accuracy of 92%.Finally, the impact of the sneak currents and IR drop in large crossbar arrays of FTJ memristors is investigated.Owing to the low memristor conductance, the IR drop induced voltage error is radically suppressed.This in combination with the built-in current-voltage nonlinearity characteristics make the FTJ a highly attractive choice as a memristive element.Overall, this study highlights the potential of using Hf x Zr 1Àx O 2 based FTJs as memristive elements in future neuromorphic applications to accelerate neural network training and inference.

Experimental Section
A schematic of the device structure and the fabrication steps is shown in Figure 1c.FTJ structures consisting of W/Hf x Zr 1Àx O 2 / TiN were fabricated on Si(100) substrates.A 40 nm-thick TiN bottom electrode (BE) was deposited by RF sputtering at a power of 150 W in an AJA Orion system (I).Subsequently, 45 cycles (≈4.5 nm) Hf x Zr 1Àx O 2 were grown by alternating cycles (1:1) of TEMA(Zr) and TDMA(Hf ) precursors by thermal atomic layer deposition (ALD) at 200 °C, with water as the oxidizing precursor (II).Although a Hf/Zr cycle ratio of (1:1) was used, the actual oxide composition was not measured and will therefore be denoted Hf x Zr 1Àx O 2 .To separate material and device design, we employ an electrode replacement process, as previously reported in ref. [22].A 50 nm W crystallization electrode (CE) was deposited using DC magnetron sputtering at 100 W to induce tensile strain in the Hf x Zr 1Àx O 2 promoting the formation of the ferroelectric phase. [30]Subsequently, post metallization annealing (PMA) using RTP at 535 °C for 30 s in a nitrogen environment was used to crystallize the Hf x Zr 1Àx O 2 (III).The CE was removed through wet etching using H 2 O 2 for 60 s, followed by NH 4 OH for 60 s both at a heated temperature of 60 °C.The second etching step is critical to remove the interfacial WO x formed during the PMA process required for crystallizing the as-deposited amorphous Hf x Zr 1Àx O 2 .Finally, a fresh 50 nm thick W top electrode was sputtered using DC magnetron sputtering and patterned via UV-lithography and lift-off (IV-VI).The fabricated device stack was characterized in Figure S1 and S2, Supporting Information, using a JEOL 3000 F transmission electron microscope (TEM).The HRTEM verifies that the Hf x Zr 1Àx O 2 layer crystallize in the Pca2 1 ferroelectric phase and has a thickness close to 45 Å.
Electrical characterization was performed in an MPI TS2000-SE probe station using a Keysight B1500A parameter analyzer equipped with a B1530A waveform generator fast measurement unit (WGFMU) for pulsed measurements.For current-voltage measurements high-resolution source measurement units (HRSMUs) coupled with E5288A Atto-sense units were used.The electrical characterization was performed on circular capacitors with a radius of 10-25 μm 2 .The conventional positive-up-negative-down (PUND) technique was utilized to measure the polarization vs electric field (P-E) characteristics.Rectangular voltage pulses were used for wake-up cycling and endurance measurements at a frequency of 100 kHz.All polarization measurements were performed at 10 kHz.For potentiation and depression measurements a combination of the HRSMUs and WGFMU was used.First the WGFMU was used to set the state of the FTJ using a pulsed input, then HRSMUs were used for the readout process.In the readout process, linear I-V sweeps were conducted within the range of 150-300 mV, deliberately kept well below the coercive field to avoid disturbing the programmed state.The conductance at V = 150 mV was subsequently derived from these measurements.

Ferroelectric Characterization
The conductance of an FTJ is determined by the polarization direction of the ferroelectric Hf x Zr 1Àx O 2 sandwiched between the two electrodes.The multi-domain property of the polycrystalline Hf x Zr 1Àx O 2 allows for gradual polarization switching, which alters the surface charge at the two metal interfaces.The asymmetric screening of this polarization charge at the metal electrode interfaces alters the effective barrier height.This modulation changes the probability of electron transmission, which in turn affects the conductance of the device.With this in mind, we start by evaluating the ferroelectric properties of our FTJs as shown in Figure 2. Using the traditional PUND method, a clear ferroelectric response is visible in Figure 2a with a large ferroelectric polarization reversal current measured during the P and N pulses respectively.From this data, we extract the polarization-voltage (P-V) curve in Figure 2b where a strong remanent polarization P r of 12 μC cm À2 is found.To optimize the number of accessible polarization states we evaluate the switching dynamics of the ferroelectric domains by varying both the pulse amplitude and pulse width.This is done as described in ref. [31] by first using a conditioning pulse followed by a rectangular programming pulse with varied amplitude and pulse-width and finally by two triangular read pulses.Figure 2c,d displays the time-voltage dependence for potentiation and depression respectively.Extracting the time and voltage dependance from the map in Figure 2c, the relative switched polarization ΔP normalized by the saturated polarization P s is shown in Figure 3e,f.We are able to switch the polarization direction of the ferroelectric using pulse widths below 100 ns, provided a sufficiently high bias is applied.On the contrary, using a pulse width of 10 ns almost no polarization reversal occurs independently of the bias applied (0.2-1.6 V).However, it is important to point out that this is not an inherent limitation of the response of the device, but instead stems from a large RC constant (≈100 ns) of the circuit.In Figure S3 Supporting Information, a faster response of the polarization switching is achieved as the device area and the capacitive load is reduced.Additionally, the fundamental switching speed limit of these materials are still under investigation, but previous studies indicate switching speeds below 300 ps in FeFETs. [32]

Memristor Properties of Relevance for System Integration
With a good knowledge of the ferroelectric characteristics and its switching dynamics, we now seek to investigate the memristive properties of the FTJs. Figure 3 shows the memristive characterization of the FTJs.In Figure 3a, the I-V characteristics of the FTJ can be seen.A counterclockwise (CCW) hysteresis is observed when a positive bias is applied to the W TE as the FTJ is set into a low resistive state (LRS).Similarly, as a negative bias is applied to the TE the FTJ is programmed into its high resistive state (HRS).

Nonlinearity
A key advantage of using FTJ based memristors is the highly nonlinear I-V characteristics due to the tunneling current mechanism, as this reduces the requirement of an external selector (access device) when integrated in large crossbar arrays.The self-rectifying current characteristic can enable a true crossbar implementation reducing the on-chip footprint and fabrication complexity while still allowing vertical stacking capabilities.In Figure 3b the I-V nonlinearity using both the V/2 and V/3 biasing schemes is shown.With values of 150 and 1100 respectively at V = 1.25 V, which to date are the highest values reported for HfO 2 -based FTJs (Table S1, Supporting Information for comparison).Our FTJs are thus highly promising for integration into large scale crossbars, as we will show in more detail in Section 3.3.1.

Programming Pulse Schemes
To allow for accurate programming of the conductance state of the FTJs, one needs to understand the relationship between polarization switching and conductance modulation in the memristors.We therefore examine changes in conductance through the utilization of two distinct pulse schemes shown in Figure 3c: pulse width modulation and pulse amplitude modulation.For pulse width modulation we applied a constant amplitude of AE1.5 V and a pulse width ranging from 100 ns to 1 ms, whereas for pulse amplitude modulation a constant pulse width of 100 μs and varying amplitude from AE0.1 to 2.4/À2.35V (set/reset) was used.These two pulse schemes will from here on be denoted as pulse schemes "1" and "2" respectively.In Figure 3d,e the conductance modulation of the memristor using the two pulse schemes can be seen.Figure 3f,g shows the gradual shift of the read current during successive programming using pulse scheme 2, from which the data in Figure 3e was extracted.
Based on the current level in the device, the maximum read power consumption can be calculated as P max = V read Â I max (V ) yielding P max,read = 0.3 nW.However, it should be emphasized that this value is proportional to the area of the device, meaning that for a scaled device of 100 Â 100 nm 2 would yield a P read = 30 fW instead.Similarly, the device programming energy, which is dominated by the polarization switching current, can estimated to E write = 20 pJ bit À1 (Figure S4, Supporting Information), which similarly scale to 2 fJ bit À1 for a 100 Â 100 nm 2 device size.
For successful online training the linearity and symmetry of the positive and negative conductance change is critical.However, linear and symmetric behavior is seldom observed in real memristors.In the case of a non-linear memristor, one can extract the nonlinearity parameters A p and A d based on the measured conductance change data according to the definitions in the Supporting Information, adopted from ref. [29].Once A p and A d are known, the asymmetry can be calculated as |A p À A d |.In our FTJs, pulse scheme 1 (Figure 3d) allows for a rather linear conductance update during potentiation with A p = 1.38, whereas the depression is significantly more nonlinear with A d = -4.22.Instead, by using pulse scheme 2 (Figure 3e) a more symmetrical and linear response is achieved with A p = À1.31 and A d = 2.4.The resulting asymmetry |A p À A d | of the two pulse schemes become <4 compared to <6, again indicating a closer to ideal behavior for pulse scheme 2. Additionally, by implementing pulse scheme 2 a higher number of programmable conductance states (>60) can be achieved, which is beneficial for achieving high classification accuracy. [32,33]Not only is the precision of the memristor improved using pulse scheme 2, but the dynamic range (DR) (Figure 3h) evaluated as G max /G min , is also significantly enhanced from 4 to 10 when amplitude modulation is used.The DR is strongly correlated with the classification accuracy and ideally one would like to achieve a DR > 10 for online learning. [33]igure 3i,j summarize the nonlinearity and asymmetry results of the two pulse schemes.The measurements clearly indicate that utilizing pulse amplitude modulation to modify the conductance of these FTJ memristors provides notable advantages in terms of hardware implementation.Therefore, in the following sections we focus exclusively on evaluating the utilization of pulse scheme 2.
Apart from the previously assessed parameters, it is crucial to consider the memristor's ability to maintain the programmed conductance state.In Figure S5, Supporting Information, we examine the retention characteristics across various conductance states, when programmed using pulse scheme 2, demonstrating stable operation of the programmed state for a minimum of 100 s.

Memristor Variabilities
In real-world applications, the integration of memristors into a large crossbar array necessitates careful consideration of nonidealities.The effects of both device-to-device variation (DtDV) and cycle-to-cycle variation (CtCV) can significantly influence system performance, making it essential to evaluate these factors for a comprehensive understanding. [33]In Figure 4a 13 sub-range potentiation and depression cycles using amplitude modulation of an FTJ memristor is shown.Figure 4b shows the superposition of all 13 cycles to visualize cycle-to-cycle variability for each pulse number.Figure 4c highlights the CtCV (standard deviation) as a percentage of the dynamic range.The CtCV does not exceed 2% and is around 1.2% on average during the 13 cycles.To study the device-to-device variations (DtDV) three identical FTJs were measured using pulse amplitude modulation between AE0.1 and AE2.3 V.The first potentiation and depression cycle of the three identical devices is presented in Figure 4d. Figure 4e shows the superposition of the data in Figure 4d to help visualize the DtDV whereas Figure 4f shows the DtDV (standard deviation) as a percentage of the dynamic range.The DtDV does not exceed 2.5% with an average around 0.8%.In addition to the cycling-induced variations and DtDV, the drift of on-state and off-state conductance can also present a challenge for achieving reliable implementation.Therefore, we conducted an evaluation of the stability of memristor conductance states by subjecting the same FTJ memristor to 1500 cycles of setting and resetting using a single pulse (refer to Figure S6, Supporting Information).Based on the analysis of a representative distribution of the two conductance states during cycling, the FTJs exhibit highly stable on-state conductance, with a standard deviation (σ) of less than 0.05 nS.However, the off-state conductance shows a larger σ of 0.15 nS.This discrepancy might be attributed to an increase in defect levels as the off-state is drifting toward higher conductance with successive cycling.
To summarize, considering the low CtCV and DtDV, as well as the relatively good stability of the conductance states during continuous programming, these FTJs show promise as their low variability is expected to have minimal impact on classification performance. [33]

System-Level Performance Evaluation
To benchmark the use of the FTJ devices on an integrated system level we use the MLP þ NeuroSim V3.0 framework, [29] for simulating memristor-based in-memory computing hardware for the task of classification of images of handwritten numbers from the MNIST dataset. [34]The framework implements a three-layer fully connected multilayer perceptron neural network, with 400 input neurons, a small hidden layer consisting of 100 neurons and a final layer with 10 output neurons, as depicted in Figure 5a.The weights of this neural network are mapped onto a true crossbar array in the framework without an external selector as depicted in Figure 1a, where the memristor cells consist of the presented FTJ devices and their characteristics.
Avoiding access transistors increases the memory density and would enable back end of line (BEOL) integration on top of the peripheral circuitry for further density gains.For more information regarding the simulation parameters utilized, we refer to the Supporting Information.
The classification accuracy considering various inputs is presented in Figure 5b.In the ideal case (blue) where no nonlinearity, DtDV or cycle-to-cycle variation (CtCV) is considered, a classification accuracy of ≈94% is achieved.When considering only the weight nonlinearity characteristics (red) of the FTJs extracted in Figure 3e, a significant drop in accuracy is observed down to ≈84%.Interestingly, by adding a CtCV (grey) of 3%, above the value extracted in Figure 4c, the classification accuracy improves to ≈92%.This correlates well with previous  observations in ref. [33] where a small CtCV helps to combat the nonlinearity, thereby improving the performance.The reason for this may be attributed to the random disturbance that aids the convergence of the weights to an optimal weight pattern by avoiding getting stuck in local minima.Additionally, a DtDV of 1% (black, observed mean from Figure 4f ) or 3% (teal, above observed max from Figure 4f ) do not impact the classification accuracy, which stays constant around ≈92%.

Scalability of FTJ Crossbar Arrays
In large crossbar arrays operated as random-access memory, undesirable sneak currents arising from half-selected cells diminish the read margin and limits the size for which the crossbar arrays remain functional.This is typically solved using an external selector device with highly nonlinear I-V characteristics, such as a transistor or a diode.While transistors can be considered for FTJs, they necessitate the inclusion of additional circuitry for a third electrode, thereby increasing the memory cell's footprint.Since FTJs demand the application of both negative and positive biases, conventional diodes are not suitable.Instead, symmetric threshold switches exhibiting highly nonlinear I-V characteristics [35] may be employed, albeit at the cost of introducing additional complexities in the manufacturing process.However, as shown in Figure 3b, the current-voltage characteristics of the FTJs is already strongly non-linear, due to the tunneling-based current transport, thus the selector behavior comes built-in to the device itself.To determine the maximum functional FTJ array size without external selectors, we evaluate the read margin ΔV/V pu of the array. [36]Figure 5c shows the calculated readout margin of the FTJ memristor when using the V/2 and V/3 voltage schemes. [37]We assume a worst-case scenario where all unselected cells are in the ON-state incurring maximum read disturbance, the so called one bit-line pull-up (1 BLPU).In this scenario, the difference in voltage drop (ΔV ) across the pull-up resistor (R pu ) within the crossbar array can be utilized to differentiate between the ON and OFF states of the selected cell.Typically, a ΔV/V pu (pull-up voltage) ratio of 10% has been recognized as the minimum criterion to distinguish their switching state. [36,38]This criterion enables the maximum number (N) of word/bit lines using the resistor voltage divider Equation (1), which is expressed as follows In our specific case, the values of R F sneak and R R sneak observed at unselected cells play a crucial role in determining the overall resistance through sneak paths.These values can be determined by performing linear fittings on the I-V curve in Figure 3a at the chosen read voltage, V read .We evaluate these resistances at V read = 1.25 V where the nonlinearity is the largest obtaining the resistance values R pu = 75kΩ, R F sneak = 28 MΩ (5.9 MΩ), and R R sneak = 10.1 MΩ (4.8 MΩ) for the V/3 (V/2) scheme.We note that although the chosen read voltage is large enough to switch the resistance state of the FTJ for long pulse times, for pulse times <100 ns the state would be largely unaffected.Depending on the voltage schemes employed, the permissible maximum size of the crossbar array varies significantly.On average, the V/2 scheme allows for up to 54 kbits, while the V/3 scheme permits ≈1.2 Mbits (as shown in Figure 5c).
In addition to sneak currents, the IR drop across parasitic wire resistance is a severe bottleneck, limiting the up scaling of the array size.The IR drop arises from the non-negligible wire resistance along the row/column wires which increases quadratically with the number of rows and columns in the array, heavily hampering the array density scaling.However, the IR drop issues can be radically suppressed by implementing low conductance memristors such as FTJs in the crossbar array.To assess the scalability of the FTJ array in regard to IR drop we use the open-source tool developed by Joksas et al. [39] The wire resistance used in the simulation is calculated as r ¼ ρ Â 2FA À1 ¼ 2ρF À1 where ρ is the metal resistivity, F the feature size which controls the cell-cell pitch 2F and the wire cross section A = 2F.We assume a tungsten wire with ρ = 10 μΩ cm [40] and a feature size F = 20 nm from which r = 10 Ω is obtained.Figure 6a,b shows the calculated potentials of V TE (red) and V BE (blue) as well as ΔV = V TE À V BE (green).A square array of size N = 1000 and the worst-case scenario where all cells are programmed to the LRS with G = 1.2 nS (see Figure 3e) was assumed.Figure 6c shows the calculated relative error introduced in the I ¼ G Â V operation due to the IR drop for various memory device technologies, such as 1T1R RRAM [41] , FeFET, [42] 1,1SR PCM [43] and FTJs.Owing to the very low conductance of the FTJ, an increase in array size of 150Â and 5Â at equal error can be achieved compared to FeFETs and 1S1R PCMs respectively.This result is of key importance as the implementation of large crossbar arrays will be critical to achieve high energy and area efficiency in hardware accelerators of artificial neural network (ANN) applications.Low memristor conductance and a large array size results in a significant reduction of the peripheral circuitry required, which in turn allows for a dramatic reduction of both energy and area consumption.
Finally, it's important to emphasize the existing tradeoff between optimizing the memristors for minimal IR drop or minimal sneak current.Applying a low V read increases memristor's resistance, thereby effectively suppressing the IR drop.
to limit the sneak currents, a large V read should be applied as a notably larger I-V nonlinearity is obtained.Despite these conflicting effects, we contend that leveraging low conductance memristors holds greater promise, as it allows for a substantial reduction in required peripheral circuitry.This reduction is pivotal in mitigating the substantial overhead and energy consumption associated with analog-to-digital (ADC)/ digital-to-analog (DAC) components, a crucial step toward the successful implementation of area and energy-efficient hardware accelerators for in-memory computing.Future efforts should thus be directed toward enhancing the FTJs I-V nonlinearity in the low bias regime of memristors to improve the readout margin and facilitate the upscaling of crossbar arrays.Nevertheless, the results obtained in this work are highly encouraging, signifying that the fabricated FTJs hold significant potential for high-density and energy efficient neuromorphic applications.

Conclusion
In conclusion, we experimentally demonstrate W/Hf x Zr 1Àx O 2 / TiN FTJ memristors utilizing partial switching of the ferroelectric Hf x Zr 1Àx O 2 to modulate its conductance.The FTJs exhibit near symmetric potentiation and depression, good linearity, DR up to 10 and 60 conductance states, when using an amplitude modulation scheme.[46] Additionally, the low conductance radically reduces the IR drop which in combination with the built-in I-V nonlinearity encourages the realization of system level integration of large-scale true crossbar arrays.

Figure 1 .
Figure 1.a) True crossbar implementation of FTJ memristors where the ferroelectric (teal) is sandwiched between the top (red) and bottom (blue) electrodes.b) Implementation of multiply and accumulate operations in a crossbar arrangement using analog temporal encoding.The input x i is encoded in the pulse length t n using a constant amplitude V 0 .The currents I are summed up though each bit-line of the array where the magnitude of the current is dependent on the programmed memristor conductance G.The current is then integrated to get the charge Q. c) Fabrication process of FTJ devices.(I) Deposition of the TiN bottom electrode on Si/SiO 2 substrate using RF Sputtering.(II) ALD growth of amorphous Hf x Zr 1Àx O 2 followed by (III) W crystallization electrode deposition and RTP at 535 °C.(IV)-(VI) metal replacement process and W top electrode deposition and patterning through UV-lithography and lift-off process.

Figure 2 .
Figure 2. Ferroelectric characterization of the MIM capacitor structures.a) I-t and V-t data measured using the PUND technique of the fabricated MIM capacitor (b) Extracted P-V curve from the data in (a), where a large remanent polarization is achieved.c,d) Dynamic polarization switching for potentiation and depression respectively.e,f ) Time and voltage dependance of the switched polarization ΔP normalized to the saturated polarization P s , extracted from (c).

Figure 3 .
Figure 3. Memristive characterization of FTJ memristors.a) current-voltage (I-V ) characteristics, showing the counterclockwise hysteresis indicative of FTJs.b) I-V nonlinearity defined as I(V)/I(V/2) and I(V)/I(V/3) for V/2 and V/3 scheme respectively.c) Definition of the two pulse schemes "1" and "2".d,e) Potentiation and depression of memristor conductance (G) using pulse scheme 1 and 2 respectively.The nonlinearity parameters A p and A d are fitted according to the definitions available in the Supporting Information.f,g) Gradual shift of the read current in the FTJ with successive programming using pulse scheme 2, the data from which the data in (e) was extracted.h-j) Comparison of the G max /G min (DR, target = 10), nonlinearity (A p , A d ) and asymmetry |(A p -A d )| for the two different pulse schemes.

Figure 4 .
Figure 4. Variability of FTJ memristors.a-c) cycle-to-cycle variation (CtCV) and d-f ) device-to-device variation (DtDV).b-e) shows a superposition of the data in (a) and (d) respectively, to visualize the variations at each pulse number.c,f ) shows the CtCV and DtDV (standard deviation) as a percentage of the dynamic range (DR).The dashed dotted red lines indicate the average.

Figure 5 .
Figure 5. Memristor system integration.a) The neural network structure used in MLP þ NeuroSim V3.0, to train the MNIST dataset.The network is a fully connected multi-layer perceptron network consisting of 400 input neurons, 100 hidden neurons, and 10 output neurons.b) Online classification accuracy as a function of number of epochs for ideal (blue) and non-ideal memristor characteristics.c) Evaluation of the crossbar array read margin ΔV/V pu using V/2 (blue) and V/3 (red) bias scheme.

Figure 6 .
Figure 6.Evaluation of IR drop on an FTJ crossbar array.a,b) Calculated node potential of the top (red) and bottom (blue) electrode as well as the difference between them ΔV (green) in a square array with N = 1000.c) Voltage error caused by IR drop as a function of array size for various memory technologies.The break in the solid line indicates the beginning of extrapolated values.