Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.


Introduction
As an alternative computing architecture to current von-Neumann systems, neuromorphic computing has garnered significant attention.The result of much research on the neuromorphic mimicking of memory and learning behaviors has rapidly developed through various nanoscale devices. [1]For example, devices emulating the function of biological synapses have been investigated through work in resistance random access memory (RRAM), [2] conductive bridge random access memory (CBRAM), [3] phase-change memory (PCM), [4] spin-torque transfer magnetic random access memory (STT-MRAM), [5] flash memory, [6] and field-effect transistors (FETs) to overcome limitations of conventional computing systems. [7]As the most crucial property for these devices, synapse plasticity is the ability to strengthen or weaken over time in response to the frequency and strength of stimulations. [8]RRAM and CBRAM emulate synaptic plasticity by controlling the migration of oxygen vacancies or metallic ion filaments, and were studied to control the filament with various materials, [9] structures, [10][11][12] and pre-treatments. [13,14]owever, stable controlling the vacancy or ion filament is difficult to achieve consistently and continuously. [15,16]][16] With respect to circuits, non-identical pulses require calibration of the pulse amplitude or width to read the current conductance states. [17]Twoterminated synaptic devices offer the benefits of scaling and fabrication efficiency compared to three-terminated synaptic devices.However, it is challenging to control their resistance A fully depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics.Gate-last processed FDSOI MOSFET with a high-k/metal gate stack features a memory window of 10 3 .Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET.Short-and long-term plasticity are investigated by applying engineered pulse, verifying the long-term synaptic properties of pattern recognition processes.With controllable synaptic conductance, the trade-off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83.To verify the pre-and post-synaptic weights within a real hardware-based neuromorphic system, 5 Â 6 FDSOI field-effect transistor (FET) synapse array is interconnected to 10 Â 10 leaky integrate-and-fire (LIF) neuron array.The synaptic plasticity of FDSOI MOSFET in post-neurons following neuron firing in the neuron device is successfully demonstrated.These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self-learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.state stably, and improvements are still required for the reliability of cell-to-cell.The two-terminal synaptic device has the same channel for writing and reading terminal, which is difficult to control the synaptic characteristics sensitively.However, the three-terminal synaptic devices allow decoupling the read and write steps, permitting stable and sophisticated operation in low operating voltage. [18]Furthermore, two-terminal based memristor synapses have limitation of sustaining synapse characteristic for long-term plasticity due to problem with the mismatch and retention in SET/RESET current state compared to threeterminal device and need the additional circuitry for implementation of neuromorphic system. [19]or controlling and maintaining the reliability of the multistate memory levels, three-terminal structure devices of interest, such as the thin-film transistor (TFT), do not hamper signal transmissions through the source and drain electrodes using the gate terminal. [20]A synaptic TFT device using zinc oxide demonstrated the synaptic functions of excitatory post-synaptic conductance (EPSC) and potentiation/depression endurance after the application of a voltage pulse on the bottom gate electrode. [20,21]This TFT structure, with its global bottom gate, offers a structural limitation.TFT devices has limited application due to their materials structure (for example, the absence of the stable p-type channel material), and in particular, they are difficult to universally use in the current Si technology process.Therefore, metal oxide semiconductor field-effect transistor (MOSFET) is emerging as the frontrunner three-terminal candidate device.The MOSFET, which has been applied in many semiconductor industries, was studied to mimic synaptic function using bulk or floating body substrate. [22]Compared to bulk Si, floating body substrate provides the advantage of suppressing leakage current more effectively.Synaptic transistor with this Sibased floating-body substrate is introduced to contact synapse devices to the neuron circuit without the additional switch or controller thanks to the four-terminal transmission. [19]Research results on other types of three-terminal based devices are also reported.The optically gated carbon nanotube field effect transistors (OG-CNTFETs) are fabricated for neuromorphic computing to solve crosstalk effects of two terminal devices and show that could be independently programmed each device in simple circuits. [23]The MOSFET having dual gates in top and bottom emulates the synaptic plasticity. [24]Three-terminal synaptic devices with 2D materials, [24][25][26][27] semiconductors, [27] and synthetic chemical compounds [28,29] appear to control synaptic characteristics stably and the reliability compared to two-terminal RRAM devices.However, other synaptic plasticity behaviors observed in the biological human brain, such as the interaction between neurons and synapses, have not been thoroughly studied in a conventional FDSOI MOSFET in terms of hardware.Further study on how to apply a conventional MOSFET as a synapse device is needed to support the rapid and unpredictable future changes in the semiconductor industry.Furthermore, research utilizing FDSOI devices includes neuron research, [30] array neural network, [31] and neural network research connecting SRAM synapse and SRAM neuron array. [32]FDSOI MOSFET has advantage of suppressed short channel effect (SCE), low capacitance, low junction leakage, low voltage, and so on. [30,33]Demonstrating artificial neural networks often requires numerous devices and complex circuits, making low-power devices advantageous.However, there is a dearth of research on the configuration of a hardware-based array system that connects these three hardware-based terminal devices with a neuron device and evaluates the electrical characteristics that regulate pre-and postsynapses accordingly, thus mimicking the human brain.
In this work, three-terminal FET using a fully depleted siliconon-insulator (FDSOI) substrate that can reliably control the flow of current between a drain and source with a potential difference between the gate and body is demonstrated as a stable artificial intelligence device and furthermore hardware-based neuromorphic system was fabricated and characterized with leaky integrate-and-fire (LIF) neuron arrays.FDSOI MOSFETs with atomically layer deposited (ALD) HfAlO x and TiN gate stack were fabricated to enable low operating voltages without leakage current.The FDSOI MOSFET configured as a synapse device emulates the biological synaptic plasticity characteristics of long-term and short-term memory using an operating gate voltage range between À2 and 1 V and a drain voltage at 0.1 V. Synaptic conductance changes following a weight update in the gate terminal are verified by electrical characteristics and applied to pattern recognition using a perceptron network.Finally, to evaluate the hardware-based neuromorphic system, real hardware-based neuromorphic system having the 5 Â 6 synapse array using the verified FDSOI FET interconnected to 10 Â 10 LIF neuron array consisting of Ag/HfO 2 /Pt was characterized and the synaptic plasticity after a neuron firing was demonstrated.Through the connected neuromorphic system, it was verified that the postsynapse conductance of the FDSOI MOSFET could be adjusted by controlling the pre-synapse weight.

Results and Discussion
Figure 1a,b shows optical microscopy (OM) images and transmission electron microscopy (TEM) analysis of single and arrayed FOSOI MOSFET synaptic devices.The synaptic device was fabricated as array position, which was identified with OM in top view as likely as Figure 1a.The FSOI MOSFET synaptic device was cut clearly with a focused ion beam (FIB) for investigating the cross-section of the gate structure.Figure 1b shows these cross-sectional images from the TEM analysis to confirm the gate stacking layer, thickness, and elements.The ALD TiN/HfAlO x layers on the FDSOI substrate were verified with a 4.6 nm thickness of the high-k oxide, HfAlO x , as seen in Figure 1b.In addition, using energy-dispersive X-ray spectroscopy (EDS) the mapping elements Ti, N, Si, Hf, Al, and O of the gate stacks were analyzed.Each element was distinguishable for the layers of TiN/HfAlO x /Si, as shown in Figure 1b.An I D À V G switching curve of the FDSOI MOSFET synaptic device showed memory characteristics when a DC sweep was applied to the gate electrode with a potential difference between the drain and source electrodes.The gate voltage was swept from À0.4 to 1.2 V while applying 0.1 V on the drain terminal.Figure 1c illustrates 7-order ratio of the on-to-off current and a 3-order ratio of the memory window at a 0.4 V gate value of V read .This specific V read had the largest conductance margin and was insufficient to change the channel conductance.[36][37][38] This observed hysteresis can be controlled by the dielectric thickness, energy, and space trap location. [37]The 3-ordered memory window of the FDSOI MOSFET synaptic device behaved the same as a conventional RRAM device and was sufficient to perform the synapse functions.To evaluate where this device can operate as a synaptic device, the synaptic plasticity was measured by applying an engineered synaptic pulse on the gate electrode, as shown in Figure 1d.During the two synaptic pulses, the post-synapse current level increased to approximately 10 nA, which corresponds to EPSC in a biological brain.The increased current level relaxed during the interval period in Figure 1d.The secondary spike decreased over 1.7 s until reaching the same current value of the 1 s decreasing time from the first spike.The fit lines of the graph calculate the measurement current value needed to identify the relaxation time according to where I(t) is the synaptic current of the MOSFET device at time t.The I 0 , A, and τ values are the initial synaptic current, constant value, and slope coefficient of relaxation time, respectively.The slope coefficient of relaxation time is seen to increase during the secondary spike from 0.1 to 0.3 s.This change of EPSC indicates that training is influenced by pulse frequency, transforming into long-term memory with the more repetitive stimuli.As a result, it was verified that FDSOI-MOSFET could mimic the biological synaptic property.[41] To investigate these SRDP characteristics in the FDSOI MOSFET synaptic device, a regular variation of the input pulse weight was applied to the gate terminal.The input gate pulse consisted of an increasing pulse width from 10, 20, 40, 100, and 200 ms or an increasing pulse frequency from 1, 2, 4, 10, and 20 Hz, as shown in Figure 2. The learning rate was strengthened with increasing pulse width, where the growth  values of the output current level increased by 2.18 Â 10 À8 , 2.65 Â 10 À8 , 3.17 Â 10 À8 , and 3.63 Â 10 À8 A, following an increased pulse width of 20, 40, 100, and 200 ms, respectively.Similarly, high frequencies strongly enhanced the synaptic current value, where current values increased to 3.11 Â 10 À8 , 3.25 Â 10 À8 , 3.59 Â 10 À8 , and 5.58 Â 10 À8 A, following the frequencies of 2, 4, 10, and 20 Hz, respectively, as seen in Figure 2b.In Figure S1, Supporting Information, the change of post-synapse current was calculated and investigated, showing that increasing the frequency was observed to be more effective for long-term memory learning than increasing the pulse width.The FDSOI MOSFET device stably emulated SRDP, indicating this FDSOI FET could be applicable for an artificial synaptic device.In Figure S2, Supporting Information, spike-timingdependent plasticity (STDP) was verified, indicating that a smaller Δt, representing a shorter delay time between preand post-spike, leads to greater conductance changes.Based on these results, FDSOI MOSFET, with a linear and symmetric change of conductance in response to electrical pulses, emulates the STDP learning rule, similar to a biological synapse.
Figure 3 shows short-term memory characteristics of pairedpulse facilitation (PPF) and post tetanic potentiation (PTP) with respect to different pulse widths.To examine the learning rates, pulse widths of 100, 300, 550, 750, and 2000 s were applied to the pre-synaptic gate terminal.As shown in Figure 3, the examination extracted I 2 ─I 1 and I 10 ─I 1 to represent the PPF and PTP akin to biological processes where a stimulus at the pre-synapse induces the release of Ca 2þ ions to influence neurotransmitters.Before these stimulated Ca 2þ ions decay to an equilibrium state, an applied second stimulus strengthens the release of neurotransmitters, which then enhances the response of the post-synapse PPF.The response continues to increase until the application of the 10th stimulus, as in PTP. [42]The FDSOI MOSFET synaptic device emulates this complicated biological system comprising the PPF and PTP.The red lines represent the curve fitting of the extracted ΔI with Δt in the post-synaptic terminal, as shown in Figure 3a,b, respectively.Following this curve fitting analysis, the learning rate weakened according to the increasing interval times between the stimuli.[45] With this model, memorization occurs in a three-step process comprising a sensory memory stored in an exceedingly short time, a short-term memory stored temporarily, and a long-term memory stored permanently.Based on the frequency and strength of the stimulus, new information can transmit long-term memory, which is like a rehearsal process.Similar to human learning, the MOSFET synaptic device demonstrated long-term memory properties when the stimulus strength was higher in the pre-synapse terminal.The output current level increased during the application of the eighth pulse sequence.Interestingly, the MOSFET was trained by applying pulses, leading to the linear memorization of synaptic current in the post-synapse, following a first-order function.
where i(t) is the post-synaptic current with a pulse sequence at time t.Here, a and i 0 are the constant values of 1.9 Â 10 À8 and 1.4 Â 10 À7 A for potentiation and 6.2 Â 10 À9 and 3.4 Â 10 À8 A during depression, respectively.The three-terminal MOSFET synapse did not hamper with the signal transmission through the source and drain electrodes using the gate terminal, the trap/ de-trap of the charge carrier was linearly controllable as the synaptic weight in the gate terminal, and the device appeared to offer feasible reliability of the multi-state memory levels.Trapped charges and fixed charges in the high-k metal oxide can be generated during the deposition process, and these charges trap and de-trap electrons in the channel in response to the applied voltage at the gate electrode. [46,47]When a positive pulse is applied to the gate electrode, electrons in the channel are trapped in the metal oxide, resulting in a decrease in the current level.Conversely, when a negative pulse is applied, the trapped electrons in the metal oxide are de-trapped in the channel, leading to an increase in the current level.The three-terminal control enabled the MOSFET synapse device to operate superior to that of the two-terminal RRAM.
The perceptron algorithm is a probabilistic model for information storage and organization inspired by the human brain, and was studied by Rosenblatt [48] in 1958.A pattern recognition simulation can be performed by utilizing measured electrical data to represent the potentiation and depression characteristics of the synaptic device with this simple neural computational model. [49,50]To verify the pattern recognition capability of the FDSOI MOSFET synaptic device, a single-layered perceptron neural network applying a sigmoid activation function was simulated with the Modified National Institute of Standard and Technology (MNIST) database, as shown in Figure 4.An engineered pulse weight was applied to the gate terminal that influences the synaptic conductance, as shown in Figure 4a,b.This result was achieved due to the controllability of the post-synapse weight in the FDSOI MOSFET synapse.These measured conductance results were normalized by dividing the minimum conductance value, which shows that the stronger weight causes a higher rate value between the minimum and maximum conductance during the learning.However, a trade-off exists in the conductance linearity, as the maximum rate of conductance, Δg = g max /g min , is approximately 12.5 and 2, respectively.Following previous study [51] the linearity value was defined and calculated through curve fitting, as shown in Figure S3, Supporting Information.The linearity (A p ) of long-term potentiation (LTP) is comparable, with values of 0.01551 and 0.01361, respectively.However, in Case 2, the linearity (A d ) of long-term depression (LTD) is superior to that in Case 1, with a value of 0.02822.The LTP and LTD values of the FDSOI MOSFET synaptic device were simulated for pattern recognition with a training number for which the rate converged to approximately 0.83 and 0.31 in the case of 1 and 2, respectively.The higher value of Δg leads to a higher recognition rate with the training number, and Δg appears to be more dominant compared to NL for the pattern recognition simulation, as was seen in the preceding research analysis. [52,53]Following these results of the recognition rate, pattern mapping images were also definitely distinctive in case 1 as they featured a higher Δg.The simulation results suggest that the current industrial-grade FDSOI MOSFET can control LTP and LTD via an engineered input pulse and applying a synaptic device that could be leveraged in a variety of areas requiring a neuromorphic system.
In the human brain, neurons consist of axons and dendrites, which receive electrochemical signals from other neurons and transmit them through synapses.When a stimulus exceeds the threshold, neurons are triggered through the opening or closing of ion channels, and this signal is transmitted to the synaptic end.Particularly at the synaptic end, stimulation is conveyed through electrical and chemical compartmentalization of dendrites. [54]For imitating the interaction of biological human brain, hardware-based neuromorphic system consisting the verified 5 Â 6 synapse FDSOI MOSFET arrays and the 10 Â 10 LIF neuron arrays was characterized as shown in Figure 5. Figure 5a shows that the neuron with Ag/HfO 2 /Pt structure exhibited threshold switching behavior, which emulated the LIF property, [55] representing a fundamental spiking neuron behavior following the biological neuron model.The conductive filament of the threshold switching device formed an unstable filament, changing the high resistance state (HRS) below the threshold voltage.Therefore, the device does not require the RESET voltage for the initial HRS, while the stimuli exceed the threshold voltage transmits to synapse. [56,57]As observed in Figure 5b, the firing time decreased as the pulse weight decreased from 2 to 1 V, while the current level of a post-neuron increased.Hardware system of neuromorphic system is illustrated in Figure 5c.Following via etching and tungsten (W) filling, the bottom electrode of the neuron devices was interconnected at the pre-synapse of the FDSOI MOSFET device.When a stimulation applied to the pre-neuron exceeded the threshold voltage, the neuron device fired and transmitted the stimulation to the pre-synapse of the MOSFET device.However, when the stimulation was below the threshold voltage, the neuron device did not transmit the stimulation.Figure 5d shows the post-synaptic plasticity of the hardware system.It shows that there was no change at 1 V below the threshold voltage, but at 3 and 5 V above the threshold voltage, the post-synapse level changed depending on the weight of the stimulus.The transmitted stimulation over the threshold voltage of 5 V was positive, and the post-synapse exhibited a forgetting curve following an exponential formula.The observed synaptic plasticity resulting from the interaction between neurons and synapses implies that the neural system could be applied and developed into a complex neural system, [51] leveraging the verified properties and process system.

Conclusion
A three terminal structure using FDSOI MOSFET device was demonstrated as an electronic synapse that stably controlled biologically inspired synaptic functions.The FDSOI MOSFET synapse device demonstrated conductance margins of 10 3 , sufficient to achieve synaptic plasticity at a 0.4 V gate V read .The synaptic device also featured well-behaved PPF and PTP characteristics, SRDP behaviors, and converted long-term memories from short-term memories following a strong dependence of the pre-synaptic pulse width and frequency.The synaptic conductance was linear and showed superior controllability with the three terminals by the trapping and de-trapping charge carrier.A simulated pattern recognition rate with the synaptic properties of LTP and LTD was increased as Δg increased from strengthening an engineered pulse in the pre-synapse.After verification of the potential to operate with synaptic elements, 5 Â 6 array of this FDSOI FET was connected to a LIF 10 Â 10 crossbar neuron array elements to form a hardware-based neuromorphic system.This hardware neuromorphic system showed the synaptic plasticity following the weight from 1 to 5 V. Our results show that among the three terminal-based transistors, FDSOI FET has the potential to be a synaptic device and that it is possible to develop artificial synapse device as hardware system based on the connection of actual neuron devices.Furthermore, this neural system could be applied and developed into a complex neural hardware system with a focus on low power, based on the observed properties and process system.

Experimental Section
Fabrication of Artificial Synapse and Neuron Devices: The synaptic MOSFET was fabricated on an FDSOI wafer with deposited SiO 2 and Si thin films of 375 nm and 50 nm, respectively, as shown in Figure 6a.
Transistor fabrication was based on the gate last process, where source and drain (S/D) was formed first before gate stack formation.Since our transistor uses high-k gate dielectric and metal gate as a gate stack, this gate-last process was adopted to suppress thermal degradation of high-k gate dielectric during S/D thermal activation step.An isolated SOI wafer was implanted with As and activated at 950 °C.As a gate dielectric, a 5 nm HfAlO x (Al 25%) thin film was deposited by thermal ALD.HfAlO x thin film was deposited by alternating HfO 2 and Al 2 O 3 with 1:1 ratio at 250 °C.Precursors for HfAlO x and Al 2 O 3 were Tetrakis (ethyl-methylamido) hafnium (TEMAHf ) and tri-methyl-aluminum (TMA), respectively, while an oxidant for both films was H 2 O. Transistor channel dimension is with width and length of 80 and 3 μm, respectively.Metal electrodes were DC-sputtered with 150 nm-thick TiN.Afterwards, the remaining process followed the conventional transistor fabrication process.Single neuron device was fabricated in the structure of Ag/HfO 2 /Pt, where 15 nm-thick HfO 2 was processed by ALD using TEMAHf and H 2 O for precursor and oxidant, [58] respectively, and both electrodes were process by DC-s puttering with thicknesses of 50 and 30 nm, respectively.The Lift-off process was used for the patterning.For the hardware-based neuromorphic system formation, the 10 Â 10 LIF neuron array was fabricated on the 5 Â 6 MOSFET synapse array after the via etching and tungsten (W) filling process.
Electrical Measurement Scheme: For investigating memory characteristics, the I d À V g switching curve was measured.The hysteresis from the I d À V g sweep was monitored to obtain the ratio I on /I off , conductance margin, and read voltage (V read ) of the AC pulse for synaptic plasticity.In a three-terminal synaptic device, the synaptic characteristics can be controlled through the pre-synaptic and post-synaptic spikes where the voltage is applied to the gate terminal and the drain terminal, [58,59] respectively, as shown in Figure 1.The engineered AC pulses were applied to the gate electrode while the current value was measured between the drain and source in the gate as V read .To verify the interaction between the synapse MOSFET and the neuron devices, the gate terminal of the MOSFET was interconnected with an LIF neuron array.AC pulses were applied to the Ag top electrode as a pre-neuron, which were then transmitted to the gate electrode as the pre-synapse following the firing.
Physical and Electrical Characterization: The synaptic device for the experimental sample was prepared by a FIB, Quanta model.A milling voltage of 30 kV the device using Ga ions.Cross-sectional images of the prepared sample by the FIB were verified with TEM using a JEOL 2100-F.A Keysight B 1500 semiconductor characterization analyzer measured the electrical synaptic characteristics of the MOSFET devices.Voltage biasing was applied on the gate and drain electrodes and grounded on the source electrode using 10 μm tips.

Figure 1 .
Figure 1.The physical and electrical analysis of FOSOI MOSFET synaptic device.a) Top view OM images of device array and the mask layout image of FDSOI MOSFET synaptic device with channel width 80 μm and length 3 μm.b) High-resolution TEM images of the gate stacks consist of TiN/HfAlO x /Si.EDS mapping of the gate stacks elements Ti, N, Si, Hf, Al, and O. c) When V read is 0.4 V, the memory window is largest at 10 3 A. d) During the two input stimulations, the post-synapse current level increases to approximately 10 nA.

Figure 2 .
Figure 2. Synaptic plasticity following SRDP.a) Dependence of the pre-synaptic pulse widths of 10, 20, 40, 100, and 200 ms, where a longer pulse width results in stronger values of the memorization event.b) Dependence of the pre-synaptic pulse frequencies of 1, 2, 4, 10, and 20 Hz, where the higher frequencies strongly enhanced the synaptic current value.

Figure 3 .
Figure 3. Short-term memory characteristics of PPF and PTP as the pulse interval increases.a) PPF phenomenon represented as the ratio of the postsynaptic response to the second pre-synaptic spike over the response to the first spike.b) PTP characteristic increases the synaptic weight by applying 10 stimulations to the pre-synapse.c) Schematic image of the psychology of learning as studied by Atkinson and Shiffrin.d) Successional potentiation and depression of the synaptic device where the current level increases linearly with the applied sequential pulse.

Figure 4 .
Figure 4. Simulation of the FDSOI MOSFET synaptic device using a simple perceptron neural model.a) Normalized LTP and LTD for case 1 (Δg = 12.5,A p = 0.01552, A d = 0.07976), b) Normalized LTP and LTD for case 2 (Δg = 2, A p = 0.01361, A d = 0.02822), and c) Recognition rate and pattern mapping images with the training number applied to a single layer network for cases 1 and 2.

Figure 5 .
Figure 5.The hardware system with the FDSOI MOSFET synapse array (5 Â 6) and crossbar neuron array (10 Â 10).a) A neuron switching property of the Ag/HfO 2 /Pt structure.b) LIF property of a neuron device following the weight with 1 to 2 V.The neuron receives and transmits electrical signals when it is above the threshold as in cartoon.c) Hardware system with the FDSOI MOSFET synapse array and the crossbar neuron array that were interconnected using W. The crossbar neuron array of the 10 μm line width deposited on the FDSOI MOSFET array devices.d) The synaptic plasticity of a hardware system that showed the change of synapse current level according to from 1 to 5 V weight.

Figure 6 .
Figure 6.An SOI MOSFET synaptic device.a) Structure of the FDSOI MOSFET operating as a synaptic memory device.The gate and source terminals perform as the pre-synapse and post-synapse, respectively.In the pre-synapse, synaptic spikes changed the current level of the post-synapse output.b) Schematic illustration of a biological neuron synapse.The gap between two neurons is the synapse, which responds to physical-chemical synaptic weights.