Tuning Local Conductance to Enable Demonstrator Ferroelectric Domain Wall Diodes and Logic Gates

Fundamentally, lithium niobate is a good electrical insulator. However, this can change dramatically when 180° domain walls are present, as they are often found to be strongly conducting. Conductivities depend on the inclination angles of walls with respect to the polarization axis and so, if these angles can be altered, then electrical conduction can be tuned, or toggled on and off. In ≈500 nm thick z‐cut ion‐sliced thin films, localized wall angle variations can be controlled by both the sense and magnitude of applied electrical bias. It is shown that this results in diode‐like behaviour, allowing half‐wave rectification at modest frequencies. Importantly, it is experimentally demonstrated that these domain wall diodes can be used to construct “AND” and inclusive “OR” logic gates, where “0” and “1” output states are clearly distinguishable. Extrapolation to more complex arrangements shows that output states can still be distinguished in two‐level cascade logic. Insights show that simple logic circuits can be realized by localized manipulation of domain wall conductivity. Our research complements that by Jie Sun et al. (Adv. Funct. Mater. 2207418 (2022)), where NOT, NOR, and NAND gates are realized by moving conducting domain walls to make or break electrical contacts.


Introduction
While bulk ferroelectrics are generally either insulators or wide band-gap semiconductors, it is now clear that ferroelectric domain walls (interfaces in ferroelectric microstructures that separate differently oriented domains) can show significantly enhanced electrical transport. [1][2][3][4][5][6][7][8] In some materials, such as bismuth ferrite, even though band-gap alterations with respect to bulk might be expected at domain walls, [9,10] observed conductivity seems to be primarily extrinsic in origin, controlled DOI: 10.1002/apxr.202200095 by the extent to which walls act as aggregation sites for point defects. [11][12][13][14][15] In other systems, polar discontinuities at so-called "charged walls" lead to intense local fields, and the associated enhanced domain wall conduction seems to be more intrinsic in nature. Bandbending is thought to be sufficient to either push the conduction band below the Fermi level (creating electronic conduction within the wall) or raise the valence band above it (creating hole conduction), depending on the sense of the polarization discontinuity present (being either "head-to-head" or "tail-to-tail"). [5,16,17] In head-to-head charged 180°domain walls in lithium niobate (LiNbO 3 or LNO), a correlation between the size of the polar discontinuity and the observed conductivity has been categorically established. [17] The angles of domain wall inclination with respect to the polarization axis determine the magnitude of the polar discontinuity and can be actively controlled by applied electric fields, which monotonically change associated conduction levels. Previous work [18][19][20][21] has shown that, in the specific case of z-cut ion-sliced LNO thin film capacitor structures, with thin film gold chromium (AuCr) lower electrodes, 180°head-to-head domain walls, created by partial ferroelectric switching, are initially strongly inclined and highly conducting (see schematic in Figure 1a). With positive bias applied through surface electrodes or conducting atomic force microscopy (cAFM) tips, the inclination angles of the walls appear to be maintained or enhanced and strong conductivity remains. [18] However, when a modest negative bias is applied (or if the films are left in ambient conditions for several days), regions of the walls extending some ≈50-150 nm beneath the thin film surface "straighten" (better align with the polar axis) and local domain wall conductivity collapses [18,20] (see schematic in Figure 1a and crosssectional transmission electron microscopy [TEM] image in Figure 1b). "Straightened" regions break the percolation pathway along the conducting domain wall conduits that bridge the interelectrode gap and thereby create a high resistance state for the device as a whole. This variation in near-surface domain wall inclination under positive and negative bias should be expected to result in a strongly asymmetric current-voltage characteristic, with currents shutting down for negative bias and developing progressively more strongly for positive bias applied to the Electric field control of near-surface domain wall inclination angle. a) Domain walls near the top surface of the LNO thin film can be manipulated with modest applied bias: positive voltages tilt them away from the polar axis, leading to a "conducting" state, whereas negative voltages cause them to align parallel to the polar axis, resulting in an "insulating" state. This has been confirmed by b) cross-sectional transmission electron microscopy (TEM), c) piezoresponse force microscopy (PFM), and e) conductive atomic force microscopy (cAFM) investigations: domain walls (initially set into a low near-surface inclination state by a −1 V cAFM scan (highlighted in blue)) expand radially after a +10 V cAFM scan (highlighted in red). d) A 10 nm shift in domain wall position can result in up to 11°change in near-surface domain wall inclination (depth of the subsurface domain wall region is estimated between 50 and 150 nm). [18] e) The enhanced current response is observed in cAFM data collected at +6 V compared to −1 V. Data shown is the average of the currents observed in the 11 cAFM scan lines highlighted in (c). Horizontal and vertical scale bars in (c) show 20 and 5 nm, respectively.
LNO top surface. In other words, a diode-like response should be expected.
Herein, we present experimental evidence to confirm that domain wall-enabled diodes can indeed be generated in z-cut ionsliced LNO thin films, as a direct result of electric-field control of the subsurface domain wall inclination angle. We also show that alternating current rectification, demonstrated recently in x-cut material, [22] can also be seen in these z-cut films. Significantly, we experimentally show that LNO domain wall diodes can be successfully used to realize simple "AND" and inclusive "OR" logic gates, which present a clear distinction between "0" and "1" output states. When the observed characteristics of the domain wall diodes are incorporated into circuit simulation software, we have also been able to show that output state distinguishability is maintained even in two-level cascade logic configurations. Simple Boolean logic gates, the operation of which is entirely dependent on the local manipulation of domain wall conductivity, have hence been established, further pushing forward possibilities for domain wall-based nanoelectronics. [23] The insights developed are complementary to those seen by Sun et al. [24] where NOT, NOR, and NAND logic gates were realized by moving conduct-ing domain walls in and out of contact with patterned surface thin film electrodes. [24] Importantly, however, the mechanisms of operation involved in the two studies are fundamentally different.

Electric Field Control of Subsurface Domain Wall Inclination Angle
The polarization direction of the LNO ferroelectric film in the as-received samples was oriented out-of-plane and perpendicular to the sample surface. However, when sufficiently large electrical biases were applied to the top electrodes, domains of opposite polarity (with polarization oriented into the surface plane) would nucleate and grow, traversing the interelectrode gap, to form conical (or needle-like) reverse domains, [18][19][20][21] bounded by charged head-to-head domain walls. Recent investigations, on the same kinds of heterostructures, have shown the positive coercive voltage for such switching to be ≈+19 V; for switching in the opposite sense the coercive voltage was found to be ≈−33 V. [25] In addition, cross-sectional TEM work [18][19][20][21] has revealed that the wall angle www.advancedsciencenews.com www.advphysicsres.com within a ≈50-150 nm thick subsurface region can vary strongly, being almost parallel to the polarization direction in some instances (and hence uncharged and expected to be electrically insulating), and in others, being inclined by angles between 10°a nd 20°away from the polar axis (hence charged and expected to be strongly electrically conducting). Bias-induced changes in the wall inclination angle, in this subsurface region, can be inferred by monitoring the position of the locus of the domain walls on the top surface of the LNO. [18] We used this technique to confirm the manner in which applied bias levels affected both the subsurface domain wall inclination behavior and associated wall conductivity in our specific samples: after the initial application of negative bias (−1 V), which was expected to align subsurface walls parallel to the polar axis, subsequent positive bias (+10 V) caused domain wall traces (highlighted in red in Figure 1c) to move by around ≈10 nm, in a sense that increased the fractional area occupied by the "downwardly" oriented conical domains. Assuming a minimum malleable subsurface wall section length of 50 nm, [18] this corresponds to a maximum of 11 ○ change in the local subsurface wall inclination angle (Figure 1d). The correlation between the inferred domain wall tilt variation and domain wall conductance was confirmed by cAFM current mapping at the domain wall using −1 and +6 V tip bias (Figure 1e). Diffuse current signals over the region in the vicinity of the domain wall (≈100 nm wide) are suspected to be due to both the finite size of the atomic force microscopy (AFM) tip (maintaining electrical contact with the domain wall over a range of tip positions) and a tendency for some current to traverse short lengths on the LNO surface before reaching high conductivity source-drain domain wall conduits.

Diode Behavior and Current Rectification
As expected from the bias-induced domain wall tilt variations and associated changes in conduction behavior outlined above, clear diode-like current-voltage responses could readily be obtained in simple parallel-plate capacitor structures in which mixed domain states had been produced through partial poling (Figure 2a). Such domain wall diodes were found to effectively enable alternating current (AC) rectification, but for relatively thick films (≈500 nm) this was only obvious at low frequencies: for example, half-wave rectification output is clear at 1 Hz (Figure 2d). However, when the frequency is increased to 100 Hz (Figure 2e), the response begins to show clear evidence of the superposition of domain wall transport and a capacitive current associated with the dielectric domains, acting electrically in parallel. When the frequency is increased to 1 MHz, rectification is apparently almost completely lost (Figure 2f). Perhaps near-surface domain wall tilt variations are no longer able to respond to the relatively rapidly varying AC input voltages, and hence are no longer able to contribute to the overall AC current and so capacitive currents completely dominate. This would be consistent with the work of Schröder et al., [26] who made a similar observation on super-bandgap illuminated 300 μm thick z-cut LNO parallel plate capacitors, where they found that the sample with domain walls exhibited purely capacitive behavior at frequencies greater than ≈200 Hz. We did notice, however, that when the top electrodes were reduced by an order of magnitude in area (from ≈10 4 to ≈10 3 μm 2 ) or when the LNO was milled to reduce its thickness (from ≈500 to ≈330 nm), rectification to higher frequencies could be seen. Figure 2b shows the mean value of the rectified or partially rectified, voltage output as a function of frequency and film thickness, for capacitor structures with top electrode areas around 1400 μm 2 . Any nonzero mean indicates some level of rectification. As can be seen in Figure 2c, for films around 330 nm thick, partially rectifying responses persisted to almost 10 MHz.

Diode-Resistor Logic Gates
Diode-resistor gates are a standard construction for the realization of Boolean logic operations. [27] Figure 3a illustrates a typical diode-resistor potential divider arrangement that can be used to create "AND" gate binary output (V out ) from two binary inputs (V 1 and V 2 ). Experimentally, in our case, two partially switched LNO thin film capacitor structures (domain wall diodes), with thin film silver (Ag) top electrodes, were used along with a substantial 1 GΩ resistor, placed between the diodes' positive terminals (upper electrodes) and the +5 V supply; input signals were applied to the negative terminals of the domain wall diodes.
When both inputs are set to logic "1" (+5 V, Figure 3c), there is no voltage drop in the circuit, and an output voltage of ≈+5 V is measured (Figure 3d). However, when one of the inputs is set to logic "0" (0 V), a potential drop across the circuit is established. Since the "on" resistance of the diodes (diode resistance seen in the forward direction after the barrier is surpassed) is on the order of MΩs (significantly lower than 1 GΩ) ( Figure S4, Supporting Information), a relatively small fraction of the voltage is dropped across them, and as a consequence, V out registers between 1 and 2 V (slightly above the barrier voltage) (Figure 3d). Slight differences in the voltages recorded are due to the slight differences in the current-voltage characteristics of the two domain wall diodes used. When both inputs to both diodes are set to logic "0" (0 V), both act under forward bias, and since the resistance of the two diodes acting in parallel will be reduced further, a larger potential drop across the resistor develops and V out is reduced to ≈1 V. Provided the "0" logic output state is taken to be below ≈2 V, the logic output is "0" for all combinations of logic inputs, save for the case in which both inputs are "1" (see the truth table in Figure 3f) and the "AND" gate is hence successfully demonstrated.
The diode-resistor circuit used to realize an "OR" logic gate is given in Figure 3b. Here, the 1 GΩ resistor is placed between the negative terminals of the two domain wall diodes and the ground, and input signals are applied to the positive diode terminals. The output (V out ) is the voltage dropped across the resistor. When both inputs (V 1 and V 2 ) are set to 0 V (logic "0" states), there is no bias across the circuit as the potential is uniformly 0 V at all points. Hence the measured V out is 0 V (Figure 3c,e). However, if either or both of the logic inputs are "1" (+5 V), then the potential drop developed again acts in a forward bias sense across the diodes and their parallel resistance is relatively low. Most of the potential drop, therefore, occurs across the 1 GΩ resistor, and since this is the output voltage, ≈+3-4 V is measured. The output logic state is hence "1" (provided it is defined as being above 3 V) for all input logic combinations, save for the case when both inputs are "0" (see truth table Figure 3g). A domain wall diode-enabled inclusive "OR" logic gate hence results.  Figure S2, Supporting Information). When a sinusoidal input voltage is applied at 1 Hz, d) the domain wall diode successfully rectifies the voltage across the load resistor (V out ) according to the I-V characteristics shown in (a). In this case, the capacitor has little influence because of its extremely high impedance at this low frequency. e) When the input frequency is increased to 100 Hz, the capacitive impedance reduces, and the output voltage waveform becomes distorted. f) At 1 MHz of input frequency, output current becomes fully capacitive, which is inferred by the fact that output voltage becomes almost fully symmetric about the x-axis. This implies that asymmetric domain wall current dies at 1 MHz. b) A cut-off frequency of asymmetric domain wall current response can be increased by decreasing the film thickness. Here, the mean of V out (a measure of the rectified component) was monitored up to ≈1 MHz of input frequency, and data points associated with each thickness were fitted using power functions. c) Cut-off frequencies for rectification were then estimated by extrapolating each curve fit to the noise floor for the measurements.
Adv. Physics Res. 2023, 2, 2200095  Figure 3. Experimental realization of logic gates based on two domain wall diodes and a resistor. Circuit configurations are shown, consisting of two domain wall diodes and a resistor, to realize a) "AND" and b) inclusive "OR" gates, respectively. For the "AND" gate shown in (a), when c) both inputs are set to logic "1" (+5 V), d) the output becomes logic "1," otherwise it is set to logic "0," which is defined by the blue-colored voltage band. For the "OR" gate shown in (b), when c) either V 1 or V 2 or both are set to logic "1" (+5 V), the output generated is logic "1", e) defined by the blue-colored band; otherwise it is set to logic "0" (0 V). Input-output relationship of f) "AND" and g) "OR" gates are demonstrated in truth tables.
The current-voltage characteristics of the two domain wall diodes associated with the logic gate data shown in Figure 3 were explicitly measured ( Figure S4, Supporting Information) and the information was used to develop predicted responses in two-level cascaded Boolean logic circuits, using the LTspice analog electronic circuit simulation software. We simulated two different scenarios ( Figure S5, Supporting Information): "AND" gates in the first level followed by an "OR" gate in the second level (Figure 4a), and "OR" gates in the first level followed by an "AND" gate in the second level (Figure 4b). In both cases, generated output logic levels fell into the correct logic band (ideal logic levels are shown in Figure 4d,e). Note, however, that in both cases, the voltage gap between defined logic states reduced significantly to <≈1 V. There are two reasons for this: first, the logic gate in the second stage experiences modified logic voltages generated by the first stage (Figure 3d,e) at its input; second, the voltage generated at the output of the first stage is divided between the input resistance of the second stage and the output resistance of the first stage. This depresses the modified logic levels experienced by the second stage, so the gap between the logic levels at the output of the second stage is reduced further. Nevertheless, if states are defined appropriately, then the cascade logic using domain wall-enabled diodes is successfully demonstrated.
Diode-like behaviors have previously been observed in the characterization of charge transport along domain walls, not only in LNO [18,22,28,29] but also in rare earth manganites such as ErMnO 3 . [30] However, these previously seen current-voltage asymmetries have almost entirely been associated with the contact resistance at the electrode-wall interface [30] and have hence been reflective of barrier physics, rather than being due to changes in the inherent behavioral properties of domain walls themselves. Observations made by Zhang et al. [22] are perhaps the exception, as asymmetry in device conduction in their x-cut LNO coplanar capacitors appeared to be the result of making and breaking domain wall-electrode contacts under different senses of applied bias: one sense caused electrode-ferroelectric "interfacial" domains to contract to allow percolative domain wall pathways to be established between the source and drain electrodes, while the other caused the "interfacial" domains to grow and hence break domain wall enabled source-drain electrical contact. This diode mechanism of making and breaking contact between domain walls and electrodes differs from that seen in our study, as the conductivities of the domain walls themselves were not explicitly manipulated; nevertheless, the half-wave rectification and creation of NOT, NOR, NAND, and OR logic gates in very recently published work (performed in parallel with the research we report herein) is highly noteworthy. [24,31] Figure 3: a) "AND" gates in the first layer followed by an "OR" gate and b) "OR" gates in the first layer followed by an "AND" gate. c) All possible logic input combinations are applied through time, and d,e) the output voltage is simultaneously recorded. For both cases, the correct output logic levels are successfully maintained in output voltages with ≈1 V of separation between "1" and "0."

Conclusions
We have shown that electrical diodes, rectifiers, and logic gates can be realized in ferroelectric thin film LNO coplanar capacitor structures. Although operationally slow, and similar in response to those investigated by Zhang et al. [22] and by Sun et al., [24] the domain wall diodes developed in our work are conceptually unique. Rather than acting as mobile interconnects among arrays of fixed devices or contact points, our diodes operate because the walls themselves change their conductivities through localized changes in inclination angle; the walls, therefore, are the active devices that switch conductivity on and off internally. Such a notion is important for domain wall electronics development, as it shows that domain walls can simultaneously constitute both interconnects and devices (also seen in the very recent demonstration of domain wall p-i-n junctions by Qian et al.). [32] Since walls can be created, moved, and destroyed, this suggests the genuine possibility of fully ephemeral dynamic nanocircuitry and information processing in the future. [33]

Experimental Section
Experiments involved bias-induced domain wall injection and manipulation within ≈300-500 nm thick ion-sliced single crystal thin films of undoped congruent z-cut LNO. These films were bonded to a 150 nm thick chromium-gold-chromium electrode stack and deposited onto a 2 μm silica layer on a 500 μm thick z-cut lithium niobate wafer (in a commercial production process). Ag top electrodes were thermally evaporated onto the LNO surface, through hardmasks, to create simple parallel plate capacitor structures.
For diode and logic gate experiments, samples were then fixed on printed circuit boards (PCBs); the lower chromium-gold-chromium electrode was contacted using conductive silver paint on the sample sidewalls. 25 μm-diameter aluminum wire was wire-bonded to both the Ag top electrodes (which were ≈100 × 100 μm 2 in size) and contact pads on the PCBs, to make a robust sample for handling during electrical characterization. The wire-bonded samples were placed in an aluminum enclosure to protect them from electromagnetic noise and electrical connections to the feedthroughs in the enclosure were made using triaxial cables. A Keysight B2910BL Source-Measure Unit was used for direct current (DC) currentvoltage measurements, using 100 ms long voltage pulses. Delay, hold, and measurement times were set as 0, 80, and 20 ms, respectively. 10 A of current compliance was set for all measurements. For probing rectification behavior, an Agilent 33220A Arbitrary Waveform Generator was employed to generate sine waves in the 1 Hz-1 MHz frequency regime (5 V in amplitude). A Rohde & Schwarz RTC 1002 digital oscilloscope was used to monitor any rectified AC voltages. For logic gate characterization, a Keysight E3631 single-output DC power supply and a Keysight E3641 triple-output DC power supply were used to generate digital input signals. Currents were measured with a Keysight B2910BL Source-Measure Unit, which was connected in series to the resistor. Electronic circuit simulations used LTspice analog electronic circuit simulation software.
For rectification experiments on devices with different thicknesses (Figure 2b,c), an LNO film was first polished using a dimple grinder to create a thickness gradient on the film. ≈37 × 37 μm 2 Ag electrodes were then thermally evaporated on the polished region. Parallel plate LNO capacitor devices were contacted with tungsten microprobes. Liquid In-Ga-As was used to enhance the quality of electrical contact between the microprobes and Ag electrodes. Similar measurement conditions as described above were then used.
An MFP-3D Infinity AFM system from Asylum Research, equipped with a high voltage conducting atomic force microscopy (HV-cAFM) holder, was used for some local poling experiments and PFM/cAFM scans.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.