Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal‐oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28‐nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1‐MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd.


INTRODUCTION
Modern wireless and wireline data communication systems impose severe requirements on phase noise (PN) at a given frequency offset from the carrier [1][2][3]. Accurate analysis of the behavior of oscillators has been the subject of intense investigation [4][5][6][7][8]. An effective method for providing qualitative and quantitative predictions of PN in integrated oscillators is based on the impulse sensitivity function (ISF) [9]. In [10,11], the authors addressed how to derive accurate evaluations of the ISF in relation to simulation settings. Moreover, the authors in [10,11] report topological investigations carried out for oscillation frequencies between 1 and 100 GHz, under the same design conditions in a 28-nm complementary metal-oxide semiconductor (CMOS) technology, taking into account both flicker and thermal noise contributions. The results showed for the first time that there is no best topology in the absolute sense as it may have appeared from previous studies reported in the literature limited to oscillators operating at a few gigahertz, but the opportunity of identifying the topology exhibiting the lowest PN depends also on the operating frequency range. Moreover, the use of the ISF allowed the separation of the total PN in its two components because of flicker and thermal noise from each device in the oscillator circuit. In particular, it was observed how the tail transistor plays a significant role in the PN degradation occurring in the Colpitts oscillator circuit topology, here shown in Figure 1. In detail, the results in [11] show that minimizing the flicker noise in the output spectrum is particularly important because the 1/f 3 PN region of integrated CMOS oscillators usually extends beyond 1 MHz offset from the oscillation frequency as a consequence of the deep sub-micrometer devices featuring 1/f corner frequencies of several tens or hundreds of megahertz. On the basis of these results, it is worth exploring techniques that allow reduction of PN, in particular due to the tail transistor.
An effective technique for the reduction of PN due to the tail transistor in CMOS LC oscillators was proposed in [12,13]. Namely, the inductive degeneration of the tail transistor, which consists of introducing a high value off-chip inductance as a degeneration impedance to the source node of the tail transistor in a common-source cross-coupled differential pair oscillator circuit topology, in the specific case equal to 100 μH for an oscillator circuit operating around 2 GHz and implemented in 0.35-μm CMOS technology.
Moreover, the technique of noise filter was proposed in [14][15][16] for the reduction of PN due to the tail transistor in CMOS LC oscillators. In particular, it was capable to reduce the up-conversion of low-frequency noise. It consists of replacing the tail transistor with a band-stop filter, referred therein [14][15][16] as noise filter, in a common-source cross-coupled differential pair oscillator operating close to 1.1 GHz and fabricated in 0.35-μm CMOS technology.
These techniques for the reduction of PN due to the tail transistor are here applied to the Colpitts oscillator circuit topology of Figure 1. In particular, these techniques will be adopted and analyzed for a single-ended Colpitts topology designed in a 28-nm bulk CMOS process.
Our analyses will allow us to show mathematically and prove by means of simulations that there is a specific degeneration inductance value for M 2 in Figure 1, for which the PN of the Colpitts oscillator reaches a minimum. Furthermore, that there is a specific inductance value that tunes the resonance frequency of the noise filter to the oscillation frequency and for which the PN reaches a minimum, confirming the discussion in [14]. The analyses will allow also the evaluations about the dependence of the oscillation frequency on the degeneration inductance and filter components.
Moreover, a third technique for PN reduction, namely, optimum current density, will be proposed and analyzed in detail. It consists of biasing an oscillator circuit topology with the optimum bias current density for minimum PN. This technique of the optimum bias current density applied to specific metrics of interest has been extensively used for the design of low-noise amplifiers with minimum noise figure and the design of power amplifiers with a maximum linearity range [17,18]. In a few cases, it has been also mentioned in achieving low PN in differential Colpitts and commonsource cross-coupled differential pair oscillators [19][20][21]. Here, it will be applied to a single-ended Colpitts oscillator circuit topology with the objective of providing adequate theoretical proofs of the benefits for its extensive use in oscillators. Our analyses will allow for the first time to gain insight into the theoretical details of this technique and its effective application, in addition to the oscillator performance optimization with respect to transconductance-to-current ratio (g m /I D ); for example, [22].
Overall, the primary objective of this study reported here is to analyze by circuit theory and verify by circuit simulations, compare the results, and highlight the benefits emerging from the aforementioned PN reduction techniques applied to the Colpitts oscillator circuit topology. In particular, in our theoretical analyses, we will consider the equivalent circuit of the transistors with the typical parameters of a typical 28-nm bulk CMOS technology commercially available. The details of the equivalent circuits will be given in the related sections. The circuit simulations will be carried out within the Cadence design environment, which takes into account the full models of the transistors of a process design kit commercially available, including all their non-idealities and parasitic components. In our analyses, we will exclude the effects of the layout interconnections, because the additional parasitic components introduced by the layout could mask the results of the topological properties that we would like to bring to the light. Moreover, the exclusion of the effects of the layout interconnections is compliant with the expectations from theoretical analyses, because the additional parasitic components introduced by the layout would lead to cumbersome expressions that could limit the understanding of the results and opportunities to identify useful insights. Capacitors will be considered as ideal components, whereas a typical quality factor (Q) of 10 will be considered for all the spiral inductors [23]. Because the quality factor of the LC tank has a heavy impact on the PN, this condition will assure that all the oscillator circuits will be compared under common conditions [24][25][26]. All the transistors have minimum length. The reference values of the circuit components used for the theoretical analyses and circuit simulations are reported in Appendix. PN circuit simulations are carried out by means periodic steady state and periodic noise analyses in SpectreRF simulator. Details on simulation settings for accurate results can be found in [10,11].
The paper is organized as follows. Section 2 addresses the inductive degeneration of the tail current transistor in a Colpitts oscillator. The analytical expressions of the oscillation frequency and the optimum inductance are derived by means of circuit theory and validated by means of the results provided by SpectreRF simulations in Cadence. Section 3 addresses the noise filter technique where the tail current transistor is replaced by a passive band-stop filter, that is, noise filter. The analytical expressions of the oscillation frequency and the optimum inductance are also derived by means of circuit theory and compared with the results obtained by means of SpectreRF simulations. Section 4 addresses the optimum current density for minimum PN for the Colpitts oscillator circuit topology under examination. The theoretical results are validated by the results obtained from SpectreRF simulations for oscillation frequency of 10 GHz. Finally, conclusions are drawn in Section 5.

INDUCTIVE DEGENERATION
In this section, we will derive an analytical expression for the oscillation frequency (f 0 ) of the Colpitts oscillator circuit topology in which we introduced an inductive degeneration (L 2 ) to the source node of the tail current transistor (M 2 ), as shown in Figure 2(a).
In order to extract appropriate evaluations about the improvement of performance with respect to the traditional topology of Figure 1, the oscillator circuit design will be carried out under the same transistor size, power and current consumptions, and inductance of the tanks and their quality factors, as in [10,11]. Specifically, the transistor width is 30 μm, whereas the power consumed is 6.3 mW. V DD is equal to 1 V. The tank inductance is equal to 500 pH.

Oscillation frequency
The Colpitts oscillator circuit topology with an inductively degenerated tail current transistor (M 2 ) is shown in Figure 2(a). Its small-signal equivalent circuit is shown in Figure 2 transconductance (g m ), gate-to-source capacitance (C gs ), gate-to-drain capacitance (C gd ), source-tobulk capacitance (C sb ), drain-to-bulk capacitance (C db ), and output resistance (r o2 ). In the interest of a low complexity of the derived equations, the small-signal output resistance r o1 of M 1 as well as the polysilicon gate resistance r g of M 1 and M 2 are neglected. Later, we will see that this working hypothesis is acceptable. If the small-signal output resistance r o2 of M 2 is also neglected, it can be proved that the oscillation frequency f 0 does not depend on L 2 . Thereby, in order to take into account the effect of L 2 in f 0 , r o2 is considered in the equivalent circuit. R p represents the total load resistance of the LC tank, including the effect of the finite Q and the resistance seen from the source of M 1 scaled by the capacitive divide factor. C p is the parasitic capacitance at the drain node of M 1 , equal to the sum of C db1 and C gd1 . C p2 is the parasitic capacitance at the source node of M 2 , equal to the sum of C gs2 and C sb2 . C 1 appears in parallel with C gs1 , C sb1 , C gd2 , and C db2 . Their sum can be represented as an equivalent capacitance C 1eq .
In order to excite the circuit into oscillation, we insert a current stimulus I in at the source of M 1 . We can now write that (2) From Kirchhoff current law (KCL) at the source of M 2 it derives that By applying the KCL at the source of M 1 and the output node, we can write Solving (4) with respect to V gs2 and combining with (5), we obtain Additionally, V gs1 is given by Moreover, from KCL at the output node, which can be expressed as a function of V gs1 as follows Using (6) in (7), expressing the result as a function of V gs1 and equating to (9), we can express the closed-loop transfer function V out /I in as a ratio. By equating the imaginary part of the denominator of V out /I in to zero, we find that the oscillation frequency is given by (10)- (13). To reduce the complexity of the expression, C p2 is neglected in the equation for f 0 reported hereinafter.
where  Figure 3 shows the results obtained by theoretical expressions of the oscillation frequency provided by (10)- (13), as a function of the LC tank capacitance C tank expressed as The simulations are repeated for three values of L 2 in order to demonstrate the weak dependence of the oscillation frequency f 0 on L 2 . This means that L 2 can be sized to satisfy other design requirements, with limited effects on the oscillation frequency. This result will be exploited in the next section. Moreover, note that the oscillation frequency predicted by (10)-(13) closely follows the simulation results obtained by SpectreRF. In particular, the maximum difference amounts to about 50 MHz, observed for L 2 = 2 nH. Thereby, the aforementioned simplifications in the derivation of (10)- (13) are justified for an accurate first-order prediction of the oscillation frequency f 0 .

Optimum inductance for minimum phase noise
Here, our aim is to explore the dependence of PN on L 2 and to derive under which condition the PN in the output spectrum of the Colpitts oscillator circuit topology of Figure 2(a) could be minimized. The theoretical results will be compared with respect to the simulation results obtained by means of SpectreRF.
From [27], we can write where V 1 and I 1 are the amplitudes of the fundamental harmonics of the source voltage and drain current of M 1 , respectively. V tank is the amplitude of the fundamental harmonic of the tank voltage. G m1 is the large-signal transconductance of M 1 , and n is the capacitive divide factor equal to C 2 / (C 1eq + C 2 ). The power spectral density of the flicker noise current of M 1 can be written as follows [28]: where K is a process dependent parameter, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, W and L are the width and length of M 1 , respectively, and f is the frequency.
Moreover, the small-signal transconductance g m1 of M 1 and the PN for the Colpitts oscillator due to flicker noise from M 1 can be expressed as [29][30][31][32] where ϕ is equal to ω 0 t and Φ is half the conduction angle defined by with V GS and V T being the direct current (dc) gate-to-source voltage and the threshold voltage of M 1 , respectively. Moreover, N = 1 for the single-ended Colpitts, q max is the maximum charge displacement across the tank capacitance, Δω is the angular frequency offset from the oscillation frequency, cos ϕÀcos Φ , and Γ 2 id;dc is the square dc value of the ISF given by [30][31][32] where Γ 2 id;rms can be derived from [29] Thereby, (20) now becomes In order to take into account the cyclostationarity of the noise from M 1 , we replace Γ 2 id;rms in (24) with Γ 2 id;eff ;rms , that is, the square root mean square value of the effective ISF [8,29] Γ 2 id;eff ;rms ¼ Combining (18) and (19), the flicker noise current can be rewritten as follows Thereby, using (26) into (24), we yield Then we substitute Δf and Γ 2 id;eff ;rms in (27) as expressed by (18) and (25), respectively. Rearranging the result by using (15)-(17), we arrive in the following expression In order to excite the Colpitts oscillator circuit topology of Figure 2(a), a stimulus can be applied to different nodes. The type of stimulus (voltage or current) must be chosen such that when it is set to zero, the circuit returns to its original topology [33]. The large-signal equivalent circuit of the Colpitts oscillator topology of Figure 2(a) is shown in Figure 4.
V in is a voltage stimulus applied to the gate of M 1 . Transistor M 1 is represented as a transconductance amplifier according to the describing function analysis [27]. G m1 is the large-signal transconductance of M 1 , equal to the ratio of the fundamental harmonic of the drain current of M 1 to the fundamental harmonic of the gate-source voltage of M 1 . For transistor M 2 , a simplified largesignal equivalent circuit is used [34,35]. This equivalent circuit is obtained by considering the simplified transistor model with the large-signal transconductance (G m ), gate-to-source capacitance (C GS ), gate-to-drain capacitance (C GD ), source-to-bulk capacitance (C SB ), drain-to-bulk capacitance (C DB ), and output resistance (R DS ). G m2 is approximated by the average value of g m2 during the oscillation period. C 1 appears in parallel with C GD2 and C DB2 . Their sum can be represented as an equivalent large-signal capacitance C 1EQ . C P2 is the parasitic capacitance at the source node of M 2 , equal to the sum of C GS2 and C SB2 . R DS2 is approximated by the average value of r o2 during the oscillation period. For simplicity of our analysis, it is assumed that, at the oscillation frequency of 10 GHz, extrinsic components as well as the gate and substrate resistances have a negligible effect to PN [36,37]. Later, we will verify that this assumption is acceptable.
We can now write We will now calculate the equivalent transconductance for the circuit of Figure 4 with respect to the voltage stimulus V in , that is, G m,eq1 = I out /V in . Next, we will determine L 2 for which the flicker and thermal PN components at the output of the Colpitts oscillator circuit topology of Figure 2(a) reach the minimum values. For simplicity of the derived equations, C P2 will be neglected.
From Kirchhoff voltage law then from KCL at the source of M 2 which can be rewritten as Moreover, from KCL at the source of M 1 , Finally, from KCL at the drain of M 1 , Furthermore, we can substitute V GS1 in (35) with its value given by (31). Using (31) and (33) into (34), solving with respect to V x and substituting for V x in (35), G m,eq1 can be written as By replacing G m1 with G m,eq1 in (28), taking the derivative with respect to L 2 and equating to zero, we find the value of L 2 for which the flicker noise present at the output of the Colpitts oscillator circuit topology of Figure 2(a) reaches a minimum, that is, 624 I. CHLIS, D. PEPE AND D. ZITO A similar derivation can also be performed for the PN component because of the thermal noise of M 1 , M 2 , L 2 , and the LC tank. From [27,29], we have where The PN expression due to the thermal noise is where K B = 1.38 × 10 À23 V × C/K is the Boltzmann constant and T is the absolute temperature.
Combining (42) and (43), we obtain Moreover, (44) can be rewritten as Taking the absolute value of (46), equating to (47), and then solving with respect to I B and equate to zero, we find that the value of L 2 , for which the thermal noise at the output of the Colpitts oscillator circuit topology of Figure 2(a) reaches a minimum, is where The total PN expression is found by adding the flicker and thermal PN components given by (28) and (45), respectively, as follows: The total PN given by (52) is plotted in Figure 5 versus L 2 , at an average bias current of 6.3 mA, for an oscillation frequency of 10 GHz, at a 1-MHz frequency offset. C 1 and C 2 have equal size, and their value changes according to the value of L 2 , keeping f 0 constant at 10 GHz. Moreover, V B3 and V B4 are chosen to have the same average current, also considering the voltage drop across the parasitic resistance of L 2 . Note the agreement between the theoretical derivations and the SpectreRF simulations. In particular, the maximum difference between the results of the theoretical derivations and circuit simulations is about 2 dB.
Thereby, the aforementioned simplifications in the derivation of (39)-(41) and (49)-(51) are acceptable for a first order and lead to a relatively accurate derivation of the optimum inductance value (L 2 ) for which the Colpitts oscillator circuit topology of Figure 2(a) exhibits a minimum PN.
From SpectreRF simulations, for an oscillation frequency of 10 GHz, a minimum PN is achieved for L 2 equal to about 4 nH. This value of inductance can be obtained by means of integrated inductors.
The existence of an optimum value for L 2 for minimum noise contribution from M 2 can be explained as follows. Assuming that the tail transistor M 2 generates a flicker and thermal noise current with power equal to I 2 n , then the power of the noise current at the drain of M 2 , I 2 n;out , is equal to I 2 n = Z S g m2 þ 1 ð Þ 2 , where Z S is the impedance of the parallel combination of L 2 with the capacitance present at the source node of M 2 , which is C p2 shown in Figure 2(b).
I 2 n;out versus frequency is plotted in Figure 6. R p2 is the parallel resistance representing the losses of L 2 . It can be observed that I 2 n;out shows a minimum at the resonance frequency of the bandpass filter formed by L 2 and C p2 . At that frequency, Z S takes its maximum value, which means that the impedance Z out looking down from the drain of M 2 and equal to [1 + (g m2 + g mb2 )r o2 ]Z S + r o2 will also be maximized. According to the authors in [14,15], for single-ended Colpitts, the impedance (magnitude) seen at the source of M 1 should be maximum at the oscillation frequency of the oscillator topology. Thereby, in order to have the maximum value of Z out at the oscillation frequency, the resonance frequency f filter of the bandpass filter at the source of M 2 should be equal to the oscillation frequency.
In regard of the up-conversion of the flicker noise from M 1 and M 2 , it is reduced as follows. The inductive degeneration acts in a similar way to the noise filter, because at f filter , the nonlinear capacitance at the source node of M 2 is cancelled by L 2 . Thereby, the modulation of the current flowing through the nonlinear junction capacitance at the source node of M 2 and then through M 1 to the output is minimized.
At this stage, it is worth also comparing these results obtained from the Colpitts topology with the inductive degeneration with those obtained for the traditional Colpitts oscillator circuit topology of Figure 1, previously reported in [11]. In particular, from [11], the PN obtained under the same design conditions amounts to À96.25 dBc/Hz for an oscillation frequency of 10 GHz. Comparing this PN performance with the results obtained here and reported in Figure 5, we can observe that the Colpitts topology with inductive degeneration can lead potentially to a PN reduction up to 16 dB.
Last, the results presented in [10,11] show that the 1/f 3 region of the PN extends above a 1-MHz frequency offset for the Colpitts oscillator topology under study. This is a consequence of the adoption of nanoscale CMOS technologies characterized by flicker noise corners of several tens or hundreds of megahertz, which lead to flicker noise up-conversion being responsible for most of PN [38] even at large offsets from the carrier frequency. Thereby, the optimum inductance value for the total PN shown in Figure 5 is very close to that given by (39)-(41), because at a 1-MHz offset, thermal noise has a negligible effect on PN.

NOISE FILTER
In this section, we will derive the analytical expression for the oscillation frequency (f 0 ) of a Colpitts oscillator circuit topology in which we introduced a band-stop filter (L 3 , C 3 ) to the source node of M 1 as shown in Figure 7(a). Because of its noise filtering action, it is referred therein [14][15][16] as noise filter. Moreover, we will observe that there is an optimum inductance value (L 3 ) for which the oscillator circuit topology exhibits a minimum PN, and we will calculate such an optimum inductance that leads the noise filter to resonate at the oscillation frequency, as mentioned in Section 1. It is worth emphasizing that the circuit topology incorporating the noise filter, as in Figure 7(a), is different from the circuit topology with inductive degeneration, as in Figure 2(a). Thereby, despite the analyses reported in Section 1 and the analyses reported hereinafter share the Again, in order to extract appropriate evaluations about the improvement of PN performance with respect to the traditional topology of Figure 1, the oscillator circuit design will be carried out under the same transistor size, power and current consumption, and inductance of the tank and its quality factor, as in [10,11].

Oscillation frequency
The Colpitts oscillator circuit topology incorporating a noise filter is shown in Figure 7(a). Its smallsignal equivalent circuit is shown in Figure 7(b). This equivalent circuit is obtained by considering the simplified transistor model with the small-signal transconductance (g m ), gate-to-source capacitance (C gs ), gate-to-drain capacitance (C gd ), source-to-bulk capacitance (C sb ), and drain-tobulk capacitance (C db ). To reduce the complexity of the derived equations, the small-signal output resistance r o1 as well as the polysilicon gate resistance r g of M 1 are neglected. Later, we will verify that this hypothesis is acceptable. R p represents the total load resistance of the LC tank, including the effect of the finite Q of the tank and the resistance seen from the source of M 1 scaled by the capacitive divide factor.
The junction capacitances of transistors M 1 and M 2 in Figure 1 behave nonlinearly during the oscillation period. One of the major up-conversion mechanisms of flicker noise is the modulation of the current flowing through the capacitance at the source node of M 1 [38]. By removing M 2 , the modulation of the current flowing through this capacitance is significantly reduced, because of the decrease of the nonlinear parasitic capacitance. The presence of an optimum L 3 for minimum PN is due to the resonance with the capacitance at the source node of M 1 , which exhibits ideally high impedance at the resonance frequency of the noise filter. This results in further decrease of the modulation current, because this capacitance is effectively tuned out by L 3 .
C 3 can be varied in order to tune the oscillation frequency, avoiding changes in the tank capacitance. Moreover, the amplitude of the tank voltage can be larger than that in the topology of Figure 1, because there is no reduction of voltage headroom due to the tail transistor.
It is worth noting that because no varactor was used in the circuit of Figure 7(a), there are only two major up-conversion mechanisms: the modulation of the current flowing through the capacitance at the source node of M 1 and the modulation of the harmonic content of the output voltage waveform (i.e., Groszkowski effect). The adoption of the noise filter can minimize the first cause of flicker noise up-conversion [38].
C gs1 , C sb1 and C 3 appear in parallel with C 1 , and their sum can be expressed as an effective capacitance C p is the parasitic capacitance present at the drain node of M 1 , given by In order to excite the circuit into oscillation, we insert a current stimulus I in at the source of M 1 . From KCL at the source of M 1 , we obtain and also Solving (56) for I C1eff and using the result in (57), we find and from KCL at the output, Expressing (59) as a function of V gs1 and equating to (58), we can derive the closed-loop transfer function V out /I in as a ratio. By equating the real part of the denominator of this ratio to zero, we find that the oscillation frequency is given by Figure 8 shows the theoretical estimation of the oscillation frequency provided by (60)-(63), as a function of C 3 . Simulations are repeated for three different values of L 3 in order to show the dependence of f 0 on L 3 , which turns out being significant. Note that the oscillation frequency predicted by (60)-(63) closely follows the results obtained by circuit simulations. In particular, the maximum difference is about 70 MHz, observed for L 3 = 2 nH. Thereby, the aforementioned simplifications in the derivation of (60)-(63) are justified and lead to an accurate first-order prediction of the oscillation frequency f 0 .

Optimum inductance for minimum phase noise
Here, the objective is to explore the dependence of PN on L 3 and to derive the condition for which the PN at the output of the Colpitts oscillator circuit topology of Figure 7(a) can be reduced. The theoretical results will be compared with those obtained by means of SpectreRF simulations.
The large-signal equivalent circuit of the Colpitts oscillator of Figure 7(a) is shown in Figure 9. V in is a voltage stimulus applied to the gate of M 1 . Transistor M 1 is represented by a transconductance amplifier according to the describing function analysis [27]. G m1 is the large-signal transconductance of M 1 , equal to the ratio of the fundamental harmonic of the drain current of M 1 to the fundamental harmonic of the gate-source voltage of M 1 .
G m1 does not take into account the degeneration effect because of the non-ideal bias provided by L 3 . For this reason, first, we calculate the equivalent transconductance for the describing function model of Figure 9 with respect to the voltage stimulus V in , that is, G m,eq2 = I out /V in . Next, we will derive the condition on L 3 for which the flicker and thermal components of the PN at the output of the Colpitts oscillator circuit topology of Figure 7(a) can be minimized.
We can write Using (65) into (66) and rewriting Moreover, From KCL at the drain of M 1 , it derives Finally, replacing V GS1 and V x into (69) with their values given by (67) and (68), respectively, we find G m,eq2 as follows: By replacing G m1 in (28) with G m,eq2 given by (70), taking the derivative with respect to L 3 and equating to zero, we find that the value of L 3 for which the flicker component of the PN at the output of the Colpitts oscillator circuit topology of Figure 7(a) reaches the minimum is given by Figure 9. Large-signal equivalent circuit of the Colpitts oscillator circuit of Figure 7(a). G m1 is the largesignal transconductance of M 1 . V in is a voltage stimulus applied to the gate of M 1 .
A similar derivation can also be performed for the PN component because of the thermal noise of M 1 , L 3 , and the LC tank. The PN expression due to the thermal noise is Then we substitute G m1 in (48) with the expression of G m,eq2 given by (70) and use the calculated value of I B in (72). After taking the derivative with respect to L 3 and equate to zero, we find that the value of L 3 for which the thermal PN component at the output of the Colpitts oscillator circuit topology of Figure 7(a) reaches the minimum is given by The total PN is plotted in Figure 10 versus L 3 , at an average current of 6.3 mA, for an oscillation frequency of 10 GHz, at a 1-MHz frequency offset. C 1 and C 2 have equal size, and their value changes according to the value of L 3 , keeping f 0 constant at 10 GHz. C 3 is set equal to zero. Moreover, V B5 is chosen to have the same average current, also considering the voltage drop across the parasitic resistance of L 3 . Note the relatively good agreement between the theoretical derivations and the SpectreRF simulations. In detail, the maximum difference between the results of the theoretical predictions and circuit simulations is about 1 dB.
From SpectreRF simulations, the minimum PN is achieved for L 3 approximately equal to 8 nH. Thereby, this result confirms the discussion in [15], according to which the optimum inductance value in terms of PN is expected to be the value that tunes the resonance frequency of the noise filter (L 3 , C 3 ) to the oscillation frequency. This value of inductance can be obtained by means of integrated inductors.
At this stage, it is worth also comparing these results obtained from the Colpitts topology with noise filter of Figure 7(a) with those obtained for the traditional Colpitts oscillator circuit topology of  Figure 1, previously reported in [11]. In particular, from [11], the PN obtained under the same design conditions amounts to À96.25 dBc/Hz for an oscillation frequency of 10 GHz. Comparing such a PN performance with the results obtained here and reported in Figure 10, we can observe that the Colpitts oscillator circuit topology with noise filter can potentially allow a PN reduction up to 16 dB. Last, coherently with the fact that the 1/f 3 region of the PN extends beyond 1 MHz, as observed in [10,11], we can also observe that the optimum inductance value for the total PN shown in Figure 10 is very close to that given by (71), because at a 1-MHz offset, thermal noise has a negligible effect.

OPTIMUM CURRENT DENSITY
In this section, we will examine the technique of biasing an oscillator topology with the optimum current density for the minimum PN. The effectiveness of this technique for oscillators was shown in [19][20][21] where the transistors were biased close to the current density per unit of width for minimum noise figure. From the point of view of the PN analysis, an oscillator can be treated as a low-noise amplifier, needed to be noise matched to the signal source impedance, represented in this case by the tank impedance at the resonance frequency [18]. In low-noise amplifiers, the transistors should be biased with the optimum current density for minimum noise figure [17]. In oscillators, the quiescent point may vary significantly during the oscillation period, and thereby, the optimum current density for minimum PN may deviate from the dc bias current density for minimum noise figure of the transistors. Hence, in our analyses, we will consider the dc bias current (I B ) as the average total current. We will analyze and apply this third technique for further reduction of PN to the Colpitts oscillator topology incorporating either inductive degeneration or noise filter investigated earlier.
Combining the benefits of this third technique with those of inductive degeneration or noise filter could lead to maximize the potential reduction of PN achievable for the oscillator circuit topology under common design conditions. First, in our analysis, the PN components due to flicker and thermal noise will be expressed as a function of the bias current. Next, the resulting equations will be plotted versus the bias current density and validated by means of the results provided by SpectreRF simulations in Cadence.

Inductive degeneration
Combining (17), (42), and (43), we yield With reference to the Colpitts oscillator circuit topology with the inductive degeneration (L 2 ) at the source node of the tail current transistor (M 2 ) shown in Figure 2(a), we use G m1 given by (74) into (36)- (38) in order to express G m,eq1 in terms of I B . Then, for the flicker component of the PN, we use (28) where G m1 is substituted by the value of G m,eq1 calculated earlier. After taking the derivative of the resulting equation with respect to I B and equating to zero, we find where The thermal noise contribution to PN does not exhibit a minimum. By examining (45), it can be observed that the PN due to the thermal noise decreases for higher values of I B .
The total PN is given by (52) where the flicker and thermal components of the PN have been replaced by the new derivations. The total PN is plotted in Figure 11 versus the bias current density per unit of width I B /W and validated by means of the results provided by SpectreRF simulations in Cadence, for a 1-MHz frequency offset from the carrier. In order to demonstrate the dependence of PN on L 2 , the total PN is plotted for three different values of L 2 . The maximum difference amounts to about 7 dB, observed for L 2 = 1 nH. The tank capacitance is such that f 0 is held at 10 GHz, whereas C 1 and C 2 have equal value. V B3 in Figure 2(a) is connected to V DD , whereas V B4 has been swept from the value required to start up the oscillations to V DD .
At 10 GHz, both theory and simulations predict a current density of about 0.075 mA/μm for which PN reaches a minimum. This value is independent of L 2 according to SpectreRF simulation results. However, from simulations, it appears that beyond the local minimum and a certain bias current density, further increases may offer a further slight reduction in PN for inductances of 2 and 3 nH. Thereby, in this case, it may be worth investing additional bias current in order to achieve improved PN performance.
From Figure 11, we can calculate the difference in PN between the values obtained for the bias current of 6.3 mA considered in Section 2, corresponding to a bias current density of 0.21 mA/μm, and the optimum bias current density of 0.075 mA/μm. SpectreRF simulation results for 10 GHz show a reduction of PN of about 3 dB for L 2 equal to 1 nH and optimum bias current density of 0.075 mA/μm. By summing up the PN reduction provided by the inductive degeneration of 3 nH and optimum bias current density of 0.075 mA/μm, a potential overall reduction up to 14 dB can be achieved. Despite the current density of 0.075 mA/μm may lead to a better figure of merit, as mentioned earlier, it could be worth increasing the current consumption to 0.23 mA/μm in order to reach an overall potential reduction up to 16 dB. Figure 11. Total PN at a 1-MHz frequency offset from the carrier versus the bias current density I B /W for the circuit of Figure 2

Noise filter
With reference to the Colpitts oscillator circuit topology of Figure 7(a), where a noise filter (L 3 , C 3 ) has been introduced to the source node of M 1 , for the PN component contributed by flicker noise, we use G m1 given by (74) into (70) in order to express G m,eq2 in terms of I B .
The value of G m1 in (28) is then substituted by the value of G m,eq2 calculated before. After taking the derivative of the resulting equation with respect to the bias current I B and equate to zero, we obtain the following expression: where Again, the thermal noise contribution to PN does not exhibit a minimum. By examining (72), it can be observed that the PN due to the thermal noise decreases as I B increases.
The total PN is given by (52) where the flicker and thermal PN components have been replaced by the new derivations. It is plotted in Figure 12 versus the bias current density I B /W and validated by means of the results provided by SpectreRF simulations in Cadence, at a 1-MHz frequency offset from the carrier. In order to demonstrate the dependence of PN on L 3 , the total PN is plotted for three values of L 3 . The maximum difference is about 2 dB, observed for L 2 = 3 nH. C 1 and C 2 have equal size and are chosen to have f 0 equal to 10 GHz. C 3 is set equal to zero. V B5 has been swept from the value required to start up the oscillation to V DD . Figure 12 shows that for L 3 = 2 nH, both theory and simulations predict a bias current density of around 0.375 mA/μm for which PN is minimized. Moreover, we can calculate the difference of PN between the results obtained for the bias current of 6.3 mA adopted in Section 3, corresponding to a current density of 0.21 mA/μm, and the optimum current density. From SpectreRF simulations, for instance, a PN reduction of about 6 dB can be achieved for L 3 of 2 nH and a current density of 0.36 mA/μm.
Overall, by summing up the PN reduction provided by the Colpitts topology with the noise filter for 3 nH and optimum bias current density of about 0.31 mA/μm, a potential overall reduction up to 19 dB can be achieved with respect to À96.25 dBc/Hz of the traditional Colpitts topology [11]. Note that because of the very close PN performance, the case of 3 nH and 0.31 mA/μm lead to a lower current consumption and, thereby, potentially to a better figure of merit of the oscillator with respect to the case of 2 nH with a current density of 0.36 mA/μm.

CONCLUSIONS
The techniques of inductive degeneration and noise filter for the reduction of PN due to the tail transistor in CMOS LC oscillators have been applied for the first time to a single-ended Colpitts oscillator circuit topology. These techniques have been analyzed in detail by means of circuit theory and simulations. The analyses have allowed us to bring to the light a few interesting aspects not addressed yet in the literature.
In particular, an analytical expression of the oscillation frequency has been derived in order to allow an accurate prediction and show the dependence on the degeneration inductance and the noise filter components. In addition, an analytical expression of the PN has been derived in order to allow a good prediction and identify design opportunity for PN reduction in the previous techniques. The theoretical results, supported by circuit simulations, show that the PN of the Colpitts oscillator topology modified with the introduction of either the inductive degeneration or the noise filter reaches a minimum, leading to considerable potential benefits. In particular, there is an optimum degeneration inductance that resonates at the oscillation frequency with the parasitic capacitance at the source of the tail current transistor. In addition, for a given typical capacitance, there is an optimum inductance for which the noise filter resonates at the oscillation frequency. Last, it is possible to integrate a degeneration or noise filter inductor, in particular for an oscillation frequency of 10 GHz.
Moreover, a third technique for the PN reduction, namely, optimum current density, has been applied to the Colpitts topology with either the inductive degeneration or noise filter and analyzed in detail by means of circuit theory and simulations. It consists of biasing the oscillator circuit with the optimum current density for the minimum PN. The proposed analyses allow us for the first time to get an understanding of the theoretical details of this technique and its applications, identifying additional opportunities for the reduction of PN in the examined circuit topologies.
Overall, the analyses carried out for multiple degeneration inductances, noise filter inductances, and current density variations allow also some evaluations about the sensitivity of the respective PN reduction techniques.
The results of the analyses presented earlier show that, under the adopted common design conditions in a 28-nm CMOS technology, the previous techniques may potentially lead to PN reduction up to about 19 dB at a 1-MHz offset from an oscillation frequency of 10 GHz, with respect to the traditional Colpitts topology.

APPENDIX
The reference values of the circuit components used for the theoretical analyses and circuit simulations are reported in Table I. All the transistors have minimum length equal to 28 nm. In the adopted conditions, the transistors exhibit small-signal drain-to-source conductance g ds of about 2.7 mS and gate resistance r g of about 3 Ω.