A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.


INTRODUCTION
The rapid development of portable electronic devices using wireless data and video protocols has prompted the use of increasingly low-power mixed signal circuits, specifically analog-to-digital converters (ADCs). Given these specifications, pipelined ADCs are popular architectures for high-speed data conversion (10-100 MS/s) at medium to high resolution (8-14 bits). 1 They are employed in a variety of applications such as imaging or instrumentation systems. Within this architecture, the first few stages have the greatest impact on the performances of the ADC, the comparator being one of their fundamental building blocks because their speed determines the time margin for settling the signal in the amplifying phase of the ADC. Dynamic comparators are the preferred choice in these ADCs because they can tolerate a high offset error and their power consumption is very low. However, one of the most important disadvantages of these comparators is the noise sources, 2,3 particularly the distortion over the input signal because of the kickback effect, which limits in fact the resolution of the ADC. Kickback effect or kickback noise is caused by voltage variations in the regeneration nodes of the dynamic comparator 3 and the coupling of the digital input and output of the circuit to its analog input voltage. Moreover, the regeneration process provides a delay time between the digital input and output of the dynamic comparator. This regeneration time and propagation delay at the digital outputs is solved through digital latches that allow synchronization with the rest of the clock signals generated by the timing circuit. With respect to distortion, this is considered a nonlinearity effect known as kickback noise. In a pipelined ADC, this noise and, in general, the total noise power of a pipeline ADC with k stages, referred to its input, is given by where e 2 i is the noise power at the stage input and G i is the interstage gain of the ith stage. Because the noise contribution of the subsequent stages is attenuated by the interstage gains of the proceeding stages, the kickback noise is especially critical in the first stages of the pipelined ADC. Once the topology of the comparator has been tested for the first stage, this is integrated for the rest of the stages of the pipeline ADC. On the other hand, contrary to the noise power, the offset voltage V OS, Comp that can be allowed in the comparators depends exclusively on the topology of the stage and the reference voltage. This error is given by where B i is the digital output of the ith stage and r is the redundancy of the stage. This means that the smaller offset voltage would not improve the general performance of the pipelined ADC. Dynamic comparators disclose multiple advantages with respect to other typologies, meaning this does not require any extra preamplifier stage that would imply the addition of static power consumption. 3 Another advantage is that the dynamic comparator does not use additional capacitors, contrary to other publications. 4 Therefore, the use of reference capacitors is not necessary, thereby simplifying the circuit. In addition to the aforementioned ones, in the literature, there are recent proposals of dynamic comparator designed to reduce the kick back effect. In the works of Yongzhen et al 5 and Bahmanyar et al, 6 three stage comparators are used employing more than 20 transistors each, being the latter circuit able reduce the kickback noise from 7.6 mV to 5.9 mV. Also in the work of Ayesh et al, 7 a single-ended charge steering dynamic comparator, which offers a kickback noise of 3 mV is described. In other works, [8][9][10] other topologies of dynamic comparators are shown exhibiting different performance, although their kickback effect reduction is not quantified. In this short communication, a low kickback noise dynamic comparator is presented. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while, simultaneously, the offset voltage error is remained in the working range and the power consumption is extremely low. The rest of the paper is organized as follows: Section 2 describes the implementation of the dynamic comparator. The proposed architecture is simulated in Section 3. Section 4 presents the experimental results obtained from the implementation of the stages of an 11-bit pipelined ADC. Finally, conclusions are drawn up in Section 5.

CIRCUIT IMPLEMENTATION
Dynamic comparators are very efficient circuits from a power consumption perspective because they do not need static currents to work properly. 3 Moreover, some dynamic comparators allow the reduction of the global reference voltages that are needed for the analog amplification of a pipelined ADC because the trip points are internally fixed through the geometrical relationships. This topology reduces the total number of reference voltages, simplifies circuits such as bandgaps and analog buffers, and reduces the complexity of the physical layout. Figure 1A shows the structure of a conventional dynamic comparator. 11 The operation of this circuit is as follows. When the clock signal (CLK) is high, the transistors M5 and M8 are ON and the transistors M12 and M13 are OFF. This effect forces both differential outputs to VDDA. Consequently, M6 and M7 are OFF and M10 and M11 are ON. In this state, the dynamic comparator is not consuming energy and the transistors M1, M2, M3, and M4 are in the triode region fulfilling the role of these transistors as When the clock signal (CLK) goes down, the transistors M12 and M13 are turned ON and M5 and M8 are turned OFF. This means that at the end of this falling edge, the transistors M5, M6, M7, and M8 are cut off and the transistors M10, M11, M12, and M13 are ON. At this precise point, the outputs voltages will start to turn low or high depending on the polarization of the transistors M1, M2, M3, and M4 if the rest of the circuit is geometrically symmetrical. Therefore, considering that transistors M1, M2, M3, and M4 are in the triode region, if the conductance G M1−M2 formed by the transistors M1 and M2 is higher than the parallel conductance G M3−M4 formed by M3 and M4, then V + OUT will turn low faster than V − OUT and V + OUT will turn on the transistor M7 forcing the output V − OUT to high. Otherwise, if V − OUT turns low faster than V + OUT , then V + OUT will be forced to high. Given that once the comparison is made and the dynamic comparator reaches a stable state in the voltages output, there will be no static current flowing through the dynamic comparator. The delay between the clock signal and the digital outputs is caused by the regeneration time. This propagation delay is solved through digital latches that allow the synchronizing with the rest of the clock signals generated by the timing circuit of the pipeline ADC.
The digital output of the comparator is defined according to the resistance fixed by the input transistors, M1 to M4, connected to the inputs V + IN and V − IN , and the references V + R and V − R . Since the structure of the comparator is fully differential, the differential analog inputs are defined as The input transistors are designed with the following width restrictions: W 2 = W 4 and W 1 = W 3 , while all their lengths have the same value. To set up the trip points, the widths of the transistors connected to the analog inputs and the reference voltages are physically configured according to W 1 = k · W 2 . As a result, the trip point of the dynamic comparator is defined by The major drawback of this topology is that the offset voltage depends heavily on the process variations. Figures 1B and C show alternate topologies of dynamic comparators called, respectively, complementary input dynamic comparator (CIDC) 12 and low-offset dynamic comparator (LODC). 13 They have the advantage of being more robust structures with respect to the offset error. The reason is that CIDC can manage a higher input voltage dynamic range because of the extra pmos transistors M ′ 1 − M ′ 4 . On the other hand, LODC has a lower input dynamic range (2 Vpp), but this reduces the To reduce the coupling of the digital input and output of the circuit to the input analog voltage, thereby decreasing the kickback effect, the circuit proposed in this study (see Figure 2) includes two additional transistors, M12 and M14 to prevent this effect. When CLK goes high, these transistors disconnect the analog input from the cross-coupled latch. Moreover, to reduce the offset error, a third transistor, M13, is used to match the voltage at nodes C and D. So, when CLK goes down, the positive feedback mechanism is triggered as in a conventional dynamic comparator, but since nodes C and D are initially at the same voltage, the offset error is reduced. If this transistor was not used, the nodes C and D could have different voltages when CLK goes down and this would imply higher offset voltage. As a result of this modification, this topology presents lower kickback effect and offset error than the comparators found in the state of the art; consequently, this effect is less dependent on the process variation.

SIMULATIONS
Different simulations have been performed to evaluate both the kickback effect on input signal of the comparators as well as the voltage offset error. For the simulation of the kickback effect, the gates of the input transistors (M2 and M4) in the four topologies were connected through 50Ω resistors to V + IN and V − IN , respectively. V + R and V − R were connected directly to an ideal voltage source. For a fair comparison, the transistors were sized for k = 1∕1 and V R = 0V. This means that, according to (3), the theoretical trip point should be placed at 0V. Figure 3 shows the results obtained for a typical means condition for the four topologies.
The results show that when a comparison is made, a glitch is created over the input voltage of each dynamic comparator. The peak-to-peak voltage amplitude of each glitch allows the comparison of the kickback noise for each individual topology under test. The simulations of the four topologies show that the proposed circuit has the lowest kickback noise (287.9 V pp ) in an order of magnitude in comparison to CIDC, CD,C and LODC. These topologies had a kickback noise of 1342.1 V pp , 2309.4 V pp and 1567.5 V pp , respectively. On the other hand, CDC presents the higher kickback effect because of the direct coupling between the output and the input signals through the transistor M10 and M11. CIDC and LODC present similar performances when the kickback effect is evaluated. Figure 4 shows a transient simulation of the proposed comparator for four clock semicycles.
The simulation was done using a range that covers negative and positive input differential voltage values next to zero. The figure shows that the output of the comparator (V − OUT , V + OUT ) for the negative values is V − OUT = High and V + OUT = Low. Subsequently, when the values are positive, V − OUT = Low and V + OUT = High, being High = 3.3V and Low = 0V. This figure shows the strong coupling that exists between the nodes A and B with respect to the outputs of the dynamic comparator but this also shows that the distortion over the input signals is drastically minimized. Once the kickback effect was simulated for the four dynamic comparators, offset voltage was evaluated with respect to the technological process variation in order to reach a robust design. Figure 5    deviation of the offset error. This deviation varies from -400 mV to 400 mV making its implementation in the pipelined ADC critical. Moreover, another drawback of this topology is the high kickback effect shown in Figure 3A.
On the other hand, the comparator presented in this study has an offset voltage in the range of -250 mV to 200 mV. Although the obtained offset voltage is one order of magnitude higher than the measured for CIDC and LODC, this offset voltage allows the fulfillment of the specification for a maximum offset voltage of 375mV defined initially for the pipelined ADC. Diversely, from the point of view of the current specifications of the dynamic comparator and the pipelined ADC, a lower offset voltage in the comparator would not improve the effective resolution the ADC. In contrast, the current magnitude of the kickback effect over the input signals of the first stages of the pipelined ADC is an important source of distortion which seriously affects the signal-to-noise distortion ratio of the ADC.  Finally, Figure 6 shows the propagation delay obtained in the four topologies of dynamic comparators under study. The simulations of these circuits show that they have a similar propagation delay around 380ps. The obtained propagation delays for this work, CIDC, CDC, and LODC were 296.14ps, 462.94ps, 251.86ps, and 353.96ps, respectively. The propagation delay was measured with respect to the clock signal with a period of 25ns. The results shows that the delay propagation is two orders of magnitude smaller than the period of the clock signal. Moreover, another result of the simulation is that the CDC topology and this works present the minimum delay propagation while CIDC show the higher delay. It proves that the influence of the transistors M12 and M14 over the delay propagation is minimal. With respect to the power consumption, since there is no static current, the results show that the differences in power consumption of the topologies under study are negligible. The obtained power consumption for this work, CIDC, CDC, and LODC were 70.12 W, 76.82 W, 72.24 W, and 70.75 W, respectively. Table 1 shows the results, for the proposed comparator, of the eight corner conditions recommended by the AMS foundry. From this analysis, it can be concluded that the offset error of the proposed dynamic comparator does not depend on the corner conditions defined in Table 1. This means that the design is more affected by the process variations and the matching of the transistors than by the corner conditions defined in Table 1. Thus, the comparator shown in this work presents a good trade-off between kickback effect and offset voltage.   Figure 7 shows six full differential dynamic comparators and a digital encoder implemented as a low-resolution ADC. At the same time, this circuit is used for the implementation of the stages of an 11-bit pipelined ADC. Moreover, according to this low-resolution ADC, each stage has a resolution B i = 3 and a redundancy r = 1 and consequently, each stage has a resolution of 2.5 effective bits. The maximum offset voltage allowed in the comparators for such resolution and redundancy is less than ±375 mV. The low-resolution ADC requires configuration for the dynamic comparators with k = 1∕8, 3∕8 and 5∕8. The analog inputs are V + IN , V − IN , V + R , and V − R , the digital input is the clock signal CLK and the digital output are BIT0, BIT1 and BIT2. In this circuit, the most significant bit (MSB) is BIT0 while BIT2 is the least significant bit (LSB). Therefore, the expected digital outputs are shown in Table 2. This circuit has been synthesized using a 0.35 m CMOS AMS C35B4 process technology. Figure 8 shows the micrograph of the prototyped low-resolution ADC. The picture displays five of the six dynamic comparators. The area occupied by a single comparator is 38 × 34 m 2 while the whole area of the low-resolution ADC is 168 × 310 m 2 . Figure 9 shows the laboratory measurements obtained using a differential ramp input voltage with a frequency of 1.578MHz and a clock frequency of 60MHz. The input reference voltages were internally generated through bandgap circuits and analog buffers. The internal reference voltage V R was estimated through the real measurements and the lineal regression technique obtaining V R = 1.566V. Table 3 shows the theoretical trip point values, the estimated trip points using V R = 1.566V and the offset voltage obtained for each dynamic comparator. The measured results show that the dynamic comparators present an offset voltage lower than the maximum offset voltage of 375mV.

TABLE 3
Trip points and measured offset voltage in the low-resolution analog-to-digital converter for an internal reference voltage of V R = 1.566V

FIGURE 9
Real measurements for low-resolution analog-to-digital converter of 2.5 effective bit using a differential ramp input voltage with a frequency of 1.578MHz

CONCLUSIONS
In this paper, a fully differential dynamic comparator with low kickback noise has been described. The circuit exhibits a reduction of the kickback noise at least in one order of magnitude with respect to the other topologies under study and a propagation delay two orders of magnitude smaller than the period of the clock signal, comparable to that achieved by other comparator topologies. The proposed circuit has an offset voltage lower than ±375 mV. The circuit comprises a reduced number of transistors, which yields an extremely small silicon area for a 0.35-m CMOS process. Given that the kickback noise is one of the main factors that limit the resolution of the ADCs and according to the simulations and experimental results presented in this paper, the proposed circuit can be an optimal solution for the design of low power pipeline ADC converters with reduced kickback noise with stages which effective resolution is less than or equal to 2.5 bits. Moreover, due to the achieved noise reduction, this circuit can be used in other circuits where comparators with a preamplifier stage were required, contributing to a reduction of the power consumption in these circuits.