Temperature dependence of ESD effects on 28 nm FD‐SOI MOSFETs

The failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from −75 to 125°C are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28 nm fully depleted silicon‐on‐insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, potential, and so forth were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.


INTRODUCTION
2][3] ESD protection structures are commonly employed in the design of ESD protection for integrated circuits.However, in practical applications, ESD protection devices will be significantly affected by ambient temperatures when they are subjected to complex electrostatic environments during the manufacturing, packaging and transportation processes. 4,5Temperature fluctuations will cause deviations in the parameters of the ESD protection structures from their design windows, leading to greater complexity in ESD protection design. 6Moreover, as semiconductor technology advances, the feature sizes of microelectronic devices continue to shrink, resulting in thinner oxide layers and greater sensitivity to ESD effects. 7Liang et al. 8 investigated the impact of temperature on the ESD protection characteristics of various thyristors and diodes within the range of 300-500 K, they found that the holding voltage of all types of devices decreased as the temperature increased, while the relationship between the breakdown voltage and temperature varied depending on the trigger conditions of each device.Wang et al. 9 presented the variation characteristics of the holding voltage of 0.18 μm H-NMOS within the temperature range of 30-195 • C, and conducted a detailed analysis.Tazzoli et al. 10 proposed a high holding voltage SCR structure and investigated the temperature dependence of the device.They discovered that the self-heating effect caused by ESD pulse duration could lead to changes in the holding voltage.Nevertheless, the majority of these investigations focused on evaluating the temperature-dependent properties of conventional or novel ESD protective devices to ensure their dependability within operational temperature range, without delving into the detailed explanations of their failure mechanisms.
In this paper, simulations are performed in the −75 to 125 • C temperature range on a 28 nm Si FD-SOI NMOSFET at a given drain current pulsing.The HBM model was selected for simulation.First, the devices and simulation conditions are introduced.In the second part, the influence of transient injection current on the typical parameters of the devices as well as the failure mechanisms are investigated.The findings of this study will provide valuable reference for ESD design of the devices.

DEVICE STRUCTURE AND CONDITIONS OF SIMULATIONS
Owing to superior ability to provide physical insight into transient behavior and robust computing power, the Silvaco Technology Computer-Aided Design (TCAD) device simulator was employed to assess ESD effects.The Silvaco Atlas simulator was used to build an accurate three-dimensional (3D) structure model capable of defining grid information and doping concentration.Figure 1 depicts the cross-sectional view of the simulated devices, the length and width ratios are L G : W G = 36 nm:200 nm, and the channel length is 28 nm.During simulation, silicon was utilized as bulk and substrate material, while Aluminum was employed for the drain and source.The physical and technological parameters of the FD-SOI structure are presented in Table 1.
When an ESD effect occurs in a device, in addition to solving traditional semiconductor physics equations, the thermal and electrical equations need to be coupled for solution to accurately account for the impact of increased device temperatures.Furthermore, due to velocity overshoot effects, carrier diffusion, the relationship between carrier temperature and lattice temperature, the correlation between mobility and temperature, impact ionization rate and carrier energy F I G U R E 1 Cross-sectional view of a 28 nm FD-SOI MOSFET considered in this paper.distribution with lattice temperature under deep submicron technology, and so forth, traditional drift-diffusion models (DD) are no longer adequate for the entire numerical calculation.Consequently, an energy balance model (EBM) is used instead of the DD model to address these concerns.Moreover, Giga models are required to simulate the internal heat flow changes in the device due to non-isothermal simulation.Other physical models used in numerical device simulation include doping, temperature-dependent SRH model, Auger model and impact ionization model.The doping-dependent low-field mobility model and high-field saturation mobility model, as well as the temperature-dependent bandgap narrowing model are also considered.These physical models are detailed in the semiconductor device simulation tool.

TA B L E 1
The striking condition of ESD stress is HBM model.A 0.8 V DC voltage is applied to the gate and the source is grounded.A current pulse with a rise time of 5 ns, a fall time of 150 ns and a pulse amplitude of 0.1 mA is applied to the drain terminal.The temperature is various from −75 to 125 • C, the thermal conductivity is 1000 W/cm 2 K and the thermal contact is defined at the bottom of the device.

RESULTS
Figure 2A shows the injecting drain pulse current of a 28 nm FD-SOI MOSFETs as a function of time, and Figure 2B shows the ESD I-V curve obtained from TCAD simulation of the device at different temperatures, with an inset providing a detailed view of the ESD hysteresis curve.In order to facilitate the subsequent analysis, several special points on the curve are taken to analyze the electric field, carrier distribution, and temperature distribution of the device at the moments.
Moment "1" on the curve corresponds to the turn-on point of the parasitic transistor, moment "2" to the maintenance point and moment "4" to the second breakdown point.It can be seen from the figure that the ESD characteristics of the device are relatively sensitive to temperature.As the temperature gradually increases, the I-V curve moves towards the negative direction, and the first breakdown voltage (V T1 ) and holding voltage (V H ) gradually decrease.The transient response caused by the ESD effect can be divided into three distinct stages. 11As the incident excitation current increases, the device experiences an avalanche breakdown, resulting in the deposition of holes in the body region, which in turn triggers the activation of the parasitic BJT.At this point, the drain voltage of the device continues to rise until it reaches the first breakdown voltage.After that, the transient current flowing into the drain terminal is discharged to the source through the body region, thereby causing a decrease in the drain voltage of the device until it reaches the holding voltage.This phenomenon induces the hysteresis process as depicted in the Figure 2B.As the incident current further increases, the internal state of the device becomes exceedingly unstable, giving rise to the formation of hot spots.The temperature within these regions rapidly surges to the melting point of the semiconductor, causing permanent damage to the device.

The first breakdown voltage versus temperature
The extracted values of first breakdown voltage (V T1 ) for FD-SOI devices are shown in Figure 3.It can be seen that V T1 decreases gradually with increasing temperature from −75 to 125 • C, with a total decrease of about 1.12 V, which is about 27.32% lower than V T1 = 4.09 V at −75 • C. The V T1 of 28 nm FD-SOI device is the turn-on voltage of parasitic BJT.Avalanche breakdown occurs in the drain-body junction, producing a large number of electron-hole pairs through avalanche multiplication.The hole current flows into the body region and produces a voltage drop on the body resistance, which raises the body potential and makes the body-source junction forward-biased, leading to the turn-on of parasitic BJT in FD-SOI device.Throughout the entire process of temperature increase, the following mechanisms exist.
Firstly, when the temperature rises, the turn-on voltage V BS,on of parasitic BJT decreases.The temperature dependence of p-n junction forward bias voltage was studied by Khanna, 12 which can be expressed as follows: Where V is the forward bias voltage of p-n junction; T is the thermodynamic temperature; V thermal is the thermal voltage; E g is the bandgap width.From (1), it can be observed that at room temperature, the turn-on voltage decreases by 2 mV for every 1 K increase in temperature.At other temperatures, dV/dT remains negative, indicating that the forward bias voltage of the p-n junction decreases with increasing temperature.
Secondly, the impurities in the doped substrate are fully ionized at room temperature, intrinsic excitation inside the device is not significant, and carrier concentration hardly changes.As the temperature rises, lattice vibration scattering gradually becomes the main scattering mechanism for carriers.At this time, carrier mobility decreases with increasing F I G U R E 3 First breakdown voltage versus temperature.

F I G U R E 4
Total current density distribution versus temperature under same ESD current at moment "1".temperature, so the body resistance increases with temperature.Therefore, under the same body hole current conditions, the body potential also increases with temperature.
The total current density distribution inside the device at different temperatures during first breakdown is shown in Figure 4.It is observed that as the ambient temperature rises, the current density from the drain contact to the body region gradually decreases.With the same ESD current, the current density distribution decreases with increasing temperature, indirectly indicating that the body resistance R Body increases with temperature.Therefore, under the same ESD current pulse, the higher the temperature, the easier it is for parasitic BJT turn-on effect to occur, resulting in a higher first breakdown voltage.
Impact ionization occurs when the electric field across the drain-body junction exceeds the critical breakdown electric field after a current pulse is applied to the drain terminal.The carriers in the device are accelerated and a large number of secondary electron-hole pairs are generated, resulting in avalanche multiplication.The avalanche multiplication efficiency can be characterized by the collision ionization rate.As shown in Figure 5, the impact ionization rate inside the device decreases as the temperature increases, which is related to the electric field and the average free path of the carriers.

The holding voltage versus temperature
The plot in Figure 6 depicts the relationship between the holding voltage (V H ) and the ambient temperature extracted from the ESD I-V curve.It can be observed from the graph that the V H increases as the temperature descends.Specifically, as the temperature drops from 125 to −75 • C, V H increases from 2.59 to 2.81 V, which amounts to an 8.49% augmentation.V H represents the minimum clamping voltage that is required to sustain the parasitic BJT turn-on.The potential distribution under various temperatures is illustrated in Figure 7, from which it can be inferred that the V DB contributes the most to the total potential difference in V H .As the ambient temperature ascends from −75 to 125 • C, V DB gradually drops, with the temperature effect being most pronounced.
The potential distribution along Path is depicted in Figure 8, where the potential decreased by 0.85 V.As the temperature increases, R Body increases while V BS,on decreases.
This increase in temperature makes it easier to satisfy the condition for maintaining parasitic BJT turn-on (V body ≥ V BS,on ).Furthermore, the current gain  of the parasitic BJT also increases, leading to an increase in its current driving capability. 13

𝛽(T) = 𝛽 (T
Where T is the ambient temperature; (T) is the current gain of the parasitic BJT; T 0 =273 K; ℵ is the temperature coefficient.F I G U R E 9 Lattice temperature distribution versus temperature under same ESD current at moment "3".
In the equation, I CEO is the collector-emitter current when the base is open, I CBO is the collector-base current when the emitter is open,  0 is the current gain at 273 K, and ℵ is the temperature coefficient, with a typical value between 0.1 and 1 for silicon devices.
The rise in temperature influences the R Body , V BS,on , and , facilitating the sustenance of parasitic BJT turn-on and maintaining a specific level of current flow.Ultimately, leading to a decrease in V H .

3.3
The lattice temperature versus temperature The temperature-dependent variations in the internal lattice temperature of the device are extracted as shown in Figure 9.
It is evident that, at different temperatures, the internal hotspots of the device are located beneath the gate after ESD current striking, and the lattice temperature gradually increases with the operating temperature.

F I G U R E 10
The maximum lattice temperature versus ambient temperature.
The relationship between the maximum lattice temperature of the device and the operating temperature is shown in Figure 10.The maximum lattice temperature increases from 249 to 475 K.This phenomenon can be attributed to the internal collision ionization of the device, which intensifies with rising temperature, causing a concomitant rise in the lattice temperature.Despite the highest internal hotspot temperature of the device failing to reach the melting temperature (1685 K) of the semiconductor across the four different temperature ranges, and no permanent damage to the device is found.Nonetheless, significant deviations in the ESD characteristic parameters are anticipated.

CONCLUSION
The TCAD simulations conducted on ESD effects reveal that an escalation in temperature results in a reduction of the obtained V H and V T1 , as well as an increase in the maximum lattice temperature, for a 28 nm Si FD-SOI MOSFET subjected to a given ESD current pulsing.Notably, a temperature increases from −75 to 125 • C induces a substantial 27.32% decrease in V T1 and an 8.49% decrease in V H , indicating a strong dependence of ESD stress on temperature.The variations in electrical parameters may stem from drops in V BS,on and increases in R Body ,  as temperature increases.Nevertheless, the maximum lattice temperature failing to reach the melting temperature of semiconductor under this study.These results provide a valuable point of reference for the ESD design window design margin and high temperature reliability evaluation of similar devices.

2
The characteristic curve of the device.(A) The injecting drain pulse current of the device as a function of time; (B)ESD I-V curves of FD-SOI MOSFET from −75 to 125 • C. Inset: detailed ESD hysteresis curves.

F I G U R E 5
Impact ionization distribution versus temperature under same ESD current at moment "1".F I G U R E 6 Holding voltage versus temperature.F I G U R E 7 Potential distribution versus temperature under same ESD current pulsing at moment "2".

F I G U R E 8
Potential distributions in the source to drain surface along path under various ambient temperatures with same ESD current pulsing at moment "2".
Device parameters used for the simulations.