A novel receiver design for energy packet-based dispatching

A steadily growing share of renewable energies with uctuating and decentralized generation as well as rising peak loads require novel solutions to ensure the reliability of electricity supply. More speci cally, grid stability is endangered by equally relevant line constraints and battery capacity limits. In this light, energy packet-based dispatching with power signal dual modulation has recently been introduced as an innovative solution. However, this approach assumes a central synchronicity provision unit for energy packet dispatching. In order to overcome this assumption, the present paper's main contribution is a design of an energy packet receiver which recovers the required synchronicity information directly from the received signal itself. Key implementation aspects are discussed in detail. By means of a DC grid example, simulation results show the performance and applicability of the proposed novel receiver for packet-based energy dispatching.


Introduction
Today's electricity grid is based on the equilibrium principle, i.e. the amount of power generated corresponds to the power consumed at every instant of time. Due to the steadily growing number of renewable energies with fluctuating and decentralized generation as well as increasing peak loads due to the rising use of electric vehicles and heat pumps in the context of the energy transition, it is increasingly challenging to guarantee this instantaneous balance while considering local constraints. Demand Response (DR), Demand Side Management (DSM) and Energy Management Systems (EMS) can be considered as potential solutions to this challenge, at least in the short term [1] [2] [3]. Unfortunately, the possibilities for load shifting in today's power grids are limited due to equally relevant line constraints and battery capacity limits. For a long-term solution, it is therefore necessary to consider completely new concepts, which operate without overall synchronicity between generation and consumption.
A packet-based energy distribution concept, as presented e.g. in [4] and [5], can be one of such long-term solutions. According to the number of recent publications e.g. [6], [7] and [8], such a packet-based energy distribution approach is highly topical and widely accepted. Inspired by the Internet protocol (IP) known from modern communication technologies, an asynchronous energy distribution is a promising option to solve the problem described above and to make the entire power distribution network future-proof. Equivalent to the data packet from the Internet protocol, an energy packet (EP) is defined as the key element in this concept. An energy packet itself is a defined amount of energy that is exchanged within the distribution network between source and sink asynchronously according to demand or availability. In combination with energy storage elements, this approach enables energy transmission based on the store-and-forward principle known from the IP protocol. The two characteristics of this concept, namely the energy packet definition and the store-and-forward principle, result in two major advantages which contribute significantly to the improvement of the energy supply infrastructure: (i) creating a clear decoupling between demand and generation; (ii) always allowing the best use of the infrastructure capacity, i.e. line limits and storage capacity.
While in [4] the vision and the underlying theoretical considerations are presented in detail, in [5] a possible solution for the realization of energy packets and their transmission via a direct current (DC) 2 Packet-based energy distribution in DC networks 2.1 Concept Figure 1 visualizes the concept of packet-based energy distribution in a simplified form. Each participant of this simple energy distribution network is connected to a DC bus either via DC/DC (see G1, L1 and L3) or DC/AC converters (see L2). The generator G1 supplies the DC bus with a constant DC voltage V G1 . Communication paths are represented by transceiver blocks Tx/Rx. All loads are in standby at initial time t 0 , i.e. the respective input impedance of the converters is very high and no current flows. At time t 1 , an energy packet is transmitted to the load L 3 . For this purpose, the load L 3 is informed via a communication path that it should switch to the current consumption mode for the duration T L3 . For the duration T L3 a current I L3 flows. This process could be interpreted as an energy packet transmission procedure: Obviously, the same principles apply to the transmission of EP L2 at t 2 and EP L1 at t 3 . Taking the concept shown in Figure 1 as a basis, it becomes clear that an energy packet is a combination of the energy Europe to a very high degree, thus immensely limiting the achievable transmission rates. The European standard (EN) defines the in-band and out-of-band emission limits and states that the CENELEC A band (3-95 kHz) is reserved for energy suppliers and that only the CENELEC B-D bands (95-148.5 kHz) may be used by consumer installations [21]. Due to these restrictions, conventional NB-PLC technology operates in Europe exactly within a frequency band where the power electronics required for generating the energy packets have the maximum disturbance emission, and consequently, communication is vulnerable to the switching frequency noise.

Power Signal Dual Modulation based Powerline Communication for Energy Packet distribution
To overcome this problem, powerline communication based on Power-Signal-Dual-Modulation (PSDM) was proposed in the articles [22], [23], [24] and [5]. With PSDM, the information signal is embedded into the power signal by manipulating the pulse width modulation signal of the power converter. Either the phase or the frequency of the PWM signal can be manipulated to inject the information. In this way, both data modulation and power conversion are implemented in a single electronic circuit and no explicit analog front ends or coupling units are required like in conventional PLC transmitters. This simplifies the system structure and minimizes implementation costs. The paper [5], on which the present contribution is based on, describes exactly how energy packets can be generated and transmitted using PSDM technology. However, the paper does not answer how the synchronization required for processing the information part of an energy packet can be achieved. Other publications dealing with PSDM also do not give a satisfactory answer to the problem of synchronization in the receiver. For example, the theoretical demodulation process of a DBPSK is described in the [25] and it is also pointed out that the symbol clock is crucial for the demodulation of the data, but at the same time it is written: "Still, bit-synchronization is required, which can be easily achieved by program". However, as described in section 4 bit-synchronization or more precisely symbol-clock recovery is not an easy procedure at all, and is essential for processing and interpreting the received information. In [23] a PSK/DSSS modulated signal with suppressed carrier is coherently demodulated. The authors noted that accurate information about the frequency and phase of the carrier is necessary to demodulate the data. To obtain this information, they propose to transform the received PSK/DSSS signal simply into the frequency domain without any pre-operation. However, a non-linear operation has to be applied to a suppressed carrier information signal first to obtain a clear spectral line of the carrier, as can be found in [26] or [27].
Furthermore, another essential component of a receiving unit, the Adaptive Gain Control, has been completely disregarded in all cited articles, whereby in all of them the interpretation of the data depends on a normalized level.
Hence, the present contribution discusses possible solutions for synchronization and level stabilization in the information path in the context of packet-based energy distribution based on PSDM.

PSDM Transmitter for Energy Packet generation
To provide an input signal for the implemented receiver, a power signal dual modulation based generator for energy packets as proposed in [5] is realized. Figure 2 shows the structure of this generator. As the name implies, the generator performs two tasks: First, it acts as a buck converter, which supplies the DC bus with a constant DC voltage and the energy during the energy packet transmission phase. At the same time, it also acts as an analog part of a powerline transmitter by injecting the information signal into the power line without additional circuits such as an analog front end or coupler. In the following simulation, the output signal of this generator serves as input signal for the realized receiver.
As shown in Figure 2, the information signal is embedded into the power signal by manipulating the duty cycle of the PWM signal used to control the power transistors. The theoretical basics of this procedure are explained in detail in [5] or [23]. The transmitter responsible for generating the modulated PWM carrier is based on the Direct Sequence Spread Spectrum (DSSS) technology. For this purpose, the data to be transmitted are first DBPSK-coded, then spreaded with an orthogonal pseudo-random sequence based on the Walsh-Hadamard matrix and finally modulated onto the PWM carrier. The use of DSSS transmission technology makes it possible to secure the data connection against the pulse interference and multi-path propagation strongly represented within the power line and thus to design the control path reliably [28] [29]. It also ensures a certain level of security, since only the load that knows the corresponding despreading sequence can decode the data. Figure 3 shows the implemented powerline communication receiver. In principle, every receiver and also the implemented powerline communication receiver is a transmitter backwards that contains some additional elements, especially several indispensable synchronization units. These are necessary because the receiver generally has no precise information about the symbol, i.e. chip clock, frequency and phase of the carrier and the start point of the data packet. Furthermore, the receiver has to derive this information from the received signal itself. In addition, the clock elements in both the transmitter and receiver have a certain temperature drift, manufacturing tolerances, ageing phenomena, which cause a variable time offset [30].

Receiver for the information part of Energy Packets
The resulting time errors have an influence on the signal level within the digital signal processing and can significantly influence the reception quality or even make data transmission impossible [27]. Therefore, the receiver has to perform at least the following synchronization tasks for a successful data transfer [27] [31] [26]: In general, two additional synchronization stages are required for direct spread spectrum systems: • Code acquisition • Code tracking However, these are only indispensable if one has to deal with strong frequency-selective interference or if one wants to implement a system with code multiplexing media access. However, since we primarily use  spread spectrum technique to assign the messages to the respective load and our intention is to show that the synchronization approaches presented afterwards can also be used for power/signal dual modulation, we can skip with these two synchronization stages in the first step. This is possible because a DBPSK/DSSS signal can be treated for synchronization purposes as a pure DBPSK signal with a data rate increased by the spreading factor. Furthermore, the synchronization approaches described in the following are so generically implemented that they can be modified to a strict DSSS solution with a manageable effort. Among the required adjustments are the replacement of the Timing-Error Detector (TED) by a code phase error detector, the addition of a code acquisition unit and the calculation of the carrier phase error using the despread symbols and not the baseband signal. Thus, the solutions shown in this paper can be considered as the basis for further synchronization steps.
Next, the realized synchronization levels 4.1. Adaptive Gain Control -4.5. Frame Synchronisation are explained in detail. The corresponding simulation results follow in Section 5. The description of the general elements of the receiver, such as matched filter, demodulation unit, etc., which form the counterpart to the transmitter, is omitted, but reference is made to further literature where these elements are described in detail [26] [27] [32].

Adaptive Gain Control
Phase Locked Loop (PLL) based synchronization algorithms require a constant average signal energy, since this influences the K p factor of the Phase Error Detector or Timing Error Detector [32]. The level of the threshold value for frame synchronization also depends on the average signal energy of the incoming signal [33]. Thus, a constant signal level is a critical parameter for the realization of a digital transmission system. This is ensured by the Adaptive Gain Control (AGC) unit.
As shown in Figure 3, the signal level correction via AGC takes place in the baseband, i.e. after the down-conversion of the input signal, but before any synchronization. At this point the signal can be described by: where u(k) represents the input signal, A(k) the amplitude of the symbol and φ r (k) the phase of received symbols. Due to the variable distance between the transmitter and receiver, the used transmission power as well as different attenuation influences within the channel, the amplitude A(k) of the signal is variable and even time-variant. In order to compensate this variance and to adjust the signal level to the reference level, the AGC unit is used. Following difference equations describe the implemented Least Mean Squares (LMS) signal level adaptation algorithm: where • u(k) represents the complex input signal • R represents the reference signal level • α represents the step size • x(k) represents the divide by factor • y(k) represents the output signal of the AGC To ensure a constant signal level, the magnitude of the AGC output signal y is compared with a reference signal level R. If the output signal level is too high (low), a negative (positive) signal is fed back, reducing (increasing) the gain. The control parameter α regulates the amplitude of the feedback signal and is used to control the AGC's time constant.
Corresponding to Eqn. (3) the calculation of the absolute value of the complex input signal |u(k)| for determining the amplitude of the input signal is a non-linear process, so the resulting equation is also non-linear. However, based on the assumption that the system is driven by a step u(k) = c k with c k > 0, the non-linear equation becomes a linear difference equation: From this solution follows that in steady state the gain is x(k) = R c and the system time constant is τ = 1 αc .

Carrier synchronization
A phase deviation of the local oscillator of the down-converter from the carrier wave regardless of whether time-variant or not causes an offset (if time-invariant) or rotation (if time-variant) of the received symbols in the symbol domain [31]. Figure 4 shows an example of such a time-variant deviation of the received symbols (blue) from the expected symbols (red). At the shown snapshot the phase shift of the symbols is approx. 45°. If the offset is large enough -in the case of the BPSK more as ±90°-a wrong symbol will be detected. The task of carrier synchronization is to keep this phase offset as low as possible. In principle, carrier synchronization is a process of tracking the frequency or phase of the local oscillator to the frequency and phase of the carrier wave. This can be undertaken in different ways [27] [31] [32]. To avoid the need for additional frequency offset estimation and to keep the complexity of the receiver as low as possible, a PLLbased decision-feedback carrier synchronizer is implemented. This has the advantage that it can correct both phase and frequency offset at least within a limited range. As shown in Figure 5, the implemented carrier synchronization unit consists of a carrier phase error detector (PED), a loop filter F(z), a phase error accumulator as well as a phase rotator.
The carrier phase error detector determines the phase error between the carrier wave and the local oscillator. The loop filter removes the unwanted high-frequency signal components and generates the corresponding control signal for the phase error accumulator. The phase error accumulator is responsible for determining an accumulating phase error. The phase rotator eliminates the estimated phase error.
Since the functionality of the used Proportional-Integral loop filter and phase error accumulator is known from discrete PLLs, only the principle of the used carrier synchronization and the functionality of the implemented carrier phase error detector are presented in the following. For the general functionality of the loop filter and phase error accumulator please refer to the further literature [32] [34].
The received signal can be described by: where the representations are • G a gains and losses of the signal • i(k) k-th chip • p(t) unity-energy pulse shape • ϕ e unknown combined phase offset • T s sample period • ω 0 t angular frequency of carrier wave • w(t) addative white Gaussian noise Without loss of generality and for simplicity, only the part of the overall function that is relevant for carrier synchronization is used in the following: The combined phase shift φ e = Δωt + Δφ consists of a possible frequency shift Δω and a constant phase shift Δφ between the carrier wave and the local oscillator. To eliminate φ e , an asynchronous shift of the passband signal into the baseband is first performed by means of the down-converter using a complex signal s(k) = 2e -jΩ 0 k , cf. Figure 3: The double-frequency components resulting from the multiplication are then eliminated by the matched filter and the following relation is obtained: This means that the symbols x(k) of a signal mixed down asynchronously are shifted in the symbol domain by phase offset φ e from the nominal position φ d of the symbols as shown in Figure 4. The phase error increment that occurs during a single chip interval is calculated in the implemented Phase Error Detector as follows: Angle of the received symbol: Angle of the nearest possible symbol : Resulting phase error: The resulting correction phase is then formed using the phase error accumulator by integrating the phase error; subsequently the phase rotator eliminates the offset. Figure 6 shows the S-Curve of the Phase Error Detector. Observe that the S-Curve has two stable locking points at φ e = 0 and φ e = ±π. Therefore, a phase ambiguity of π exists. This disadvantage is eliminated by difference coding in the transmitter. As mentioned in section 3.

Timing recovery
The output of the matched filter must be sampled periodically at the corresponding chip 2 rate f c at time t k = kT c +τ, where T c describes the chip period and τ the time delay due to the signal propagation between the transmitter and the receiver. Since τ is generally unknown and T c in the transmitter and receiver are not completely identical, e.g. due to production tolerances of the clocking elements or thermal variance [30], the optimum sampling point is generally unknown. Not sampling the output of the matched filter at this optimum sampling point t k and with the locally generated asynchronous sampling frequency f c results  in periodic degradation of the signal level, leading either to a wrong symbol decision or to temporary full signal loss [27] [31], cf. Figure 16 in Section 5.
The task of the Clock Recovery Unit is to find this optimal sampling point, i.e. to synchronize the receiver with the received signal. Note that since both the installation of a separate clock line between all devices and the reduction of the available signal power (respectively transmission bandwidth) in favor of an explicit clock signal are not viable options, the symbol clock must be derived from the received data. This can be executed both in the time-continuous domain and in the time-discrete domain [32]. In the presented article, a time-discrete solution first introduced by Lars Erup and Floyd M. Gardner is implemented [35] [36]. Figure 7 shows the block diagram of the implemented clock synchronization unit. This consists of a 3rd order Fractional Delay Filter, a Gardner Timing-Error Detector, a loop filter and a Timing Control Unit.
In the first step, the received continuous signal is oversampled discretized with a fixed asynchronous local frequency f s = 1 /T. Then, with the aid of the down-converter, it is mixed down into the baseband area and fed to the matched filter. After signal level correction in the AGC unit and carrier synchronization, the signal can be described as follows: Thereby i(n) describes the n-th chip, T the sampling period, T c the chip duration and r p (u) is the auto-correlation function of the pulse shape and τ the unknown timing delay. The goal of the Timing Recovery Unit is to eliminate τ, i.e. each resulting sample is aligned with the maximum eye opening. This can be achieved by shifting the asynchronous signal by means of fractional delay interpolation, so that after interpolation the data looks as if it had been sampled at the optimal sampling point. To accomplish this, first the timing error e(n) = f(τ) is determined in the Timing Error Detector. Then e(n) is fed to the loop filter to determine the corresponding phase and frequency error of local chip clock. Subsequently, the Timing Control Unit generates a fractional delay Δ from the loop filter output signal. This fractional delay Δ is required to correct the estimated timing offset τ = -τ by sample value correction via interpolation in the interpolator. At the same time, the Timing Control Unit calculates the optimum sampling time in the maximum amplitude of the symbol, i.e. it adjust the local chip clock.

Interpolation unit
As mentioned above, the fraction delay filter is used to compute desired samples of y(nT c ) at the optimum sampling instances from the available sample x(kT). To ensure a linear-phase transmission behaviour of the filter, an odd-order polynomial is chosen. However, due to the fact that interpolation with a 1st degree polynomial leads to large deviations, the next option of a 3rd degree polynomial is used. The resulting algorithm for calculating the desired interpolation value is: where p represents the order of the used interpolation polynomial, Δ the fractional delay of the Timing Control Unit and b l (i) the corresponding filter coefficient, Table 1.
These filter coefficients are obtained by determining the polynomial coefficients of the 3rd degree interpolation polynomial: as a function of Δ, taking into account the four given samples, which are arranged in pairs to the left and right of the value to be interpolated, cf. Figure 8. x(n-1) x(n) x(n+1) y(kT c ) n-2 n-1 n n+1

Figure 8: Interpolation principle
A detailed description of the calculation of the filter coefficient as well as a deeper description of the functionality of the Timing Control Unit is omitted and reference is made to the corresponding sources [32] [36] [35].

Timing Error Detector
Implemented TED use the Gardner algorithm to determine one timing error value e(n) per chip. The algorithm is based on a delay difference between the current sample and another sample of the same symbol delayed by half the symbol period and and requires 2 samples per chip. To determine the timing error, 3 consecutive samples are used which are shifted by half a chip to each other. The error signal is finally obtained according to the following equation [37]: Where y(nT c ) are generally complex values. If the sampling is performed at the optimum time point, two values are located in the chip center and one exactly at the transition between two chips, e(n) = 0. If sampling is premature, then e(n) < 0, if sampling is delayed, then e(n) > 0. The advantage of this algorithm is the insensitivity to a carrier frequency offset, thus no previous carrier synchronization is required.

Timing Control Unit
The Timing control unit provides the interpolator with the fractional interval Δ and the TED with the strobe signal CLK to calculate the correct timing errors once per chip. The interpolation is performed for every sample, and a strobe signal is used to determine if the interpolant is taken as output value. The operation principle of the timing controller is based on the Modulo-1 decrements counter. The counting frequency is determined by the constant 1 /N, where N is the number of samples per chip. The output of the Modulo-1 counter is defined as: with and where ν(n) corresponds the loop filter output and δ(k) corresponds each sample calculated Δ. The ν(n) signal from the loop filter adjusts the amount by which the counter decrements and δ(k) is only passed to the interpolation filter as Δ if the strobe signal is valid.

Loop-Filter
For both carrier and clock synchronization, a time discrete Proportional-Integral (PI) filter is used to calculate the control variable for the frequency and phase offset. The filter is a 1st order filter with the following transfer function in the z-domain [38]: The gain parameters C 1 and C 2 define the behavior of the closed loop and are calculated as follows: ζ is the loop attenuation coefficient, K 0 the numerically-controlled oscillator (NCO) gain, K D the error detector gain, T c the chip interval and ω n natural frequency. Values from Table 2 are used for the carrier synchronization loop respectively timing recovery loop. The NCO Gain K 0 correspond to the gradient of characteristic curve of the respective NCO. The Error Detector Gain K D can be taken from the respective S-curve of Error Detector [32].

Frame Synchronisation
After successful carrier synchronization and timing recovery, the next step is to locate a structure in the chip stream within which the valid data is located.
For the reliable detection of a frame start within the chip stream, a 78-chip synchronization word is used, which consists of a 64-chip long code word and a 14-chip long guard interval. The code words are with The selected codewords (H 8,3 , H 8,5 ) have very good aperiodic autocorrelation properties. This ensures a sufficient distance between the maxima of frame start detection and the side lobes.
The detection of the synchronization pattern is performed by a correlator realized in FIR filter structure, which cross-correlates the local version of the synchronization pattern with the incoming baseband symbol stream. The amount of the cross-correlation is then squared. By applying a non-linear function, the distance between the main maxima and the possible sidelobes is further increased. This enables reliable detection even with a very low SNR. If the set threshold value is exceeded, a preamble is detected and valid data follows. The data can then be despreaded and demodulated. The block diagram of the frame synchronization unit is shown in Figure 9.

Despreading and demodulation
After synchronizing all three levels, the received data must now be despreaded and demodulated. After clock synchronization, chip stream to be treated is now available as chip/sample. The code phase position required for successful despreading of the data is also known due to the detection of the start of frames in the frame synchronization. Now the data is fed to a despreading unit in FIR filter structure. This delivers all L (length of code word) chips the despreaded symbol, which is converted into a data bit in the DBPSK demodulation unit. The resulting data bit stream is then stored in a queue register.
5 Simulation results Figure 10 shows the structure of the DC grid which was used for the simulative performance analysis of the implemented transmission system. It is a low voltage direct current circuit consisting of two generator converters (G1 and G2) and three consumer converters (L1-L3). Both the converters on the generator side and on the load side are synchronous DC-DC buck converters. This structure is based on the structure LG2 for testing the power/signal dual modulation (PSDM) Techniques for packet based energy dispatching from [5]. This modified simulation example for the power/signal dual modulation technique, which in contrast to the original version is equipped with the transmission system developed in the present article, is intended to show that the information exchange between generator and load required for the exchange of the energy packets does not require a third-party synchronization unit. Furthermore, all parameters required for successful information and energy exchange can be derived from the received signal itself. Figure 11 (a) shows the output signal of the generator (G1). It supplies the DC bus with 15V DC voltage. In the context of power/signal dual modulation, the existing residual ripple of the DC voltage no longer represents only the unwanted noise; it is used constructively for information transmission. The messages sent by G1 for testing are coded alternately with the unique sequence S1 for load L1 and S2 for load L2. This DC voltage superimposed with the information signal is available as a broadcast signal to all devices connected to the bus.
At the beginning of this simulation example t = 0s, the three loads are operated in listening mode. Simultaneously, L1 and L2 are configured as high-impedance (I L1 = I L2 = 0) and L3 is operated with a constant nominal current of (I L3 = 4A), cf. Figure 11 (d), (g) and (h). As seen from the correlation peaks in Figure 11 (b) L1 detects at time t = 35 ms and t = 185 ms data addressed to him within the received data stream. After the synchronization, decoding and demodulation processes described in section 4 have been performed, the receiver signals the presence of valid data by setting the signal "Valid data avaible" to high Figure 11 (c) and passes the data to the control unit of load L1 for further processing. After elimination of the metadata by receiver, the data contains the control information regarding the amount of load current required and how long this should be present. This data is interpreted in the control unit and then the current flow enable signal is activated for the required time Figure 11 (c) and the required current level is set for 35 ms. A similar process occurs at time t=110ms for load L2, see Figure 11 (e), (f) and (g). The resulting total current is shown in subplot (i). In the following subsections the results of the realized synchronization level are presented. These enable the asynchronous transmission of energy packets via PSDM and derivation of metadata from the received data.
In order to test the AGC of the implemented receiver, the information part (i.e. high-frequency part) of the broadcast signal undergoes time-variable random amplification (G = 0.5 -1.25). The change period is 175ms. Figure 12 summarizes the simulation results of the Adaptive Gain Control tests. Subplot (a) shows the received signal in the passband, which varies randomly every 175ms. In subplot (b) the corresponding baseband signal before the AGC is shown, which changes in the same way. In subplot (c) the gain factor is shown which is applied to keep the output signal constant according to the reference. Finally, the subplot (d) shows the nearly constant baseband signal after the AGC.  Next, the results of the phase and frequency offset correction are presented using the carrier synchronization unit. Figure 13 shows the correction process of a phase offset between the carrier wave and the phase of the local oscillator of π 6 . Subplot (a) shows the asynchronously downconverted baseband signal. Due to the phase shift, part of the signal power is transferred to the imaginary part (red). Subplot (b) shows the output of the phase error detector. Subplot (c) shows the resulting correction value φ and subplot (d) the baseband signal after phase offset correction.
The carrier synchronization results at a frequency offset are shown in Figure 14. The frequency offset that is used is Δf = 5Hz.
The results of Chip Clock Recovery are summarized below. The sampling frequency offset of Δf = 2Hz is used to test the Timing Recovery Unit. Subplot (a) of Figure 15 shows the bassisband signal of the received signal r(t) sampled without the local clock recovery. As one can see, plot (a) contains samples that should not be present in a DBPSK signal. These result from an asynchronous sampling. In the subplot (b) the same signal is shown but after the chip clock recovery. The constellation diagrams, Figure 16, further clarify the asynchronicity between the received data and the local clock as well as the result of the synchronisation by the clock recovery unit. Figure 17 shows the corresponding estimated timing error and the resulting fractional delay for timing error correction.
Finally, as described in Section 4 , the frame synchronization, the despreading of the chips to the DBPSK symbols and finally the demodulation of the data is performed. The results of these operations for two received data frames is shown in Figure 18. Subplot (a) shows the received chipstream. The result of the cross correlation for the preamble detection is shown in the subplot (b). Subplot (c) shows the valid-frame-detected signal and subplot (d) shows the corresponding DBPSK symbols.
In contrast, Figure 19 shows the same procedure but for the 2nd load. Since this load expects data coded with L2 unique sequence, no valid message is detected, which can be seen from the result of the cross correlation.
A series of ten information frames are sent to check the overall functionality of the implemented receiver. The received binary data are then cross-correlated with the transmitted data. The result of the crosscorrelation is shown in Figure 20. A complete match of the transmitted and the received data can be recognized by the unique peak at τ = 0.

Conclusion and Outlook
The present paper extends previous contributions [4,5] regarding packet-based energy transmission by describing a practicable design of an energy packet receiver which recovers the required synchronicity information directly from the received signal itself. The main focus is on the reception and lossless preprocessing and interpretation of the metadata of the information part of the energy packet. For this purpose, implemented solutions for the respective synchronization levels (i) Carrier Recovery, (ii) Clock Recovery and (iii) Frame Recovery are discussed in detail. Drawing upon a DC grid example, simulation results show the performance and applicability of the proposed novel receiver for packet based energy dispatching.
As future work, the proposed approach of packet-based energy distribution will be implemented and validated within the KIT Energy Lab 2.0 infrastructure [39].