Single‐layer thin‐film transistor analysis and design

A set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short‐base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.


| INTRODUCTION
Three levels of semiconductor device modeling are common, involving the use of (i) analytical mathematical relationships in conjunction with lumped parameter equivalent circuits, (ii) circuit simulation using tools such as a simulation program with integrated circuit emphasis (SPICE), or (iii) technology computer-aided design (TCAD) consisting of numerically solving electron and hole continuity equations and Poisson's equation for a specified physical device structure subject to appropriate boundary conditions and initial conditions. 1 All three levels are useful, but tend to be targeted towards answering different types of questions.Arguably, the simplest approach involves use of analytical mathematical relationships.This is the direction employed herein, but with a few novel and unorthodox twists and turns.
The goal of this contribution is to develop a set of direct current (DC) analytical equations for the analysis and design of a single-layer thin-film transistor (TFT).Initial modeling efforts are directed towards accurately modeling drift mobility as a function of applied gate voltage, μ drift (V G ).This is accomplished by accumulation layer electrostatics assessment of the TFT structure specified such that the semiconductor accumulation charge density, Q acc (V G ), and trapped charge density, Q T (V G ), as a function of applied gate bias are accurately estimated.Then, μ drift (V G ) is found by calculating the fraction of free (untrapped) charge, Q acc (V G )/(Q acc (V G ) + Q T (V G )), multiplied by the trap-free mobility, μ 0 (V G ). Once μ drift (V G ) is known, the lion's share of the modeling project is accomplished, and the drain current versus gate voltage transfer curve, (I D -V G ), or the drain current versus drain voltage (I D -V D ) output curve, for example, can be simply evaluated using the Enz, Krummenacher, Vittoz (EKV) compact model I D (V G ,V D ) equation.Within the context of this model, the EKV I D (V G ,V D ) equation can be viewed as an extrapolating function, since it takes as an input, linear regime TFT operation information pertaining to a uniform, one-dimensional channel, i.e., μ drift (V G ), and provides as an output, drain current information applicable to both linear and saturation regime TFT operation in which the channel is, respectively, either uniform, one-dimensional or nonuniform, two-dimensional, depending on the relationship between the applied drain voltage and gate overvoltage. 6][7][8][9][10]

| THE MODEL
Drain current is calculated as prescribed by the EKV compact model 11,12 As formulated, Equation (1) contains two independent (control) variables (gate voltage [V G ] and drain voltage [V D ], assuming that the source is ground), two TFT structure parameters (gate insulator capacitance density [C I ] and TFT width-to-length ratio [W/L]), and one physical operating parameter (temperature [T]), as well as one model parameter function (drift mobility as a function of gate voltage [μ drift (V G )]) and one model parameter (onset voltage [V ONSET ]).Note that the EKV formulation used in Equation ( 1) is a bit odd, as it includes an onset voltage parameter, V ONSET , rather than a turn-on (V ON ) or a threshold voltage (V T ) in the numerators of the exponential terms.In general, V ON is used as an onset indicator for subthreshold and log (I D )-V G transfer curve analysis, although V T is a better onset indicator choice for above threshold and I D -V G (linear ordinate scale) transfer curve or I D -V D output curve assessment.
Once the structure and physical operating parameters are specified, the key challenge in calculating Equation ( 1) is the appraisal of μ drift (V G ). Evaluation of μ drift (V G ) is accomplished by undertaking an accumulation layer electrostatics assessment of the single-layer TFT as summarized in Figure 1 (see the work of Wager 2 for a more detailed discussion of single-layer accumulation layer electrostatics assessment) and as briefly reviewed in the caption of Figure 1.
Although Figure 1 asserts that solving five equations in five unknowns is required in order to accomplish an accumulation layer electrostatics assessment, substituting Eqs.(iii), (iv), and (v) into Eq.(ii) and then substituting Eq. (i) into the resulting equation leads to that is, one equation in one unknown (ψ S ).Evaluating V ON as occurring in the limit of V G and ψ S approaching zero leads to the conclusion that V ON = Àb/C I .Eliminating V ON from Equation (2) yields: This is a key result, facilitating simulation of the drift mobility as a function of gate voltage.First, Equation ( 3) is solved for ψ S (V G ) using an iterative solver, for example, FindRoot in Mathematica.Then, Q acc (V G ) and Q T (V G ) may be calculated from Eqs. (iv) and (v) in Figure 1, respectively, such that drift mobility as a function of gate voltage is determined from: where μ o is the maximum drift mobility when negligible trapping occurs, that is, The two different versions of L D2 included in Figure 1 result in two different solutions to Equation (3), corresponding to either a "long-base" or "short-base" semiconductor channel thickness.Demarcation between "long-base" or "short-base" channel thickness is established by the maximum accumulation layer thickness, x acc (MAX), as follows.In general, the accumulation layer thickness as a function of surface potential is given by 2 : The maximum accumulation layer thickness is obtained when the surface potential approaches infinity, such that When d S > x acc (MAX), a "long-base" channel thickness prevails; whereas, when d S ≤ x acc (MAX), a "shortbase" channel thickness exists.L D and x acc (MAX) for the 40 nm a-IGZO TFT employed are equal to 43 and 95.5 respectively, assuming a semiconductor lowfrequency (static) dielectric constant of 12.8 and free electron density of 10 16 cm À3 . 2

| MODEL UTILIZATION
Figure 2 displays a comparison of mobility (μ) versus overvoltage (V G À V ON ) for a 40 nm a-IGZO TFT.The black curve corresponds to μ EKV as extracted from a measured transfer curve, 2,12 whereas the pink and green curves are simulated μ drift curves, as obtained by the solution of Equation (3) and use of Equation ( 4).For all simulations presented herein, the capacitance insulator density is 17.3 nFcm À2 , and the a-IGZO TFT is assumed for a 40 nm a-IGZO thin-film transistor (TFT).Black curve corresponds to μ EKV as extracted from a measured transfer curve.Pink (green) curve corresponds to μ drift as simulated using directly extracted (optimized for best fit) trap parameters.Simulated μ drift curves are obtained by solution of Equation ( 3) and use of Equation ( 4).
F I G U R E 1 Single-layer thin-film transistor (TFT) accumulation layer electrostatics assessment is accomplished via solution of five equations in five unknowns (V I , ψ S , Q M , Q acc , and Q T ).Under a forward (positive) gate overvoltage (V G -V ON , where V ON is the turn-on voltage), electric field lines originate on positive charge near the metal-insulator interface (Q M ) and terminate on negative accumulation layer charge (Q acc ) or trapped charge (Q T ) present in the semiconductor, giving rise to a voltage drop across the gate insulator (V I ) and semiconductor (ψ S ).The slope and intercept parameters presented as "a" and "b", respectively, characterize the trapped charge distribution.Two different version 2 effective Debye lengths (L D2 ) apply to Eq. (iv), corresponding to a "long-base" (LB) or a "short-base" (SB) channel thickness.
to have a "short-base" channel thickness (except for two of the simulations included in Figure 9, where a "longbase" channel thickness is assumed).
Returning to Figure 2, the pink curve is simulated using trap parameters obtained from direct trap extraction employing the method described in the work of Wager, 2 but assuming L D1 (not L D2 ) in assessing the surface potential (ψ S ), leading to an estimated trap concentration n T (ψ S ) = 5 Â 10 12 ψ S + 5 Â 10 10 cm À2 with μ o = 19.5 cm 2 V À1 s À1 .Although the simulated pink curve is quite similar to the extracted μ EKV (black) curve, the green curve is clearly a better match.The green curve is simulated using slightly different model parameters, that is, n T (ψ S ) = 6.5 Â 10 12 ψ S + 8 Â 10 10 cm À2 with μ o = 22 cm 2 V À1 s À1 , as obtained by adjusting model parameters in order to obtain a best-fit between measured and simulated mobility.The value of the green curve maximum (trap-free) mobility μ o = 22 cm 2 V À1 s À1 is particularly satisfying as it corresponds to the diffusive mobility qℏ/(6 m*k B T) obtained using an effective mass of 0.34 m 0 , that is, the electron effective mass normally assumed for a-IGZO. 13Although the simulated green curve closely matches the measured black curve above threshold, subthreshold current below an overvoltage of 1 V is not accounted for in this simulation.
Three model parameters are adjusted to obtain the green best-fit curve included in Figure 2, namely, a and b trap concentration parameters and μ 0 , the maximum (trap-free) mobility.Figure 3 locates the region of the simulated mobility curve in which each model parameter has a dominant effect.Basically, b controls the abruptness of the initial mobility rise; a determines the intermediate transition towards saturation, and μ 0 establishes the mobility maximum.In turn, each model parameter can be linked to a specific physical origin.The mobility rise, controlled by b, depends on the position of the Fermi level with respect to the conduction band mobility edge (which in turn depends on the free electron density) and (probably to a lesser extent) the near-flatband trap density.The intermediate transition towards saturation, controlled by a, is associated with conduction band tail states and near-to-the-conduction-band-mobility-edge traps.The maximum (trap-free) mobility, μ 0 , depends primarily on the conduction band effective mass, as evident from the expression for diffusive mobility, that is, qℏ/ (6 m*k B T).
Simulation allows for the possibility of predicting mobility trends as a function of variation of a given model or structure parameter, as presented in Figures 4-9.First, consider Figure 4, in which trap concentration is scaled.Decreasing trap concentration by a factor of 0.5Â (blue curve) significantly improves mobility performance, although increasing it by a factor of 2Â (green curve) or 4Â (red curve) dramatically degrades mobility.Clearly, trapping is important in determining TFT mobility performance.
Figure 5 displays simulated drift mobility trends as a function of trap concentration slope parameter, a.If this parameter can be reduced, mobility can be improved.However, because the slope factor is physically linked to the conduction band tail state and near-mobility-edge trap densities, it seems unlikely that such an improvement can be realized within a given materials system, such as a-IGZO.The conduction band tail state density depends on the conduction band effective mass and the Urbach energy. 14Thus, a sensible strategy for reducing the a trap parameter, thereby enhancing mobility, is to employ an alternative AOS, which possesses a smaller electron effective mass than that of a-IGZO, i.e., 0.34 m 0 .Finding an alternative AOS with an Urbach energy less than that of a-IGZO seems unlikely, as the Urbach energy of a-IGZO is very small, i.e., 13 meV. 14I G U R E 3 Regions in which the simulated mobility (μ) versus overvoltage (V G À V ON ) is primarily controlled by a given model parameter.a and b are the slope and intercept parameters, respectively, characterizing the trapped charge distribution, whereas μ 0 is the maximum (trap-free) mobility.
F I G U R E 4 Mobility (μ) versus overvoltage (V G À V ON ) for a 40 nm a-IGZO thin-film transistor (TFT).Black μ curve corresponds to μ EKV as extracted from a measured transfer curve.Other μ drift curves are simulated as a function of scaled trap concentration (n T ), as obtained by solution of Equation ( 3) and use of Equation (4).
Figure 6 confirms that a reduction in the trap intercept parameter, b, primarily improves the abruptness of the mobility onset, but only slightly enhances the mobility at large overvoltage.Physically, such improvements in mobility are likely to be realized by decreasing the semiconductor free electron concentration, thereby increasing the separation of the Fermi level with respect to the conduction band mobility edge.Note that when a "shortbase" channel thickness is employed, the mobility simulation based on solving Equation (3) and using Equation (4) is independent of the semiconductor electron density, N D , as L D2 does not depend on N D (whereas L D1 does depend on N D as a consequence of L D ).However, reducing N D is still advisable for a TFT with a "shortbase" channel thickness because reducing N D will (i) decrease b, as discussed above, and (ii) shift the turnon voltage to the right, such that it operates in a more enhancement-mode manner.
The simulation shown in Figure 7 suggests that mobility improves with decreasing semiconductor channel thickness, assuming that trap density does not increase with decreasing channel thickness.This implies that the channel thickness should be reduced as much as practicable.This predicted improvement in mobility due to a decrease in channel thickness is a consequence of having a "short-base" channel thickness in which L D2 depends explicitly on the semiconductor channel thickness, d S .
All simulations up to now have involved adjusting a semiconductor model or structure parameter.Figure 8 demonstrates through simulation that increasing the gate insulator capacitance density (C I ) is straightforward approach for improving TFT mobility.However, the simulated gains in mobility appear to be rather modest.For example, for the 40 nm a-IGZO TFT of Figure 8, the mobility at an overvoltage of 20 V can be improved from F I G U R E 7 Mobility (μ) versus overvoltage (V G À V ON ) for an a-IGZO TFT.Black curve corresponds to μ EKV as extracted from a measured transfer curve for a 40 nm a-IGZO thin-film transistor (TFT).Green curve is a simulated μ drift curve as optimized for best fit to the μ EKV black curve.Other μ drift curves are simulated as a function of semiconductor channel layer thickness (d S ), as obtained by solution of Equation ( 3) and use of Equation ( 4), assuming that 40 nm constitutes a "short-base" channel thickness.
F I G U R E 8 Mobility (μ) versus overvoltage (V G À V ON ) for a 40 nm a-IGZO thin-film transistor (TFT).Black μ curve corresponds to μ EKV as extracted from a measured transfer curve.Other μ drift curves are simulated as a function of gate insulator thickness (d I ), as obtained by solution of Equation (3) and use of Equation (4).13 to 18 cm 2 V À1 s À1 in going from the smallest (red curve) to largest (blue curve) insulator capacitance density employed in Figure 8.In practice, decreasing the gate insulator thickness to 50 nm is not likely to be a viable option because of reliability and other device and circuit considerations.
The fundamental physics underlying the trends observed in Figures 4-8 is quite simple.Mobility increases with decreasing trap density in Figures 4-7 because a smaller fraction of the gate voltage-induced channel charge is trapped so that more of it is mobile.Mobility increases with decreasing gate insulator thickness in Figure 8 because of a corresponding increase in insulator gate capacitance density and, hence, an increase in the amount of the gate voltage-induced charge.Quantitatively, both of these trends are captured in the electrostaticsbased expression C I (V G À V ON ) ≈ Q T + Q acc , recognizing from Equation (4) that superior mobility performance occurs when Q acc is maximized and Q T is minimized.
Precise drift mobility modeling depends critically on accurately establishing both the semiconductor free electron density, N D , and maximum (trap-free) mobility, μ o , as they (to a large extent) determine Debye length, L D , and trap concentration parameters, a and b respectively.However, N D and μ o are often not known and so are crudely estimated; this can lead to modeling ambiguities.For example, it is assumed that N D = 10 16 cm À3 for the 40 nm a-IGZO TFT employed in this study such that L D = 43 nm and x acc (MAX) = 95.5 nm so that it is concluded that 40 nm is a "short-base" channel thickness.
Instead, if it is assumed that N D = 6 Â 10 16 cm À3 , then L D = 17.4 nm and x acc (MAX) = 38.3nm so that 40 nm actually is a "long-base" channel thickness.Furthermore, if the 40 nm a-IGZO TFT is analyzed as a "long-base" device, adjusting model parameters in order to obtain a best-fit between simulated and measured mobility leads to a slight change in the estimated trap concentration, i.e., n T (ψ S ) = 5.1 Â 10 12 ψ S + 3.2 Â 10 11 cm À2 with μ o = 22 cm 2 V À1 s À1 in which a decreases and b increases compared with its "short-base" estimated trap concentration of n T (ψ S ) = 6.5 Â 10 12 ψ S + 8 Â 10 10 cm À2 with μ o = 22 cm 2 V À1 s À1 .Figure 9 illustrates mobility versus overvoltage trends for an a-IGZO TFT in which 40 nm is assumed to be a "long-base" channel thickness.Note that the two "long-base" mobility curves are identical, whereas mobility increases with decreasing channel thickness (d S ) for the two "short-base" mobility curves.In summary, nailing down N D is important for achieving accurate mobility assessment.One way to accomplish this is to perform a Hall measurement using a semiconductor thin film prepared in a similar manner to that of the TFT channel layer in order to directly measure N D .
A Hall measurement would also allow for assessment of the Hall mobility, which, perhaps, is correlated or identical to the maximum (trap-free) mobility, μ o .Obtaining an optimal estimate of μ o requires varying μ o in simulation to find a best-fit between measured and simulated μ drift (V G ) mobility curves and I D -V D output curves.

| CONCLUSIONS
An analytical model is proposed for the analysis and design of single-layer TFTs, using the EKV compact model in conjunction with drift mobility estimation via accumulation layer electrostatics assessment.Optimal TFT mobility is obtained when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that "short-base" TFT operation obtains.Improved mobility performance is achieved by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.
F I G U R E 9 Mobility (μ) versus overvoltage (V G À V ON ) for an a-IGZO thin-film transistor (TFT).Black curve corresponds to μ EKV as extracted from a measured transfer curve for a 40 nm a-IGZO TFT. Green curve (lying underneath the red curve) is a simulated μ drift curve as optimized for best fit to the μ EKV black curve.Other μ drift curves are simulated as a function of semiconductor channel layer thickness (d S ), as obtained by the solution of Equation ( 3) and usage of Equation ( 4), assuming that 40 nm constitutes a "longbase" channel thickness.

F I G U R E 5
Mobility (μ) versus overvoltage (V G À V ON ) for a 40 nm a-IGZO thin-film transistor (TFT).Black μ curve corresponds to μ EKV as extracted from a measured transfer curve.Other μ drift curves are simulated as a function of trap concentration slope parameter (a), as obtained by solution of Equation (3) and use of Equation (4).F I G U R E 6 Mobility (μ) versus overvoltage (V G À V ON ) for a 40 nm a-IGZO thin-film transistor (TFT).Black μ curve corresponds to μ EKV as extracted from a measured transfer curve.Other μ drift curves are simulated as a function of trap concentration intercept parameter (b), as obtained by solution of Equation (3) and use of Equation (4).