Minimising bulk lifetime degradation during the processing of interdigitated back contact silicon solar cells

In this work, we develop a fabrication process for an interdigitated back contact solar cell using BBr3 diffusion to form the p+ region and POCl3 diffusion to form the n+ regions. We use the industry standard technology computer‐aided design modelling package, Synopsys Sentaurus, to optimize the geometry of the device using doping profiles derived from electrochemical capacitance voltage measurements. Cells are fabricated using n‐type float‐zone silicon substrates with an emitter fraction of 60%, with localized back surface field and contact holes. Key factors affecting cell performance are identified including the impact of e‐beam evaporation, dry etch damage, and bulk defects in the float zone silicon substrate. It is shown that a preoxidation treatment of the wafer can lead to a 2 ms improvement in bulk minority carrier lifetime at the cell level, resulting in a 4% absolute efficiency boost.


| INTRODUCTION
The highest single-junction silicon wafer solar-cell power conversion efficiencies reported to date were achieved with the interdigitated back contact (IBC) architecture. Recently, Kaneka Corporation used an IBC heterojunction design to set a new single-junction silicon world record efficiency 1 of 26.7%. Back contact architectures eliminate front surface grid shading, thus potentially leading to higher short-circuit currents. As front surface doping is no longer necessary, a wider range of front surface texturing and light-trapping schemes are possible (e.g. nanoscale texturing). 2,3 Furthermore, a back-contact architecture is well-suited for mechanically stacked tandem cells with emerging materials such as perovskites. The fabrication of an archetypal IBC cell consists of local diffusion of boron into the back surface, followed by local diffusion of phosphorus, leading to alternating (interdigitated) p-and n-type regions 4 ; see Figure 1. The selective collection of the electrons and holes is optimized based on the diffusion length of the carriers as well as the passivation quality of p-and n-type regions.
A high collection efficiency of electrons and holes is vital for achieving high efficiencies, and therefore, the bulk minority carrier lifetime (or diffusion length) must be sufficiently long to ensure that a very high proportion of carriers reach their respective contacts. For IBC architectures where there are, in general, many high-temperature processes, the material must maintain high bulk lifetimes throughout cell fabrication. In this regard, float-zone (FZ) silicon is an attractive material for back junction solar cells, particularly in the laboratory, where exceptionally high lifetimes can be achieved owing to the high purity of the material. 5 However, recent work by Grant et al has demonstrated that FZ silicon contains defects, which are incorporated during crystal growth. 6,7 In as-grown samples, the defects are essentially latent, but they become activated as recombination centres upon heat-treating FZ silicon at temperatures between 450°C and 750°C.
Thus, although the as-received lifetime is very high, the lifetime can and consequently more suitable for high-efficiency solar cell architectures. This treatment (referred to as "bulk FZ treatment") consists of a dry oxidation for at least 30 minutes at 1050°C, which has the effect of out-diffusing vacancies and/or annihilating the vacancies by injection of interstitials during the dry oxidation. 8,9 In contrast, lower cost Czochralski (Cz) silicon wafers typically contain much higher oxygen concentrations and thus oxygen related defects, which can degrade the lifetime upon thermal processing and during cell operation, thereby making Cz silicon a more challenging material to use for IBC architectures. [10][11][12] In this work, we fabricate IBC cells using FZ wafers to investigate the influence of the bulk FZ treatment from the work of Grant et al on the cell efficiency. The cells were designed to have a planar front surface to facilitate their use in future planned studies on novel antireflection and light-trapping treatments and on siliconbased tandem cell development. We also present findings on cell fabrication process improvements developed during the study, including overcoming problems caused by reactive ion etching (RIE) and by electron-beam evaporation of metal contacts. We first use Sentaurus technology computer-aided design (TCAD) 13 to design the geometry of the device prior to fabrication. This determines the optimum emitter finger width and fraction as well as the diameter of localized back surface field (BSF) and contact holes.
Devices are then fabricated based on this design using a 4-stage lithography process, with various thermal, deposition, and etch steps.
Photoluminescence (PL) imaging, transient or quasi-steady-state photoconductance (PC) lifetime measurements, and current-voltage (I-V) characteristics are used to identify key degradation effects in the fabrication process. Additional I-V measurements are used to quantify performance improvements when defects are treated.
Finally, the TCAD model with input from our experimental results is used to identify how the devices can be further improved and to predict efficiencies achievable with this approach.
2 | CELL DESIGN USING TCAD TCAD modelling was used to optimize the cell geometry. The design was simulated using Sentaurus device, which calculates the currentvoltage characteristics using the Poisson equation coupled to the drift-diffusion transport equations. 13 Bulk and surface recombination mechanisms were both taken into account. For the surfaces, both chemical and field-effect passivation were considered. The 1-sun carrier generation profile used is calculated using OPAL2. 14 The doping profile for the emitter and BSF is defined by a Gaussian decay with a set peak dopant concentration and junction depth. The width of the half unit cell is 500 μm. The number of localized diffusions is based on the remaining area after the width of the emitter, and radius of the localized diffusion is taken into account. The parameters for the cell are shown in Table 1.
A 3-dimensional schematic of the unit cell of the IBC model defined in TCAD is presented in Figure 2A. We first optimized the width of the emitter (E w ) and BSF (B w ) regions, and therefore the emitter fraction. Figure 2B plots the efficiency as the widths of the doped regions are varied between 50 and 250 μm (overlaid, numbered diagonal lines indicate the emitter fraction). In the case of the BSF, the width refers to the area in which localised diffusions were used (see Figure 1). FIGURE 1 Schematic (top view) of the interdigitation in an interdigitated back contact cell, with boron-doped emitter fingers (in yellow), localised phosphorus-doped back surface field (BSF; in blue), and localised contact holes (in grey). The dimensions optimized using the TCAD model are labelled and include width of the p + emitter (E w ) and n + BSF (B w ) regions; the contact finger widths for n + region (nCF) and p + region (pCF); the diameter of the local diffusion hole size for the BSF (locDF) and contact hole (C w ), as well as pitch (C g ) for both. [Colour figure can be viewed at wileyonlinelibrary.com]  Figure 2B. These values for the emitter and BSF were then used to find an optimum local diffusion hole size of the BSF (locDF) and an optimum contact pitch (C g ).
The results of this are illustrated in Figure 3, where efficiency contours are plotted and different ratios of hole size to pitch are overlaid as diagonal lines. Data for ratios above 50% were omitted as the Sentaurus TCAD and Quokka. For consistency, the remaining parameters were taken from the IBC cell reported in Fell et al. 16 The results are shown in Table 2. The high efficiency potential of the optimized geometry is observed, with a modest gain in V oc compared to the work in Franklin et al. 4 Thus, the fabrication process in this work is based on the TCAD-optimized interdigitation design (GeoA) with E w = 125 μm, B w = 125 μm, locDF = 30 μm, C g = 100 μm, nCF = 125 μm, and pCF = 125 μm.

| Device fabrication
The device fabrication process is illustrated in Figure 4 and was based on a recipe taken from Franklin et al, 4 with the modified interdigitation design from the TCAD study above. Starting substrates were n-type FZ wafers (4″, <100>, 1-5 Ω-cm, 280 μm, double-side polished). In all cases, these were initially cleaned using RCA1, RCA2, and a dilute Hydrofluoric (HF) acid solution. Wafers undergoing the bulk FZ treatment were subjected to a double-sided dry oxidation for 30 minutes at 1050°C (1), which was subsequently stripped in HF (2). Processing for treated and control wafers was therein identical. A 230 nm   (6), and photolithographic patterning and etching to define the mask openings (7). Parameters for these steps were identical to those described above for the BSF regions. Boron doping was undertaken via tube diffusion using a liquid BBr 3 source (8). This consisted of a deposition step at 850°C with a 1:1 O 2 :BBr 3 gas ratio, followed by a drive-in at 920°C and an in situ oxidation to dissolve any potential potential boron-rich layer (BRL) of SiB 6 formed during the process. The borosilicate glass and p + diffusion mask were then removed using dilute HF.
With the p + and n + regions defined on the rear surface, both the front and rear surfaces were passivated (9). First, the rear surface  activate the Al 2 O 3 passivation, the wafer was subsequently annealed in an RTA at 400°C for 10 minutes in a N 2 ambient. The final step of metallization was achieved using 2 lithography steps. In the first step, 10-μm diameter contact holes were opened in the rear passivation stack using the same positive process as for the n + diffusion mask, but with the wet etch time increased to 10 minutes to fully clear the (10). A second lithography step, based on a negative resist lift-off process, was then used to define the contact fingers (11).
This consisted of a dehydration bake (180°C, 5  Metal lift-off was achieved by soaking in acetone and ultrasonic agitation (12). The final step was a 1-minute sinter at 350°C in an N 2 ambient to help lower the contact resistance and form an ohmic contact.

| Characterization
The devices were characterized using several techniques. Doping profiles of the p + and n + regions were measured using an electrochemical capacitance voltage tool (WEP, CVP21  prior to metallization. We suggest that this is likely due to X-rays

| RIE damage
When dry etching was used for pattern transfer prior to diffusion (steps 4 and 7 in Figure 4), low PL counts were observed in patterned regions of the wafer ( Figure 5B, right side), whereas lifetime monitor wafers maintained high PL counts ( Figure 5B, left side). These monitors underwent identical diffusion and passivation steps, but did not undergo any patterning. RIE-induced damage of the patterned area was therefore suspected. Shallow implantation of reactive ions as well as lattice damage has been shown to produce surface degradation in silicon. [23][24][25][26][27] The right-hand image in Figure 5C shows a PL image of a test wafer patterned using RIE, then doped using BBr 3 (Figure 6), which reveal an increase in effective minority carrier lifetime in cells, after passivation anneal and before contact opening (ie, after step 9 in Figure 4), from <100 to 460 μs when RIE was replaced by wet etching for the pre-diffusion pattern transfer steps. The measurements in Figure 6 are aggregated transient measurements, as multiple cells are measured over the sensor region, including the higher lifetime regions in between the cells.
Therefore, the lifetime measurements in Figure 6 could be overestimated, and thus the actual bulk lifetime of the cells is likely to be slightly lower than measured.   30 In this case, the passivation is assumed to be conformal (i.e. it also passivates the edges).

| Bulk defects
The SA passivation process occurs at room temperature, so artefacts that occur because of annealing during passivation by conventional dielectrics are avoided.
To investigate/remove edge recombination effects on the 2 × 2 cm IBC cell samples, 2 additional control 270 μm thick FZ 2.6 Ω-cm n-type samples were passivated with SA, (1) a 4-inch quarter sample and (2) a 2 × 2 cm sample from the same wafer. From the resulting lifetime results presented in Figure 8, it is evident that SA passivation provides excellent surface passivation, yielding a τ eff of approximately 5 ms on the larger quarter wafer sample (blue circles).
In contrast, the smaller 2 × 2 cm control sample yields a τ eff of approximately 4 ms (orange squares), which we attribute to edge recombination effects that do not impact the larger sample. In both cases, however, the surface recombination velocity of SA-passivated silicon is predicted to be 0.65 ± 0.05 cm/s using the S parameterisation developed in Grant et al. 30 Therefore, to correct for a surface recombination velocity, S, of 0.65 ± 0.05 cm/s (front/back) on both control samples, we have used the following equation 31 (where W corresponds to the sample thickness): whereby the dashed blue line in Figure 8 represents Turning back to the 2 IBC cell samples, Figure 9A plots the measured effective lifetime of cell A (no bulk FZ treatment) and cell B (with bulk FZ treatment) after removal of the dielectric layer and diffused region and subsequent passivation with SA. Before correcting for both surface and edge recombination, it is evident that cell A has a lower bulk lifetime compared to cell B. However, to ascertain the true bulk lifetime of each cell material, both surface (S = 0.55 ± 0.05 cm/s) and edge recombination (S edge = 0.7 cm/s) effects were removed from the measured τ eff . In this case, a lower S value is used because the doping of the cell material is lower compared to the control samples of Figure 8, thereby resulting in a slightly lower S as outlined in Grant et al. 30 The true bulk lifetime of each cell is therefore given by the dashed lines in Figure 9A. As seen in Figure 9A, the actual difference in bulk lifetime is approximately 2 ms once external recombination mechanisms are accounted for (surface and edge).
Finally, to quantify the bulk lifetime reduction during IBC cell fabrication, Figure 9B plots the effective (solid symbols) and bulk lifetimes (dashed lines) of 2 silicon wafers (neither of which were subjected to the bulk FZ treatment), (1) in the as-received condition and (2) after the boron diffusion, which was subsequently etched away prior to SA passivation. From Figure 9B, it is evident that the "as- Although we do not understand the cause for the large reduction in τ bulk following the boron diffusion, we can postulate that some level of contamination has occurred during this process, which could be reduced by removing the BRL by a wet chemical process to prevent any impurities in the BRL being diffused into the bulk material during the traditional in situ oxidation to dissolve the BRL. 18 On the contrary, it is also known that boron diffusions can form dislocations that diffuse into the bulk material, which have shown dependence on the BRL thickness. 34 Therefore, to minimise bulk degradation during cell fabrication, an optimised boron diffusion process, which limits bulk contamination or defect formation, is required and/or a phosphorus diffusion barrier is necessary to minimise any contamination or defect penetration resulting from the boron diffusion (ie, front side n + protection layer). In the latter case, the protective n + layer can be removed during front-side texturing or immediately before surface passivation.

| Further analysis with TCAD modelling
To observe the influence of varying lifetime on the IBC cell, we used the TCAD model but replaced the doping profile for the emitter and BSF with ECV measured experimental data, as well as typical fixed charge, interface defect density, and capture cross-sectional data for the dielectric/doped (n, n + , and p + ) interfaces used for the solar cells.
The bulk lifetime was then varied to gauge its influence on efficiency.
The same sweep was undertaken when the lumped resistance (calculated The modelled results show that for cell B, a difference in τ bulk of 2 to 5 ms does not result in any significant change of efficiency performance, unlike our experimental data, which showed a 28% increase. The lifetime measurements of the cell wafers shown in Figure 6 (cells A and B), however, are significantly lower. We therefore postulate that the significant difference in lifetime between cell A with Al 2 O 3 /SiN x passivation ( Figure 6) and cell A with SA passivation ( Figure 9A)   Photoluminescence studies showed improvements when metallization was followed by a sinter and when dry etching during the pre-diffusion pattern transfer was replaced with wet etching.