Can we see defects in capacitance measurements of thin‐film solar cells?

Thermal admittance spectroscopy and capacitance‐voltage measurements are well established techniques to study recombination‐active deep defect levels and determine the shallow dopant concentration in photovoltaic absorbers. Applied to thin‐film solar cells or any device stack consisting of multiple layers, interpretation of these capacitance‐based techniques is ambiguous at best. We demonstrate how to assess electrical measurements of thin‐film devices and develop a range of criteria that allow to estimate whether deep defects could consistently explain a given capacitance measurement. We show that a broad parameter space, achieved by exploiting bias voltage, time, and illumination as additional experimental parameters in admittance spectroscopy, helps to distinguish between deep defects and capacitive contributions from transport barriers or additional layers in the device stack. On the example of Cu(In,Ga)Se2 thin‐film solar cells, we show that slow trap states are indeed present but cannot be resolved in typical admittance spectra. We explain the common N1 signature by the presence of a capacitive barrier layer and show that the shallow net dopant concentration is not distributed uniformly within the depth of the absorber.

interfaces, which means that the measured device capacitance typically cannot be attributed to the SCR alone. This complex device geometry might thus require a complex electrical equivalent circuit [6][7][8][9][10][11] to even identify the SCR capacitance from the measurement. On the other hand, inter-diffusion of mobile species between the thin layers in the device stack [12][13][14][15][16][17][18] likely results in graded interfaces, where electronic properties could vary drastically with depth.
The resulting complexity of experimental capacitance spectra of thin-film devices has often led to considerable controversy how such measurement could be explained most appropriately. We will focus on typical Cu(In,Ga)Se 2 (CIGS) thin-film solar cells to illustrate this challenge, but our experimental approach will be equally relevant and straight-forward to adapt for other thin-film technologies with complex device stacks, for example, perovskite, Cu 2 ZnSnSe 4 (CZTSe) kesterite, or CdTe. Solar cells based on CIGS are very flexible with respect to device architecture and elemental composition, and thus abundance of intrinsic electronic point defects, and the exact details of experimental capacitance spectra often differ substantially between individual samples. Nevertheless, two characteristic features appear to be universally observed for virtually all CIGS thin-film solar cells: • At least one pronounced step of the frequency-dependent capacitance in TAS with an activation energy around 100 meV, which has been termed the "N1" signature in CIGS. 6,19,20 A similar capacitance step has also been reported for CZTSe 21 and CdTe. 22 • A "U"-shaped depth-dependent doping profile, 6,17,18,[23][24][25][26] resulting from a curved "Mott-Schottky" plot. The minimum apparent dopant concentration is typically in the range of a few 10 15 cm −3 to 10 16 cm −3 and increases toward negative bias voltages, that is, toward higher apparent depth within the absorber.
Deep defects lead to non-radiative recombination losses, and thus characterization of their capacitive response is of highest concern for the optimization of solar cell efficiency. Historically, capacitance steps in TAS have been most widely assigned to defect levels in semiconductors. Indeed, a capacitance feature in CIGS termed "N2" 19 was found to be a bulk defect and was shown to scale with the Ga content in the absorber and to adversely affect the device efficiency for high Ga concentrations. [27][28][29] This N2 defect level appears to be no longer present in state-of-the-art high-efficiency solar cells. 30 Defects have traditionally also been thought to cause the N1 signature in CIGS, which has been proposed as the signature of a defect level either at the interfaces 19,31 or in the bulk. 26 Electronic effects other than defect levels result in capacitance steps as well, and the N1 level has also been linked to transport phenomena in the bulk 32,33 or transport barriers at interfaces or additional layers within the device. 6,8,10,11,22,30,34,35 Note that seemingly different capacitance steps in different samples are commonly identified with the same feature, in this case, N1, if their attempt-to-escape frequency and activation energy-obtained from the temperature dependence of the inflection frequencies-lie on the same line in a Meyer-Neldel plot. 36,37 In particular for the N1 signature, literature reports scatter substantially around such a line, 20 and the Meyer-Neldel rule might in fact not be a suitable tool to classify defect signatures. 30 Furthermore, several independent signals might contribute to a single capacitive response identified as N1, 34,38,39 indicating that the dominant physical origin of the N1 signature is not necessarily the same for all solar cells-despite the similarity of the corresponding capacitance steps. A more detailed recent discussion of the various models to describe the N1 signature is presented in Ref. 30 Apparently, a consistent and universally applicable model to describe the N1 signature is currently out of reach. In fact, such a model might not even exist because-as discussed above-the seemingly universal N1 signature might have very different physical causes in different individual solar cells. Without an unambiguous understanding of all steps in the frequency-dependent capacitance spectrum and how these might relate to potential electronic defects in the semiconductor, in particular for the ubiquitous N1 signature, any interpretation of deep defect and dopant concentrations from capacitance measurements will necessarily be uncertain. This limitation of our current understanding of capacitance-based characterization of thin-film solar cells has very relevant practical consequences: Although the net dopant concentration is one of the most important quantities defining the operation of a semiconductor device, 3 and although recombination via deep defect levels is a major limitation of solar cell efficiency, we currently have no simple experimental approach to correctly and reliably quantify these two parameters for a thin-film solar cell.
We recently presented a number of studies on the electronic properties and resulting capacitance spectra of CIGS solar cells, where we combined Hall measurements, 18,40 ac impedance measurements under varying experimental conditions (frequency, temperature, bias voltage, illumination, and time), 10,17 temperature-dependent current-voltage measurements, 30 numerical device simulations, 9,30,41 and deliberate variations in absorber chemistry 30 and layer stack architecture 10,11,17,30 in an attempt to establish a consistent understanding of the electronic properties of these particular devices. We concluded that the universality of the N1 signal and typical doping profiles-for CIGS solar cells fabricated in our laboratory-are most likely linked to the deposition of the standard CdS/ZnO buffer/window layer stack onto the CIGS absorber, resulting in most cases in a transport barrier 10,11,30 (causing a capacitance step) and formation of additional donor-type defects near the interface (reducing net dopant concentration near the interface). 17,18 We also found similar mechanisms in state-of-the-art high-efficiency solar cells fabricated at different institutes. 30 Nevertheless, these results still cannot answer all questions for the devices under investigation and do not necessarily apply to all CIGS solar cells. Such an extensive set of measurements is also certainly not a feasible approach for quick monitoring, loss analysis, and optimization of thin-film solar cells.
In this manuscript, we demonstrate how to assess capacitance measurements of thin-film devices and develop a range of criteria that allow to estimate whether deep defects are evident in the capacitance measurement. We show that a broad parameter space, achieved by exploiting bias voltage and illumination as additional experimental parameters in admittance spectroscopy, helps to verify whether deep defects can consistently explain features observed in capacitancebased measurements.
In Sections 2 and 3 we discuss a simple analytical model of the capacitance step height in TAS, which helps to distinguish between majority and minority carrier traps and allows to constrain the energetic depth of a trap associated with the respective capacitance step.
We find that a defect response and effects of interfaces or additional layers in the device can be distinguished by combining conventional TAS with photoluminescence measurements or by studying the illumination-or voltage-dependence of thermal capacitance spectra.
In Section 4, we review the effect of a depleted buffer layer, Schottky-type back contact barrier, or any similar capacitive transport barrier on the temperature-dependent capacitance spectrum of a thin-film device. We focus on differences in the capacitance response between deep defects and such a transport barrier, in particular, with respect to admittance measurements under varying bias voltage and illumination. In Section 5, we then discuss the impact of slowly responding deep trap states on C-V measurements and thus experimental doping profiles, even if they do not produce a direct capacitive response at typical measurement frequencies and temperatures in TAS.

| ELECTRON/HOLE TRAP RESPONSE IN CAPACITANCE SPECTROSCOPY
In order to evaluate a given capacitance step in TAS as response of a deep defect, it is instructive to formulate a set of criteria describing under which conditions-and to which effect-such a defect response could be expected. The occupation probability of a defect level under steady-state conditions is determined by the energetic position E t of the trap with respect to the electron or hole quasi-Fermi level E Fn.p (minority or majority carrier trap, respectively, in a p-type CIGS absorber). In experiment, the small-signal capacitance is probed by a small ac voltage modulation with frequency f around a fixed steadystate working point defined by the applied dc bias voltage V dc . Under these conditions, the characteristic capture and emission rate of the trap will limit its ability to follow the external ac modulation at high frequencies. If the trap level cannot follow the ac modulation at high frequencies, its occupation probability becomes time-independent and is determined by the applied dc bias voltage.
As a result, charge modulation in the trap level stimulated by the external ac voltage will add a frequency-dependent capacitance step to the capacitance of the SCR, with inflection frequency f t determined by capture/emission characteristics of the trap and with vanishing capacitance contribution toward high frequencies. Although we no longer observe a direct capacitive contribution at high frequencies originating from charge modulation in the traps, their steady-state occupation modifies the band bending within the SCR, as discussed below. As a result, the SCR capacitance observed at high frequencies will be modified by the presence of deep traps, even if these traps do not follow the ac modulation.
These fundamental considerations have two important practical consequences: 1. The trap level has to cross the quasi-Fermi level, and the inflection frequency has to be within the experimentally accessible measurement range to observe a capacitance step caused by a defect.
2. The SCR capacitance-and thus experimental doping profiles-will be influenced by deep defects even for measurement frequencies well above their inflection frequency, as long as the trap levels have sufficient time to equilibrate with the respective steadystate quasi-Fermi level at a given bias voltage.
We will discuss these two cases individually in more detail in Sections 3 and 5.
Note that the presence of different defects with separate energy levels results in multiple capacitance steps 42 because defects might differ in capture cross-section and because each defect level would cross the Fermi level at a different depth. To simplify the formal calculations below, we nevertheless assume a single defect level. We find empirically that the capacitance spectrum in a given frequency and temperature range is often dominated by a single capacitance step, at least in state-of-the-art Cu-poor CIGS solar cells that do not show a significant concentration of the detrimental N2 defect level. We will discuss this dominant capacitance step as the "main capacitance step" in the following. In most CIGS or similar solar cells, this step would likely be identified as the N1 signature, although, as discussed in the introduction, such a label might be misleading.
We also explicitly ignore capacitance steps related to ohmic series resistance and dielectric freeze-out. Ohmic series resistance causes a breakdown of the measured capacitance value to zero with increasing ac frequency. 43 Assuming a practically low value of series resistance for a solar cell, this occurs at high frequencies of several hundred kilohertz or above, a frequency range that we thus neglect in analysis. At low temperatures, the dielectric response of majority charge carriers in the absorber layer can become too slow to follow ac modulation ("freeze-out") due to reduced free carrier concentration or mobility.
The absorber then acts as an insulator, and the capacitance drops to the geometric capacitance C geo = ε 0 ε r /d, with d being the full absorber thickness. Because the absorber thickness is typically known, a freezeout can be identified by the absolute value of the high-frequency capacitance.

| CROSS-OVER OF TRAP LEVEL AND FERMI LEVEL
In a simple analytical model of the SCR in a one-sided abrupt p/n-junction, the step in the capacitance spectrum originating from a deep trap can be expressed by the equations 1 Because Equation (2) is somewhat unwieldy in its usual form, the capacitance step height is commonly neglected when extracting information about defect levels from capacitance measurements. For example, the fitting procedure proposed by Weiss et al. 21 treats the capacitance step height as a free fitting parameter. That model is intended to correctly separate overlapping capacitance features and identify their distinct apparent activation energies but cannot determine whether a given capacitance feature is in fact a defect nor its quantitative concentration.
In contrast, Walter et al. 45 had earlier developed a theoretical model to determine a defect density of states from the derivative dC/d f of the capacitance spectrum, which does take into account the magnitude of the capacitance step. This model, however, assumes a priori that a given capacitance step is indeed caused by deep defects: The defect concentration is calculated from the capacitance derivative assuming a fixed built-in potential, whereas the energy axis is calculated independently from the attempt-to-escape frequency (obtained from an Arrhenius plot of the temperature-dependent inflection frequencies of the capacitance step). The energetic depth of the defect level and the magnitude of its capacitive contribution-proportional to defect density-are thus decoupled because both are calculated from independent quantities (capacitance and frequency  Fermi level at the defect energy E t and thus limit the built-in potential across the p-type CIGS to values close to E t − E F.p , invalidating the calculated relation between defect concentration and capacitance step height for relatively shallow defects.
It is worth pointing out that we do not dismiss the Walter method.
In their original paper, 45  We conclude that it is mandatory to establish the cause of a capacitance step-i.e., deep defects or not-before attempting to quantify any defect parameters using standard methods like the Walter method. In the following, we will show that the capacitance step height provides a useful criterion for the correct interpretation and assignment of capacitance steps in admittance spectroscopy, in particular, if the corresponding activation energy is around 100 meV or lower.
It is convenient to express Equation (2) not in terms of capacitance but in terms of corresponding equivalent depth x = ε 0 ε r /C. Rearranging where λ = x d − x t is the distance over which band bending in the depletion region leads to a cross-over of (quasi) Fermi level E F and trap level E t , see Figure 1. The depth-dependent electrostatic potential in the depletion region is found by integrating the electric field F , which is linked to the local net charge density ϱ(x) by the Poisson equation . The required band bending over the SCR to ensure a cross-over of Fermi level E F and trap level E t for a majority carrier trap is equal to the energy difference E t − E F . Assuming a constant bulk net doping N d , the distance λ is then given by 1 Although Equation (5) (5) from Equation (4) introduces some complications: By assuming N d = p, we ignore incomplete ionization of dopants at low temperatures. According to van Opdorp, 47 however, this only modifies the built-in potential and not the bias-dependent band bending relevant for Equations (4) and (5) because shallow acceptors will mostly be ionized within the SCR anyway. Equation (5) also eliminates the dependence on bulk Fermi level by implicitly assuming that Fermi level for which the capacitance step height would be maximal. In that sense, Equation (5) is indeed only applicable to estimate the maximum step height Δx or minimum trap depth. Furthermore, Equation (5) requires an assumption of N v , which is not known precisely. In contrast, Equation (4)   capacitance step is resolved in a typical temperature range of up to 200 K, the capacitive response of a shallow defect level 100 meV above the valence band would only modulate the apparent depth by less than 10 nm. Note that the capacitance step height ΔC in experiment is typically found to be virtually independent of temperature or to even increase with increasing temperature. Thus, the highest temperature where a capacitance step is still resolved typically imposes the strictest limit to the energetic depth of the trap.
In comparison with the theoretical limit for a majority carrier trap according to Equation (5), black symbols in Figure 2    The main observation from Figure 3 is that the capacitance step height for this particular sample always corresponds to a change of equivalent depth of Δx = 110±10 nm, independent of experimental condition. Note that this observation is fairly obvious from the apparent depth shown in Figure 3(a) but not readily apparent from the typical capacitance spectrum shown in Figure 3(b). If a discreet majority carrier trap level was responsible for this capacitance step, the resulting capacitance step height would indeed be independent of bias voltage over a wide range, compare Equation (4). As discussed in Section 3 above, however, we would expect this capacitance step to disappear close to flatband conditions within the absorber (Figure 1 For minority carrier traps as alternative explanation of this capacitance step, we expect the capacitance step height to vary with bias voltage as discussed above, which apparently is not the case here. Based on these bias-dependent capacitance spectra, it is thus extremely unlikely that defects could explain the main capacitance step in TAS experiments presented here.

| EFFECT OF CAPACITIVE TRANSPORT BARRIERS ON DEVICE CAPACITANCE SPECTRA
Transport barriers due to a non-ohmic back contact or buffer and/or window layers have been proposed as alternative explanations for the N1 signature. 6,8,10,11,22,30,34,35 Below we will show that such barriers in a thin-film solar cell not only explain the N1 signature in TAS more naturally than defects but also agree with voltage-and illumination-dependent capacitance spectra. Certain evidence suggests that the buffer layer 10,11 or interfaces between buffer and window layers 30 are responsible for this barrier in our own measurements. Note that any other (interfacial) layers, band offsets, or nonohmic contacts could be alternative possibilities for transport barriers in the device. For the sake of brevity, we will use the general term "barrier layer" throughout this section to refer to any such transport barriers or interlayers with capacitive impedance contributions.
A transport barrier or additional layer in the device can be modeled as an additional electrical circuit element in series with the p/n junction of the solar cell, as sketched in Figure 4(a). One of these elements represents the barrier layer (G b and C b ); the other element originates from the SCR of the p/n junction (G j and C j ). The lumped series resistance R s in Figure 4(a) explains a breakdown of the measured capacitance at high frequencies but will be ignored in this manuscript. The effective frequency-dependent total capacitance of such a device shows a step 6,10,35 with inflection frequency even if all individual parameters G b , G j , C b , and C j are independent of frequency. For the right-hand-side of Equation (6), we have assumed that the barrier and junction capacitances only have a week temperature dependence and that the barrier layer is much more conductive than the (blocking) junction, G b ≫ G j . As such, the temperature dependence of the inflection frequency is mainly determined by the conductivity of the barrier layer. If this conductivity is at least approximately thermally activated, the thermal capacitance spectra resulting from a barrier layer in series with the main junction will potentially look identical to those caused by the response of a deep defect level. For comparison, the temperature-dependent inflection frequency for a defect response is typically given by 1 with thermal velocity v th , effective density of states N c,v in the conduction or valence band, and electron or hole capture cross-section σ n,p and activation energy E a of the defect. The quadratic temperature term accounts for the temperature dependence of thermal velocity and effective density of states.
The series connection of barrier and junction elements in Figure 4(a) means that each element adds one peak at a characteristic frequency f char = G b,j /(2πC b,j ) to the total impedance spectrum Z( f ). Note that these characteristic frequencies in the impedance spectrum, which are indeed specific for each individual layer, are not the same as the inflection frequency in the corresponding capacitance spectrum, which, according to Equation (6), depends on both elements. Accordingly, the impedance spectrum is more appropriate to study individual layers than the commonly chosen admittance or capacitance spectrum. More precisely, we find that the normalized real impedance spectrum Re{ωZ( f )}, equivalent to the real part of the inverse complex capacitance, is typically most suited to identify both contributions from junction and buffer layer in our thin-film devices. 10 The reason is that the height of a characteristic peak in the impedance spectrum is proportional to the resistance of that circuit element, which differs drastically between barrier layer and junction, whereas the peak height is proportional to the inverse capacitance in the ωZ( f ) spectrum. Figure 4(b) shows such normalized real impedance spectra for different applied bias voltages at a temperature of 100 K, which is the same raw data represented as capacitance spectra in Figure 3. We clearly observe two distinct peaks, which react differently to changes in bias voltage: 1. Junction: The low-frequency peak (below 1 kHz) varies in magnitude and peak frequency as a result of the voltage dependence of SCR capacitance, diode current, and shunt 54 current. and fairly large capacitance step height discussed in Section 3, which would require a deep but discreet or fairly narrow defect distribution.
We thus conclude that the mere presence of a barrier layer is the more likely origin of the main capacitance step in admittance spectroscopy, rather than deep defects.
Besides the different interpretations of the inflection frequency discussed above, barrier layer and defect also differ in the interpretation of the capacitance values before and after the capacitance step.
Here, the correct identification of the SCR capacitance is of highest importance, in particular for the correct choice of measurement condition for the determination of doping profiles from C-V measurements: For a capacitance step caused by a defect, the SCR capacitance is equal to the high-frequency limit, compare Equation (1). If the capacitance step is due to a barrier layer, however, the SCR at least approximately equals the low-frequency limit of the capacitance. 10

| IMPACT OF DEEP TRAP LEVELS ON EXPERIMENTAL APPARENT DOPANT PROFILES
Apparent doping profiles for CIGS are usually found to be depthdependent, 6,18,[23][24][25][26] Figure 5 shows these transients at a frequency of 10 kHz and T = 300 K expressed as apparent SCR width x = ε 0 ε r /C for bias voltages in a range of +0.7 to −3.0 V.
In Figure 5, we clearly observe an initial instantaneous change in apparent SCR width, with respect to the time resolution of 1 s in these measurements, whenever the bias voltage is changed. We attribute this initial change to the quasi-instantaneous reaction of the majority carrier concentration, and the corresponding initial apparent width x 0 thus corresponds to the real SCR width of a hypothetical device free of deep defects. Such a hypothetical device would have exactly the same net dopant concentration throughout the absorber as the real device, but all defects would appear to be shallow. A Mott-Schottky plot constructed from the initial value x 0 and its bias dependence thus yields the actual net dopant concentration at the depth of the SCR edge, shown in Figure 6(a). After the initial redistribution of majority carriers, however, we indeed observe a slow charge equilibration of defects within the SCR for most bias voltages, and the apparent SCR width increases to its steady-state value x eq over timescales of several seconds to minutes.
Our measurements thus clearly show evidence for the presence of slow or metastable deep trap states, and their impact on extracted doping profiles needs to be considered. In Figure 6, we compare a "slow" C-V measurement (−0.2 V steps each 30s) with an idealized "fast" measurement, where we take the initial capacitance C = ε 0 ε r / x 0 from the capacitance transients in Figure 5(a) as SCR capacitance of an ideal device free of the influence of deep defects. Blue circles in For most CIGS devices measured in our lab, however, this simplified model leads to several inconsistencies: 1. The apparent transition between two different slopes in the Mott-Schottky plot occurs between 0 and −1 V, see dotted lines in Figure 6(a). From the capacitance transients shown in Figure 5 for the same sample, however, we would already expect a significant contribution of deep defects over most of the fitting range of the forward bias slope in Figure 6(a).
2. The apparent dopant concentration shown in the inset of Figure 6 (a) does not saturate, which indicates that the Mott-Schottky plot is in fact not straight, not even in strong reverse bias. This is not easily apparent from the Mott-Schottky plot itself, where the linearly with depth. In that scenario, the inverse cubed capacitance 1/C 3 , rather than the inverse squared capacitance 1/C 2 , would form a straight line as a function of applied bias voltage. 47 This is indeed the case here, as demonstrated by the "fast" C-V data and corresponding linear fit shown in Figure 6(b).
A straight plot of 1/C 3 vs V dc is a useful hint to consider a doping gradient but in itself is not a definite proof for a graded dopant concentration near the absorber/buffer junction. Nevertheless, such a reduced net doping in the absorber close to the hetero-junction is able to conveniently explain a number of experimental findings: 1. The increase in SCR width during experimental capacitance transients, Figure 5  Unfortunately, deep defects and buffer layers are difficult to distinguish in a classical admittance spectroscopy measurement because they result in functionally identical capacitance steps. In fact, it is common practice to record temperature-dependent capacitance spectra only at zero bias voltage and extract a thermal activation energy from an Arrhenius plot of the inflection frequencies of a given capacitance step. Other characteristics of such a capacitance step are often not taken into account, although they might be able to shed more light on the mechanisms responsible for this capacitance step. Under these circumstances, it is virtually impossible to distinguish between deep defect and circuit response.
Based on a simple analytic model of band bending in the depletion region, we demonstrated that the voltage-dependent height of a capacitance step is most conveniently expressed as a change of apparent depth Δx = ε 0 ε r /C and is a helpful measure to identify the physical origin of a capacitance step. If traps are responsible for the capacitance step, the voltage-dependent step height allows to distinguish between majority and minority carrier traps, and the magnitude of the change in apparent depth defines a strict lower limit to the energetic depth of the trap, at least in the case of majority carrier traps.
We found that fairly shallow defects below 150 meV will be extremely difficult to resolve in TAS. Furthermore, deep defects can be ruled out if the capacitance step remains present at high forward bias around the flatband voltage. On the other hand, the mere presence of a transport barrier due to a non-ohmic back contact or additional layers in the device stack naturally leads to a capacitance step. In this case, the impedance spectrum multiplied by frequency is more convenient than the admittance spectrum because it allows to isolate contributions from individual layers within the device.
We applied these criteria to experimental capacitance spectra of typical CIGS solar cells with CdS buffer layer and i-ZnO/ZnO:Al double window layer, which show the well-known N1 signature as main capacitance step. We found that deep defects would need to be fairly deep majority carrier traps, and their energetic depth would need to be severely underestimated by the thermal activation energy from an Arrhenius plot in order to explain experimental capacitance spectra at moderate bias voltage. Even defects with these properties could not explain why the N1 signature is still visible at high forward voltages. A transport barrier, for example, a depleted buffer layer, on the other hand, would naturally explain all experimental capacitance spectra.
We further demonstrated that photoconductive effects in the buffer layer result in a linear shift of inflection frequency with illumination intensity, which would not be the case for a discreet defect level.
We conclude that the main capacitance step in our devices, which agrees well with the N1 signature, is most plausibly explained by the presence of a buffer layer connected in series to the p/n junction of the device and is not related to any deep defects.
Although we thus do not observe any capacitance steps related to deep defects, such defects are still present in our CIGS devices: capacitance transients upon changing the applied bias voltage from a controlled initial state near flatband conditions revealed a quasiinstantaneous response by majority carriers at the SCR edge, followed by a comparably slow expansion of the SCR over timescales of many seconds or even minutes. We attribute this expansion to a slow equilibration of deep trap states, which now cross the Fermi level.
The response time of these trap states, however, is too slow to be observed in TAS measurements in a typical frequency range above several hertz. Nevertheless, these slow trap states have a noticeable influence on experimental apparent doping profiles determined by C-V measurements, if the voltage sweep rate is slow enough to allow (at least) partial equilibration of deep traps within the measurement duration.
Mott-Schottky plots constructed from the capacitance transients, however, showed that typical depth-dependent apparent doping profiles in CIGS devices are only partially explained by these deep traps.
Rather, the net dopant concentration near the buffer/absorber interface is physically reduced in the presence of a CdS or Zn(O,S) buffer layer, resulting in a graded doping profile at the electronic junction.
In this case, the inverse cubed capacitance, rather than the inverse squared capacitance, is expected to yield a straight line, which was indeed observed for our CIGS devices. Thus, changes in the absorber material during processing of the solar cell front layers or during operation and aging of the device must be considered in the correct interpretation of doping profiles obtained from C-V analysis in any heterojunction solar cell: The true bulk dopant concentration in these devices might be considerably different than expected.

| CONCLUSIONS
The height of a capacitance step is often overlooked in the analysis of capacitance spectra in TAS, although this measure can provide a wealth of information about the origin of a capacitance step. This was shown to be particularly true if temperature-dependent capacitance spectra are recorded over a range of applied bias voltages. Additionally, illumination can be exploited as additional experimental parameter to consolidate the analysis. If the capacitance step is caused by a deep defect, the capacitance step height allows to distinguish minority and majority carrier traps and provides an independent measurement of the energy level of the trap. Even if such measurements might rule out defects as origin of any steps in experimental capacitance spectra, trap states with response times too slow to follow the ac modulation at all might however still be present in the absorber.

APPENDIX B SIMULATION PARAMETERS
Simulations of band bending in CIGS thin-film solar cells were run in SCAPS v3.3.05 44 at a temperature of 300 K and ac frequency of 1 MHz using the material parameters summarized in Table B1. We assume flatband conditions at both back and front contacts. The trap levels drawn in Figure 1 and their corresponding charge state were not considered in the simulation. Illuminated solar cells are simulated with a 1-sun AM1.5G spectrum and absorption files for CdS and ZnO available in SCAPS, and assuming an absorption constant A = 10 5 cm −1 eV 0.5 for CIGS.

MAXIMUM STEP HEIGHT
Calculating the maximum step height from Equation (4) requires knowledge of the correct dopant concentration. By substituting where η t and η F are the trap and Fermi energies E t and E F , respectively, normalized by kT. This step height λ is largest for that Fermi level, which maximizes the argument [η t − η F − 1]exp(η F ) in the second square-root. Taking the derivative with respect to η F this is fulfilled if or, because exp(η F ) is always non-zero, η F = η t − 2. The capacitance step for a sample with constant dopant concentration and majority trap level E t is thus largest if the Fermi level is 2kT below the trap level.
Evaluating Equation (C1) at this Fermi level then results in Equation (5).