Application of metal, metal‐oxide, and silicon‐oxide based intermediate reflective layers for current matching in autonomous high‐voltage multijunction photovoltaic devices

A logical next step for achieving a cost price reduction per Watt peak of photovoltaics (PV) is multijunction PV devices. In two‐terminal multijunction PV devices, the photo‐current generated in each subcell should be matched. Intermediate reflective layers (IRLs) are widely employed in multijunction devices to increase reflection at the interface between subcells to enhance current generation in the subcell(s) positioned before the IRL, in reference to the incident light. In this work, the results of over 65 multijunction devices are presented, in order to explore the effect of different current matching approaches. The influence of variations in absorber thickness as well as thickness variations of different IRLs based on silicon‐oxide, various transparent conductive oxides (TCO), and metallic layers on all‐silicon multijunction PV devices is studied. Specifically, hybrid, 2‐terminal, monolithically integrated silicon heterojunction (SHJ) and thin film nanocrystalline silicon (nc‐Si:H) and amorphous silicon (a‐Si:H) tandem and triple junction devices are processed. Based on these experiments, certain design rules for optimal current matching operation in multijunction devices are formulated. Finally, taking these design rules into account, record all‐silicon multijunction devices are processed. Conversion efficiencies close 15% and Voc≈2  V are demonstrated for triple junction SHJ/nc‐Si:H/a‐Si:H devices. Such conversion efficiencies for a wireless, high‐voltage wafer‐based all‐silicon 2‐terminal multijunction PV device opens the way for efficient autonomous solar‐to‐fuel synthesis systems as well as other wireless innovative approaches in which the multijunction solar cell is used not only as a photovoltaic current‐voltage generator, but also as an ion‐exchange membrane, electrochemical catalysts, and/or optical transmittance filter.


| INTRODUCTION
Multijunction photovoltaic (PV) devices have the potential to enhance spectral utilization, thereby achieving increased PV yield per area as well as reduced heating and lower temperature coefficients. Additionally, multijunction PV devices can achieve high voltages without interconnection, facilitating autonomous solar-to-fuel applications.
Photo-generation of charge carriers occurs in each subcell in multijunction devices. For optimal operation, in two-terminal devices, the photo-current generated in each subcell should be matched. In multijunction devices, generally, the bottom cell is not current limiting as a reflective metallic layer can be positioned at the back of the devices.  5,7,9,13 Generally an n-type (n-) SiO x layer is used. 14 The properties of n-SiO x layers are more easily adjusted to achieve characteristics desirable for an IRL, in reference to p-SiO x properties, as the device performance is very sensitive to p-SiO x characteristics like the oxide fraction and layer thickness. 15 In this work, in addition to silicon-oxide and TCO based IRLs, the use of a very thin metallic layer is explored.
In order to characterize the performance of the different IRLs, allsilicon multijunction PV devices are used. Specifically, a hybrid c-Si and thin film Si multijunction device is used, consisting of a silicon heterojunction (SHJ) subcell and one or two additional thin film silicon subcells based on nc-Si:H and a-Si:H absorbers. The advantage of these plasma enhanced chemical vapor deposition (PECVD) processed, 2-terminal, monolithically integrated devices, is that a V oc ≈ 2 V can be achieved without external wiring. Given the inherent chemical stability of silicon in reference to other PV technologies, 16 this allows for wireless, autonomous solar-to-fuel synthesis systems, [17][18][19][20] and other wireless innovative approaches in which the multijunction solar cell is used not only as a photovoltaic currentvoltage generator, but also as an ion-exchange membrane, 21,22 electrochemical catalysts, and/or optical transmittance filter. 23 First, in Section 3.1, the influence of the nc-Si:H absorber thickness on 1J, SHJ/nc-Si:H (2J), and SHJ/nc-SI:H/a-Si:H (3J) device is characterized.
In the following three sections, the influence of an IRL based on SiO x , TCO, and silver (Ag) is characterized. Using the design rules obtained from these characterization, a champion autonomous high-voltage 2J and 3J device is processed, which is presented in Section 3.5.

| EXPERIMENTAL SECTION
In this work, a number of tandem PV devices are presented, consisting of a wafer-based silicon heterojunction subcell and a thin film silicon subcell with a nc-Si:H absorber. For the 3J devices an additional thin film silicon junction was processed with an a-Si:H absorber. Scanning electron microscope (SEM) images as well as a simplified schematic structure of the triple junction device are presented in Figure 1. All hydrogenated silicon(oxide) layers, doped and undoped, are processed using plasma enhanced chemical vapor deposition (PECVD). The exact configuration and deposition conditions of the PECVD processed layers, with exception of the p-layers, are reported in de Vrijer et al. 15 For the p-layers, a bi-layer configuration was used, consisting of a 12 nm p-nc-SiO X :H and a more highly doped 4 nm p-nc-SiO X :H + layer. The deposition conditions of these layers are reported in Table 1. Additionally, metals and TCOs are used at the front and back of the devices, as shown in Figure 1, as well as a material for the IRL in Sections 3.3 and 3.4. All TCOs are processed through RF magnetron sputtering. More information about the processing equipment and conditions of indium-oxide doped with tin (ITO) and tungsten F I G U R E 1 Schematic structure and SEM images of a typical SHJ/nc-Si:H/a-Si:H triple junction device presented in this work. The colors in the schematic structure, as well as those added to the left half of the SEM images, represent different materials, as indicated by the top-right legend. The position of the IRL, as well as the different materials used for the IRL, are indicated on the right of the schematic (IWO) can be found in Han et al, 24 while the sputtering conditions of AZO can be found in de Vrijer et al. 2 Aluminum contacts are processed using electron beam evaporation, while the Ag layers are evaporated using resistive heating.
The 300 μ m thick n-type mono-crystalline silicon wafers with <100> orientation are used for processing the SHJ devices. The wafers are textured using an approach consisting of alkaline etching step followed by an acidic etching step. Both the texturing approach 15 and the optical behavior of the textured surface 25 15 The V oc , FF, J sc , R s , R sh , and conversion efficiency (η) of all cells presented in this work can be found in the supporting information.
Finally, the reflectance measurements were performed using a LAMBDA 1050+ Spectrophotometer from PerkinElmer.  Qualitatively, the collective trends in Figure 2 suggest some design trends for the multijunction devices as a function of d nc-Si .
Most of the gains in J sc are realized in the d nc-Si ≤ 3μ m range, while for d nc-Si > 4μ m the gain in J sc is minimal. Consequently, considering the V oc *FF trend of the 1J device, d nc-Si should be kept ≤ 4μ m and preferably even ≤ 3μ m. Additionally, intentionally introducing a (small) current mismatch in which the junction with the highest FF is limiting can, in reference to a current matched design, positively affect overall device performance.
Quantitatively, the trade-off between voltage and current as a function of d nc-Si can also be expressed. In Table 2

| SiOx:H based intermediate reflective layer
In the preceding section the attractiveness of an intermediate reflec- tive layer, which could potentially yield an increase in J sc without a (significant) decrease in V oc *FF, is demonstrated. In this section the effectiveness of an silicon-oxide based IRL is investigated.
In Figure 3B, the J sc of the nc-Si:H junctions are shown to increase with increasing d n-SiOx , for both the 2J and 3J series, while the J sc of the SHJ decreases. The EQE curves of the 2J and 3J series, in Figure 3D d n-SiOx . Note that the green and blue curves in Figure 3E largely overlap. This absorption shift is in line with earlier reports. 5,7,9,13 Interpretation of the V oc *FF, in Figure 3A, is less straightforward.
The n-nc-SiO x :H layer is not exclusively an IRL, but also the n-layer in both an n-i-p subcell and p-n tunnel recombination junction. Notably, the initial V oc *FF increase for d n-SiOx ≤ 30 nm is consis- An additional observation can be made regarding the J sc 's of the devices presented in Figure 3B. The J sc-sum of the 3J devices is about 3mA Á cm À2 lower with respect to the 2J devices. This same difference is observed in the multijunction devices with different d ncSi and IRLs. Reflectance measurements presented Figure 3C, in which the front reflection of 2J and 3J devices is plotted as a function of d n-SiOx , show that this J sc loss is mainly an optical effect. With the introduction of the a-Si:H junction, given the typical layer thicknesses and the fact that no optimization has been performed regarding front-side anti-reflection, strong interference effects occur. these interference effect lead to the observed J sc-sum loss in the 3J devices in reference to the 2J devices.

| TCO based intermediate reflective layer
Next, the use of a TCO as an IRL is investigated. If we consider with a collection barrier introduced by a poorly performing TRJ. 15 3. An electrical barrier against charge carrier collection is consistent with the deterioration of the electrical device characteristics observed in Figure 4A with TCO introduction. This V oc *FF decrease is predominantly the result of a strong decrease of the R sh with increasing d TCO . Figure 4D shows that the R sh decreased irrespective of whether ITO, room temperature IWO or AZO was used. Moreover, the low R sh persists even when shunting paths at the edges of the substrate were eliminated, through additional masking steps or by physically isolating the cell from the edges by cutting the wafer.
As the use of a TCO does not result in the desired transfer of current transfer between subcells, and the V oc *FF deteriorates when a TCO is introduced, the use of a TCO as an IRL in these monolithically integrated silicon-based multijunction devices does not appear to be a desirable option.

| Silver based intermediate reflective layer
Finally, the use of a thin metallic layer as an IRL is considered. Ag is used for its favorable reflective and conductive properties. From  Figure 5C shows that this is a result of an overall decrease of the EQE of the SHJ with d Ag .
Both these effects are related to the Ag growth. At the low intended thicknesses considered in this section, the Ag does not result in the formation of a uniform layer. Rather, Ag clusters are formed as can be observed in the SEM images in Figure 6. As a consequence, the reported thickness in this section are intended thicknesses. The factual average diameter (D), and standard deviation, of these clusters are indicated in Figure 6. As a consequence of the size and shape of the Ag nanoparticles, plasmonic resonance occurs. The SEM images in For one, the plasmon resonance, so the position of maximum attenuation, is shifted to higher wavelengths with increasing D. [29][30][31] This red-shift reportedly also occurs for increasingly ellipsoidally shaped Ag nanoparticles. 32,33 The absorption peak in the EQE plot of the nc-Si:H subcell in Figure 5C is observed to red-shift with increasing d Ag . The 1-R inset shows that the shift of the EQE peak directly corresponds to a shift of reflection with d Ag .
Additionally, considering the overall quantum efficiency decrease of the SHJ with d Ag . A similar decrease has been observed before in the long-wavelength range for cells containing small nanoparticles. 34 The decrease can be attributed to reflection changes only to a small extent, as can be observed in Figure 5C. However, in the 750-950 nm wavelength range, 1-R values are roughly similar, while the quantum efficiency for devices with d Ag ≥ 2 nm is significantly reduced. The decrease therefore is a result of either increased parasitic absorption, or decreased collection efficiency as a function of increasing d Ag .
Most likely both effects have an influence on the observed device performance. It is widely reported that the scattering cross section in reference to the absorption cross section of the Ag nanoparticles increases with increasing D. 30,31,33,35 A strong decrease of the optical transparency can also be observed for the thin Ag films on glass in Figure 6. Given these reports and the average particle size shown in Figure 6, the nanoparticles will cause significant parasitic absorption in our devices. A decrease of the collection efficiency, on the other hand, is also likely considering both the strong decrease of the V oc *FF in the d Ag ¼ 4-8 nm range as well as earlier reports of a FF decreases in thin films silicon devices with increasing Ag nanoparticle size. 31,33 The mechanism through which the larger nanoparticles introduce the   Figure 7 show that the photogenerated current density is not evenly distributed among the different junctions. Additionally, a large optical loss in the blue part of the spectrum in the 300-500 nm wavelength region. The 1-R curve, and the difference between the EQE sum curve and the 1-R curve, indicates this to be a result of both relatively high front reflection as well as parasitic absorption losses, presumably in the front TCO and p-doped window layer. Further optimization of these layers in combination with the use of an anti-reflection coating, as well as improved current matching, could yield a current limiting J sc in the range of 11-12 mAÁcm À2 . Therefore, with further optimization, a hybrid allsilicon SHJ/nc-Si:H/a-Si:H 3J device with V oc > 2 V and η > 18% could realistically be achieved. Additionally, it was observed that the FF is strongly influenced by the current matching conditions. For optimal device performance, it would be advisable to intentionally introduce a minor current mismatch in which the junction with the highest FF is current limiting.
Finally, taking these design rules into account, champion devices were processed. For the triple junction SHJ/nc-Si:H/a-Si:H device a V oc ≈ 2 V and η ≈ 15% are reported, which to the best of the author's knowledge is a record for an all-silicon multijunction device. Such a conversion efficiency for a high-voltage wafer-based all-silicon 2-terminal multijunction PV device opens the way for highly efficient autonomous solar-to-fuel synthesis systems.