Post-deposition annealing and interfacial atomic layer deposition buffer layers of Sb 2 Se 3 /CdS stacks for reduced interface recombination and increased open-circuit voltages

Currently, Sb 2 Se 3 thin films receive considerable research interest as a solar cell absorber material. When completed into a device stack, the major bottleneck for further device improvement is the open-circuit voltage, which is the focus of the work presented here. Polycrystalline thin-film Sb 2 Se 3 absorbers and solar cells are prepared in substrate configuration and the dominant recombination path is studied using photoluminescence spectroscopy and temperature-dependent current – voltage characteristics. It is found that a post-deposition annealing after the CdS buffer layer deposition can effectively remove interface recombination since the activation energy of the dominant recombination path becomes equal to the bandgap of the Sb 2 Se 3 absorber. The increased activation energy is accompanied by an increased photoluminescence yield, that is, reduced non-radiative recombination. Finished Sb 2 Se 3 solar cell devices reach open-circuit voltages as high as 485 mV. Contrarily, the short-circuit current density of these devices is limiting the efficiency after the post-deposition annealing. It is shown that atomic layer-deposited intermediate buffer layers such as TiO 2 or Sb 2 S 3 can pave the way for overcoming this limitation.


| INTRODUCTION
Thin-film photovoltaic technologies offer great opportunities for electrical power generation, such as light weight and flexible modules, low energy payback time, and a low CO 2 equivalent footprint [1,2].Sb 2 Se 3 contains only abundant and low-toxic elements, can be used as an absorber layer, and recently received considerable attention as a photovoltaic material used both in superstrate and substrate device design configurations.The bandgap can be engineered from 0.9 to 1.7 eV using Bi [3] and S [4] alloying and thus is ideally suited for single-junction [5] and tandem-junction [6,7] solar cells.Recently, recorded efficiencies of 9.2% for Sb 2 Se 3 [8] and 10.5% for Sb 2 (Se,S) 3 [9] solar cells have been achieved.As pointed out by Chen and Tang, the open-circuit voltage is currently limiting device performance [10].
Figure 1 depicts the status of Sb 2 Se 3 -based solar cells, that is, without the addition of S, for substrate and superstrate architectures, which are briefly reviewed in the following.The underlying data are listed in Table 1.The efficiency for superstrate devices shows a clear correlation with the open-circuit voltage (Figure 1A) due to good charge carrier collection (Figure 1B), that is, short-circuit current densities above 25 mAcm À2 .In contrast, the short-circuit current densities are rather low ( ~< 25 mAcm À2 ) for substrate devices, even though this architecture yields the highest open-circuit voltages.The fill factors are similar for both types (Figure 1C).Considering both, V OC and J SC , recent improvements in efficiency are rather driven by increasing J SC (Figure 1D).In fact, the highest efficiencies are obtained in substrate configuration for rough micro-rod absorber morphologies [8,55,57], which facilitates charge-carrier extraction; however, it imposes additional non-radiative recombination losses due to an increased junction surface area.For superstrate devices, the highest J SC values (>31 mAcm À2 ) are obtained using a TiO 2 buffer layer [11,24,31].However, J SC values above 30 mAcm À2 are also achieved using a CdS buffer layer [27,43].In fact, mostly a CdS buffer layer is applied for superstrate devices (presented in Figure 1), which however is generally treated prior to the growth of the Sb 2 Se 3 absorber layer, for instance by an oxygen plasma [13,43] or a H 2 O 2 and CdCl 2 treatment followed by an annealing at 400 C for 5 min [27].A CdS buffer layer is also applied for the high J SC devices in substrate configuration [8,57], and thus, it seems that the (CdS) buffer does not impose a limitation for the J SC .
Here, the voltage limitation for Sb 2 Se 3 in substrate configuration is studied.Open-circuit losses can severely be influenced by the quality of the Sb 2 Se 3 front interface.In this work, we use two approaches to improve the Sb 2 Se 3 front interface: a) post-deposition annealing and b) ultrathin interfacial layers by atomic layer deposition (ALD).
Recently, a post-deposition annealing after the buffer layer deposition led to a record open-circuit voltage of 506 mV [52].We show that such a post-deposition annealing can effectively improve the interface as well as the bulk material quality of the Sb 2 Se 3 /CdS stack.While previous studies in superstrate configuration pointed out that CdS is not suitable as a buffer layer, it is shown here that in substrate configuration, the Sb 2 Se 3 /CdS interface does not impose a major problem such as a pinned Fermi level or a conduction band cliff.Sb 2 Se 3 /CdS stacks as well as finished solar cell devices post-deposition annealed in air prepared in this study reached open-circuit voltages as high as 485 mV and thus demonstrate the validity and effectiveness of such a treatment.In addition, we investigate the use of amorphous interfacial TiO 2 and Sb 2 S 3 buffer layers, to improve the interface quality.ALD provides conformal coatings of uniform and continuous layers over nanostructured surfaces.In previous works, it has been demonstrated that the use of ultrathin interfacial layers via ALD in Sb 2 S 3 and Sb 2 Se 3 devices reduces interface recombination [8,58,59].As will be shown F I G U R E 1 IV parameters extracted from reported Sb 2 Se 3 -based solar cells (see Table 1  (Continues) here, the introduction of these ultrathin layers in the Sb 2 Se 3 /CdS interface results in an enhancement of all the photovoltaic parameters.

| EXPERIMENTAL
The experimental procedure for the fabrication and characterization of Sb 2 Se 3 absorbers and solar cells is depicted in Figure 2  For some samples, intermediate thin films of TiO 2 or Sb 2 S 3 are grown using ALD prior to the CdS buffer layer deposition.Absorber layers for this experiment are selenized at 320 C (see Figure S1 for the temperature profile) and no post-deposition annealing was applied.
The interfacial ALD TiO 2 layer is deposited using an Arradiance GEMStar XT benchtop reactor.The precursors utilized are titanium From these measurements, the light entering the solar cell is calculated as 1 À R and governs the maximal achievable EQE.iv.The efficiency decreases as a result of a decreasing J SC with increasing post-deposition annealing temperature.In order to assess the diode quality, that is, the recombination current, the JV curves were fitted using the iv-fit routine [63].The voltage dependent current density J V ð Þ is fitted to a one-diode model, including a series, r s , and a shunt, R sh , resistance, according to In Equation 1, J 0 is the saturation current density, A is the diode ideality factor, k B is the Boltzmann constant, T is the temperature during the acquisition of the JV curve, and J ph is the photo-generated current density.Figure S3b shows the experimental data and the corresponding fits for the best devices of each post-deposition annealing.Evidently, the saturation current density J 0 is characteristic for the quality of the diode (see for instance sect.2.4.5 in Scheer and Schock [64]) and directly influences R sh here).Figure 3F shows the fitted values for J 0 and demonstrates a decrease by roughly two orders of magnitude for the device with the highest annealing temperature compared to the reference devices.
The smaller value of J 0 clearly indicates an improved quality of the diode and thus a reduced recombination current.The parameters for the device with the highest V OC (annealed at 300 C) are V OC ¼ 485 mV, J SC ¼ 12:0 mAcm À2 , FF = 39.5% resulting in an efficiency of 2.3%.
Mainly due to the decreasing J SC with annealing temperature, the overall efficiency of the devices is reduced.Parasitic resistances can already induce a J SC reduced by a factor of 1= 1 þ r S =R sh ð Þfrom J ph (see Supporting information).However, for the devices presented here, this effect has only a minor influence (Figure S4).In order to assess the decrease of J SC , Figure 4 shows measurements of the EQE.Optical losses due to reflection are indicated by the quantity to the application of a reverse bias, the space-charge region enlarges and consequently the collection of carriers, which are generated deeper in the Sb 2 Se 3 absorber layer.In contrast, the samples post-deposition annealed at 250 C and 300 C show a strongly reduced EQE over the whole wavelength range.The plot of A similar behavior of an increasing V OC with respect to postdeposition annealing is observed on a complete solar cell (Figure 5).In In summary, we observe an increase in V OC independently of whether we heat Sb2Se3/CdS or the whole stack, and no noticeable change in band gap is observed.To investigate the voltage change further, we use PL.An increase of the quasi Fermi level splitting Δμ can be estimated from an increased PL yield according to [69] Δμ

| Photoluminescence analysis
For

| Dominant recombination path
The saturation current density in Equation ( 1) dictates the onset of the diode current and can be written as [64] J with J 00 as the reference saturation current density and E A as the activation energy of the dominant recombination path.For dominating recombination in the space-charge region or in the quasi-neutral region, an activation energy equal to the bulk bandgap is expected.
However, an activation energy below the bulk bandgap indicates dominating interface recombination, which can be caused by a pinned Fermi level, a cliff-like band alignment [39] or a defect layer near the interface [71].
From Equations ( 1) and ( 3), the temperature-dependent opencircuit voltage reads as where q is the elemental charge.Extrapolation of V OC T ð Þ to 0 K yields the activation energy of the dominant recombination path E A .
Figure 7 shows V OC T ð Þ data for the 250 C post-deposition annealed (blue circles) and its as-grown reference sample (red circles).The activation energy of J 0 is determined according to Equation ( 4) and gives E A,ref ¼ 1:18 AE 0:02 eV and E A,250C ¼ 1:27 AE 0:01 eV, that is, E A increases by 90 meV after post-deposition annealing.This increase of E A matches the increase of the V OC at room temperature (300 K), which is roughly 80 mV higher for the post-deposition annealed sample at 250 C (see also Figure 3).Thus, after post-deposition annealing, the activation energy shifts towards the bulk bandgap value (itself unchanged by post-deposition annealing) as deduced from IQE measurements (Figure S5a) and indicates an improved interface quality.
The 300 C post-deposition annealed sample behaves as the 250 C one (Figure S7) and is omitted for clarity.
Also, the improved V OC for successive post-deposition annealings of a completed solar cell device (Figure 5) are well explained by an increased activation energy of J 0 .The as-finished device has a V OC of only 298 mV (at 300 K) with an activation energy of E A,init ¼ 0:67 eV, which is well below the bandgap, indicating (near) interface recombination as the main path.However, the device after the final postdeposition annealing step at 300 C shows an activation energy of E A,fin ¼ 1:22 eV, which is close to the bandgap of Sb 2 Se 3 and explains the improved V OC .The bandgap does not change upon the successive post-deposition annealings on the finished device (Figure S5b).

| Laser annealing
The devices presented in the previous sections were obtained by post-deposition annealing of the Sb 2 Se 3 /CdS on a hot plate, which involves heating the glass substrate and all the layers simultaneously, which is energetically expensive.Previously, it has been demonstrated that laser annealing may be used to improve semiconductor quality without significantly heating the substrate [72].Here, we investigate whether increasing the laser power by a factor 10 during the PL measurements is sufficiently heating and simultaneously enables the measurement of the PL yield in situ.The laser spot is focused on a single point of the sample, and therefore, an exact temperature measurement is not possible.an infrared camera, only an increase in the temperature is measured.With continuous laser irradiation, PL spectra are acquired every few seconds, and the integrated PL yield is calculated by integration over the whole spectrum and is plotted in  Sb, Se, Cd, and S but rather the consequence of the surface roughness that decreases the depth resolution of SIMS measurements.Indeed, as will be shown below, STEM-EDX measurements indicate the absence of elemental inter-diffusion.
It needs to be stressed that in superstrate configuration, the Sb 2 Se 3 absorber is directly deposited onto the CdS buffer layer at higher temperatures than we used here to do the post-deposition annealing [19,73], which likely leads to the formation of a CdSe layer for these growth conditions.
We observe a strong increase in alkali elements upon postdeposition annealing (Figure 9B) with highest counts at the Sb 2 Se 3 / CdS interface.The increase of the alkali elements might originate from the SLG glass substrate.Another source of alkalis could be the KCN etch, which is carried out prior to the CdS deposition.However, the reference and 250 C post-deposition annealed sample received the same KCN etch and CdS deposition.Thus, we do not believe that residuals of these processes cause the increased alkali elements.
These alkalis could alter the interface properties, as for instance observed in Cu (In,Ga)Se 2 /CdS structures [74].It remains to be investigated how these alkalis influence the interface recombination at the Sb 2 Se 3 /CdS interface, although alkali compounds such as NaSbS 2 are known to exist [75].Interestingly, an increase of Na at the Cu (In,Ga) Se 2 /In 2 S 3 heterointerface is also observed after post-deposition temperatures between 225 C and 275 C, where it is speculated that Na passivates defects [76].The oxygen at the interface Sb 2 Se 3 /CdS interface did not notably change upon post-deposition annealing in air (Figure S9b), which indicates that a SbO 3 phase does not form.
In order to investigate the Sb 2 Se 3 /CdS interface more in detail, STEM-EDX and HRTEM measurements are carried out.Figure 10A shows a high-angle annular dark field (HAADF) cross section and

| ALD interfacial layers
As demonstrated in Figure 1 and from our own results here, interface recombination can impose a major bottleneck for the V OC .Thus, to try to avoid this interface recombination, various interfacial ALD buffer layers are deposited between the Sb 2 Se 3 /CdS interface.It is reported that TiO 2 buffer layers improve device efficiency in substrate [8] and superstrate [19] configurations.However, until now, no reports exist of a Sb 2 S 3 buffer layer on a Sb 2 Se 3 absorber.Figure 11A shows illuminated and dark IV characteristics of the reference device, as well as In the case of Sb 2 Se 3 -based solar cells, the activation energy of J 0 is generally reported below the bandgap independent of the device architecture (substrate or superstrate) and for different buffer and back contact layers [18, 21, 29, 45, 48-50, 53, 55].An exception is reported in Cheng et al. [39], where an organic molecule is deposited between the window and the absorber layer.These activation energies point to dominating interface recombination due to a pinned Fermi level or a cliff-like band alignment [77].Recently, substrate Sb 2 Se 3 /CdS devices are fabricated with opencircuit voltages above 500 meV [52].These devices received a postdeposition annealing at 300 C for 5 min after the CdS buffer layer deposition.The origin for the higher V OC might be the improved activation energy of J 0 and the accompanied reduced interface recombination, as demonstrated here.
Similar to the devices with a post-deposition annealing, also an interfacial ALD buffer layer improves the interface quality as evidenced by an increased activation energy of J 0 (Figure S8), which in turn results in higher V OC values (Figure 11C).The increased activation energy of J 0 indicates that the improvement of V OC might be associated to reduction of detrimental recombination paths at the pnjunction by the interfacial layers.However, there is an additional beneficial effect of the interfacial layers since the photocurrent of the devices experience a drastic increase (Figure 11D) and is discussed in the section below.
In conclusion, as interface recombination constitutes a major recombination channel in substrate Sb 2 Se 3 /CdS-based solar cells, the front surface area should be minimized to maximize V OC .Yet the short-circuit current density J SC decreases after postdeposition annealing.While this phenomenon is not fully understood, several scenarios can be ruled out.

| Photo current losses and gains
• SIMS profiling and TEM analysis did not detect a measurable depth profile differences for Sb, Se, Cd, and S between the reference device and the device annealed at 250 C (Figure 9 and Figure 10), unlike reported in [19].In addition, from temperaturedependent JV characteristics, no blocking of the photocurrent is observed for temperatures as low as 40 K (Figure S12).Thus, even if a CdSe layer forms after post-deposition annealing, which cannot be resolved by SIMS or TEM, this layer does not act as a barrier for the photocurrent and thus cannot explain the reduced J SC .
• Williams et al. observed a void formation in close-spaced sublimated Sb 2 Se 3 films at the Sb 2 Se 3 /CdS interface and assigned those voids to a loss in J SC [73].However, no voids were observed within the resolution limit of neither the SEM (Figure S14) nor the TEM (Figure S11).
Figure 4B shows that photo-current losses are stronger for longer wavelengths.Thus, it might be possible that the post-deposition annealing reduces the collection efficiency of photo-generated charge carriers.Simulations shown in Figure S19 show that a reduced electron mobility can have a strong effect on J SC , where losses are strongest for long wavelengths.It was found previously that photo-carrier collection can depend on the grain orientation [25].However, only a minor change in grain orientation is observed by X-ray powder diffraction (XRD) measurements (Figure S13).It is possible though that the bulk mobility changed independent of the grain orientation and thus results in a decreased photo-current extraction.
Another way to have a reduced J SC , as shown in Figure S20, is to introduce a single acceptor-like defect at the Sb 2 Se 3 /CdS interface with varying distances to the Sb 2 Se 3 valence band.The defect adds a considerable negative charge at the Sb 2 Se 3 /CdS interface and therefore strongly influences the band bending in the Sb 2 Se 3 absorber layer.With defect energies closer to the Sb 2 Se 3 valence band, recombination is reduced while collection is impeded at the same time.Thus, the model of an acceptor like interface defect close to the valence band can explain at the same time increased V OC s and reduced J SC s.It is thus possible that the same defect, in that case a reduction in density, is responsible for the increased J SC after surface modifications due to the ALD buffer layer deposition.
Ultrathin Sb 2 S 3 and TiO 2 interfacial layer deposited via ALD at the Sb 2 Se 3 /CdS interface improves considerably the J SC of the devices (Figure 11D).EQE measurements demonstrate an improved charge carrier collection efficiency through the whole wavelength range (Figure 11B).The J SC values obtained by introducing Sb 2 S 3 and TiO 2 interfacial layers are already close to the best J SC values reported literature for planar devices in substrate configuration (Figure 1).
The origin of the increase in photocarrier collection is currently still under investigation.Similar to the devices with a post-deposition annealing, modifications (here a reduction) of a spike-like conduction band offset, and thus a reduced barrier for photo carriers, can be ruled out.This is supported by Figure S12, which shows that the photo current has no strong temperature dependence.
Values of J SC around 30 mAcm À2 or higher are only obtained for nano-ribbon Sb 2 Se 3 /CdS core-shell structures [8,55,57].From the TEM analysis of the Sb 2 Se 3 /Sb 2 S 3 /CdS stack, that is, a Sb 2 S 3 interfacial ALD layer, it is observed that CdS intrudes into pinholes and voids at the back contact (Figure S11).Thus, it is likely that the ALD layers passivate these surfaces similarly as the front surface [8,58,59].The improved J SC can then be explained by increased charge-carrier collection via an increased front interface area similar as in the core-shell structures.However, as pointed out in Section 3.4, the front surface constitutes a major recombination channel and thus questions the approach of core-shell structures.Ideally, with improving minority carrier lifetimes, that is, improving the bulk quality of the Sb 2 Se 3 absorber, also the carrier collection length increases.Thus, J SC will improve simultaneously, without the need of a large front surface area.

| CONCLUSIONS
The In contrast to the post-deposition annealing, these ALD interfacial layers improve J SC for our substrate devices and might pave the way to overcome the limitations observed in this study and thus for higher efficiencies in the future.
Importantly, as interface recombination acts as the major recombination channel in Sb 2 Se 3 -based substrate solar cells, the front interface area needs to be minimized, and planar structures are the preferred architecture.Once the bulk Sb 2 Se 3 properties are improved to yield a higher minority carrier lifetime, the photo current will improve naturally due to an increased diffusion length.
) in superstrate (full symbols) and substrate (open symbols) architecture.Data points from solar cells from the current study are added as open red symbols.ALD, atomic layer deposition.T A B L E 1 IV parameters for substrate and superstrate Sb 2 Se 3 devices from literature Figure S1.Prior to the deposition of the CdS buffer layer, the absorbers were etched in 5 wt.%KCN for 30 s, which generally improves the open-circuit voltage of the final device (FigureS2a).This improvement is likely due to the removal of oxide species, similar to other selenide semiconductors[60].A CdS buffer layer is deposited on top of the absorber layer by means of chemical bath deposition (CBD) at 67 C adapted from Contreras et al.[61].The thickness of the CdS layer is approximately 80 nm and was achieved by two subsequent CdS processes.The thicker CdS layers generally lead to a higher open-circuit voltage (FigureS2b).The window layer consists of a sputtered ZnO double layer, with 80-nm ZnO and 380-nm ZnO:Al.Ni/Al dotcontacts are deposited by e-beam evaporation.Individual solar cells are scribed mechanically with areas of 0.2 cm 2 .Post-deposition annealing of Sb 2 Se 3 absorbers is performed on a hotplate in air, either after CdS deposition or on full devices.The annealing temperatures range between 100 C and 300 C and the annealing time is fixed to 5 min.

For 3 |
photoluminescence (PL) measurements, a red diode laser with a wavelength of 660 nm is focused onto the CdS covered Sb 2 Se 3 absorber layer.In this study, two different laser powers are used to acquire the PL spectra: (i) 10 mW, which induces only minor heating of the sample and yields a rather constant PL yield over time; and (ii) 100 mW, which induces a significant amount of heating and results in an increasing PL yield over time.If not stated otherwise, the PL spectra shown in this manuscript are recorded with a laser power of 10 mW.The determination of the exact excitation density is not possible in this study due to the need of using a lens to focus the laser beam and a collection spot larger than the excitation spot.The PL flux from the sample is collected by two off-axis parabolic mirrors and directed into a spectrometer via an optical fiber with a diameter of 550 μm.The PL flux is subsequently dispersed in the spectrometer and measured by a 512-element (In,Ga)As array.Spectral correction is carried out by measuring a reference white-light lamp at the sample position, that is, using the same collection path as for the PL measurements.Current density-voltage (JV) characteristics are measured using a class AAA sun simulator in four-probe configuration under standard test conditions.A Si reference cell is used for intensity calibration.The external quantum efficiency (EQE) is measured by lock-in amplification using a halogen and xenon lamp as a light source.The light is focused on a spot without grid shading.A Si and InGaAs reference diode are used for calibration.From the EQE, the internal quantum efficiency (IQE) is calculated as IQE ¼ EQE= 1 À R ð Þ. Temperature-dependent current-voltage characteristics are recorded in a closed cycle He cryostat with a halogen lamp as a light F I G U R E 2 Experimental procedure for the growth of Sb 2 Se 3based absorbers and solar cells.PVD stands for physical vapor deposition, CBD for chemical bath deposition, and ALD for atomic layer deposition.source.The distance of the lamp to the sample is adjusted to match the same short-circuit current density as measured under the sun simulator.A temperature sensor is glued on a soda lime glass substrate next to the sample under test to estimate the temperature of the absorber.RESULTS AND DISCUSSION 3.1 | Device analysis The impact of the post-deposition annealing temperature of the Sb 2 Se 3 /CdS stack on the final finished solar cell devices is analyzed by their JV characteristics in the dark and under illumination.The corresponding device parameters are shown in Figure 3A-D.The following trends can be observed.i.The open-circuit voltage is rather constant for annealing temperatures up to 200 C, where only a small drop at 150 C observed.However, for post-deposition annealing temperatures of 250 C and above, a clear increase in the V OC is observed.These devices will be subject to a more detailed investigation as shown in the following.It is noted that the bandgap does not change (Figure S5a).This is an important finding as it demonstrates that the V OC increases due to a reduction of non-radiative recombination and not due to an increase of the absorbers bandgap.A possible reason for a change in bandgap might be diffusion of S from the CdS buffer layer into the Sb 2 Se 3 absorber layer, which then might form Sb 2 (S,Se) 3 with a bandgap larger than Sb 2 Se 3 .It will be shown in Section 3.5 that no elemental intermixing is observed at the Sb 2 Se 3 /CdS interface.ii.The short-circuit current density decreases with increasing postdeposition annealing temperature.The highest values are obtained for the reference devices and the device annealed at 100 C. iii.The fill factor remains rather constant independent of the postdeposition annealing temperature.F I G U R E 3 (A-D) Device parameters for solar cells processed with varying post-deposition annealing temperatures after the CdS buffer layer deposition.(E) Best JV curves.(F) Saturation current density J 0 fitted using the one-diode model (Equation 1).

Figure
Figure 3E shows the best JV characteristics.The dark JV characteristics shift towards higher voltages with increasing post-deposition annealing temperature and indicate an improved material quality due to a smaller recombination current.The dark curves also show no significant influence of shunting, as indicated by the flat diode current around 0 V. Fitted values of the shunt resistance yield values in the order of 10 kΩcm 2 as shown in Figure S3a.In contrast, the illuminated curves show a significant positive slope around 0 bias, which indicates voltage dependent carrier collection or an illumination induced shunt path.In order to assess the diode quality, that is, the indicates an improved collection at reverse bias over the whole wavelength range ( ≈ 10% and ≈ 25% for the 250 C and 300 C post-deposition annealed sample, respectively).It is noted that the bandgap is not influenced by the post-deposition annealing and yields values around 1.25 eV as determined from the IQE (Figure S5a), within the range of bandgaps observed elsewhere (1.18 eV [65] to 1.26 eV [53]).Figure 4B shows the ratio of the IQEs of the post-deposition annealed samples and the reference sample.The decrease towards higher wavelength shows that the devices with a post-deposition annealing show a deteriorated F I G U R E 4 External quantum efficiency (EQE, solid lines) and reflectance losses (1-R, dash-dotted lines) versus the photon wavelength on the left ordinate.Good collection is achieved in the reference sample around 600 nm and decreased towards longer wavelength.Post-deposition annealed samples at 250 C and 300 C show a decreased EQE.(A) The ratio of the EQE recorded at À0.2-V bias and at 0-V bias is shown on the right ordinate.(B) The ratio of the IQE after post-deposition annealing and the reference IQE.The sample with post-deposition annealing show a worse collection over the whole wavelength range, in particular for longer wavelengths.collection, in particular at longer wavelengths.Such an observation indicates that the collection length decreases upon post-deposition annealing.
that case, the post-deposition annealing procedure was carried out successively on a completed solar cell device.Clearly, an increasing open-circuit voltage is observed with successive post-deposition annealing with increasing temperature.The bandgap of the Sb 2 Se 3 does not change as shown in Figure 5B.Interestingly, J SC peaks at a post-deposition annealing temperature of 250 C and drops for a higher successive annealing temperature.The origin of this behavior is currently not understood.
Photoluminescence spectroscopy is used to assess the Sb 2 Se 3 absorber layer quality in the absence of window layers, which potentially can introduce additional recombination channels.A higher PL yield is expected for reduced non-radiative recombination and hence an improved material quality.Normalized PL spectra for the different post-deposition annealing temperatures are shown in Figure6.The energetic peak position is unchanged around 1.20 eV, in agreement with the bandgap values observed from the IQE (FigureS5a).The upper left inset shows that the peak full width at half maximum (FWHM) reduces with increasing post-deposition annealing temperature indicating an improved material quality, in terms of band tails and/or homogeneity.In particular, it is shown that band tails or a distribution of bandgaps have a direct the sample annealed at 250 C, an increased quasi Fermi level splitting of roughly 50 meV is estimated compared to the reference sample, which is in good agreement with the increase of the V OC (within the spread of the data shown in Figure 3A) of the final devices processed from the same samples as used here for the PL characterization.The sample annealed at 200 C should yield a similar improvement of the open-circuit voltage.However, interface recombination dominates this complete solar cell device, which reduces the opencircuit voltage (Figure It is noted that an increased quasi Fermi level splitting (as well asV OC ) may result from an increased charge carrier lifetime or from an increased net doping density.Several difficulties arise to discriminate these origins.First, due to the low PL yield, it is not possible to measure time-resolved PL to extract the charge carrier lifetime.Second, it is difficult to extract correct doping densities for instance by capacitance based methods due to the influence of deep defects[70], which are measured in abundance by admittance spectroscopy on Sb 2 Se 3based solar cells[12,23,35,49,50,52].In addition, it is not clear if the space-charge region (needed to measure any voltage dependence) or the geometrical capacitance is measured at the lowest temperatures and highest frequencies, where contributions of deep defects cannot follow the ac-modulation voltage.Thus, currently, it is not possible to attribute the contributions of the net doping density and the (minority) carrier lifetime to the increased quasi Fermi level splitting.

F I G U R E 7
Temperature dependence of the open-circuit voltage.Extrapolation of a linear fit to 0 K yields the activation energy E A of the dominant recombination path.Errors of the activation energy are taken from the fitting confidence interval.

Figure 8A .
Figure 8A.First, in order to demonstrate the quality of the Sb 2 Se 3 / CdS stack in the 25 C reference state, a laser power of 10 mW is used, resulting in a stable but relatively low PL yield (labeled: 1st: 10 mW).Second, the laser power was set to 100 mW resulting in an instantaneous increase in the PL During the duration for nearly 400 s, the PL yield increases with respect to time indicating an improving material quality with ongoing laser irradiation/annealing.Third, the sample is measured again at 10 mW (labeled 3rd: 10 mW).Compared to the initial measurement at 10 mW (1st), the PL yield increased by a factor of 3.3.In comparison, the sample annealed at

3. 5 |
Elemental depth profilingSeveral reports exist, which indicate that the Sb 2 Se 3 /CdS interface is not stable and elemental diffusion and intermixing takes place at the interface[8,19,21,23,50,52].In particular, for superstrate devices, it is assumed that an intermediate CdSe layer forms and has been identified to cause problems for the photocurrent collection[19,73].Elemental depth profiling our substrate configuration Sb 2 Se 3 absorber layers covered with a CdS buffer layer using SIMS could not detect a measurable compositional difference across the Sb 2 Se 3 /CdS interface between the reference and the 250 C post-deposition annealed device (Figure9A), which hints that no large CdSe layer forms within the error of the measurement.It is noted that the profiles shown in Figure9do not necessarily indicate inter-diffusion of F I G U R E 9 (A) Elemental gradients of Sb, Se, Cd, and S across the Sb 2 Se 3 /CdS interface.The overlap of Se and Sb with Cd and S is the result of surface roughness.No differences between the reference and the 250 C post-deposition annealed device is observed.(B) Na and K alkali elements for the reference and the 250 C post-deposition annealed device.Clearly, a significant increase of the alkali elements is observed upon post-deposition annealing with peak values at the Sb 2 Se 3 /CdS interface (gray dashed line).Note the different scale on the abscissa for (A) and (B).The combined plot of (A) and (B) is shown in Figure S9a on a larger depth scale.F I G U R E 1 0 TEM analysis of the solar cell device with a post-deposition annealing temperature of 250 C. (A) Cross-section STEM of the solar cell device; (B,C) EDX mapping showing the presence of Cd, Sb, S, Se, and Mo; (D) elemental profile of the selected region in (a); (E) HRTEM measurement of the Sb 2 Se 3 /CdS interface.FFTs (yellow, CdS; purple, Sb 2 Se 3 /CdS; and red, Sb 2 Se 3 region, respectively) are carried out to obtain the underlying crystal structure.No secondary phase is detected close to the interface, and all diffraction characteristics can be explained by crystal structures of CdS and Sb 2 Se 3 .

Figure
Figure 10B,C STEM-EDX elemental maps of Sb, Se, Cd, S, and Mo for the device post-deposition annealed at 250 C. The elemental maps display a CdS coating of 80 nm, the Sb 2 Se 3 layer with thicknesses oscillating between 400 and 800 nm, and a MoSe 2 layer of 150 nm.Elemental profiles in Figure 10D of the region of interest selected in Figure 10A show no indication of elemental intermixing at the Sb 2 Se 3 /CdS interface, in agreement with the SIMS results.Figure 10F shows a HRTEM image of the Sb 2 Se 3 /CdS interface.A thin (approximately 2 nm) interface region is observed, which is a narrow overlapping region between adjacent areas as the result of the finite thickness of the TEM lamella and does not indicate another phase and/or material composition.The crystal structures at the interfaces are investigated by fast Fourier transforms (FFTs) within dedicated regions close and across the Sb 2 Se 3 /CdS interface (yellow, CdS; purple, Sb 2 Se 3 /CdS; and red, Sb 2 Se 3 region, respectively).All the FFTs correspond to those obtained from the Sb 2 Se 3 and CdS crystal structures, which indicate that no secondary phase forms at the interface (see Figure S10 for additional details).

6 and 4 . 3 ( 4 | DISCUSSION 4 . 1 |
Illuminated (solid lines) and dark (dashed lines) JV characteristics for a Sb 2 Se 3 /CdS reference device (ref.ALD) and with TiO 2 and Sb 2 S 3 intermediate layers between the Sb 2 Se 3 /CdS interface.(B) EQE curves (left ordinate) of the devices shown in (A) indicating a strongly increased photo-current upon insertion of intermediate TiO 2 and Sb 2 S 3 buffer layers.The increase (compared to the reference device) of the EQE is over the whole wavelength range, with increased contribution for higher wavelengths (right ordinate).(C-F) Statistics for V OC , J SC , FF, and efficiency, respectively.devices with intermediate TiO 2 and Sb 2 S 3 layers between the Sb 2 Se 3 / CdS interface.The interfacial layers improve all the photovoltaic parameters, as presented by the statistics in Figure 11C-F.V OC values increase from 340 mV for the reference device to 380 mV for the devices with interfacial layers.This improvement, similar to the postdeposition annealing, can be attributed to an increased activation energy of J 0 from 0.86 eV to 1.00 and 1.02 eV for the TiO 2 and Sb 2 S 3 interfacial layer, respectively (Figure S8).Very importantly, the interfacial ALD Sb 2 S 3 and TiO 2 layers boost J SC values from 15 mAcm À2 to average values of 24.0 and 22.3 mAcm À2 , respectively.The resulting efficiencies of the devices show a clear increase from 2.0% for the reference solar cells, to 4.2% and 3.7% average efficiencies, being 4.2% the highest efficiency values for Sb 2 S 3 and TiO 2 , respectively.The EQE spectra for the three different buffer layer configurations are shown in Figure 11B demonstrating an improved collection over the whole wavelength range.From the ratio of the EQEs (right ordinate), it is apparent that the collection improves in particular for longer wavelengths by up to 60% compared to the reference device.TEM cross-sections of a solar cell device with a Sb 2 S 3 interfacial layer is presented in Figure 12A.EDX mappings in Figure 12B,C show the CdS and Sb 2 Se 3 layers and the absence of MoSe 2 (due to selenization temperature of only 320 C) at the Sb 2 Se 3 /Mo interface.Lower magnification TEM micrographs and elemental distribution maps expose the infiltration of CdS through pinholes in the Sb 2 Se Figure S11).Elemental profiles show that CdS and Sb 2 Se 3 layers preserve a sharp interface (Figure 12D).The analysis of the FFTs taken along the Sb 2 Se 3 /Sb 2 S 3 /CdS interface from the HRTEM image further confirms the absence of secondary phases and the formation of single crystalline structures.In particular, no crystalline stibnite Sb 2 S 3 is detected (Figures 12E and S15); possibly because an amorphous Sb 2 S 3 is deposited and/or because the volume of Sb 2 S 3 is below the detection limit.The HRTEM displays Moiré patterns at the interface due to the overlapping of two different crystal orientations attributed to the thickness of the lamella sample extracted from the device.Interface recombination

1 2
TEM analysis of solar cell devices based on Sb 2 Se 3 layers selenized at 320 C with an interfacial layer of Sb 2 S 3 at the Sb 2 Se 3 /CdS interface.(A) Cross-section STEM of the solar cell device.(B,C) EDX mapping showing the presence of Cd, Sb, S, Se and Mo; (D) elemental profile of the selected region in (a); (E) HRTEM measurement of the Sb 2 Se 3 /ALD-Sb 2 S 3 /CdS interface.FFTs (yellow, CdS; green, Sb 2 Se 3 /CdS; purple, Sb 2 Se 3 ; and red, Sb 2 Se 3 region, respectively) are carried out to obtain the underlying crystal structure.Sb 2 S 3 interfacial layer is not detected.No secondary phase is detected close to the interface, and all diffraction characteristics can be explained by crystal structures of CdS and Sb 2 Se 3 .The devices presented in Figure7, in particular the devices after post-deposition annealing, show an activation energy of J 0 close or equal to the bandgap of the Sb 2 Se 3 absorber layer, which is the highest value reported so far.These activation energies of J 0 directly influence the V OC via Equation (4) and can explain the increased values after post-deposition annealing up to 485 mV.It can be conjectured that the post-deposition annealing reduces defects at the Sb 2 Se 3 /CdS interface.For instance, removal of acceptor-like defects close to the conduction band will result in (quasi) Fermi levels, which can move upon a bias voltage, that is, Fermi levels that are not pinned, and thus an activation energy equals the Sb 2 Se 3 bandgap is obtained [77].Another possibility is the removal of defects upon post-deposition annealing, which are the origin of dipoles at the interface.Dipoles at the interface can induce a cliff-like band offset (minimum of the conduction band of the buffer below the conduction band minimum of the Sb 2 Se 3 absorber) and thus a lowered interface bandgap and hence a reduced activation energy of J 0 .The cases of a pinned Fermi level and a cliff-like band-alignment are simulated in the one-dimensional solar cell simulator SCAPS [78].In Supporting information sect.C, band-alignments, IV, QE, and V OC T ð Þ simulations are presented for the scenarios mentioned above.These simulations support the results presented here that the postdeposition annealing leads to increased V OC values due to an improved Sb 2 Se 3 interface quality.In addition, based on the used simulation parameters, further improvements in V OC and device efficiency are predicted to rely on a higher Sb 2 Se 3 quality, once a good interface is achieved (activation energy of J 0 equals the Sb 2 Se 3 bandgap).
It was shown in Section 3 that the material and interface quality improves upon post-deposition annealing due to i. Increased PL yield and therefore a lowered non-radiative recombination current ii.A decreased FWHM of the PL spectrum due to decreased disorder iii.An increased activation energy of J 0 due to an improved Sb 2 Se 3 / CdS interface iv.A lowered J 0 and hence an increased open-circuit voltage limitations of the open-circuit voltage for Sb 2 Se 3 /CdS substrate solar cells are investigated.It is shown that a post-deposition annealing after the CdS buffer layer deposition can significantly improve the open-circuit voltage due to an improved activation energy of J 0 resulting in a reduced non-radiative recombination.In particular, activation energies as high as the Sb 2 Se 3 bandgap are demonstrated, which shows that major losses due to interface recombination (pinned Fermi level or a conduction band cliff) can be eliminated.SIMS and HRTEM measurements do not show the occurrence of another phase at the Sb 2 Se 3 /CdS interface.However, while V OC improves, J SC decreases and consequently limits the efficiency of the devices presented here.EQE measurements in combination with simulations indicate that the transport properties within the Sb 2 Se 3 bulk might be the reason for the reduced J SC .Similar to the post-deposition annealing, intermediate ALD buffer layers such das TiO 2 or Sb 2 S 3 show an increased activation energy of J 0 as well and thus a reduced interface recombination.