The Doping of Si p‐Field‐Effect Transistor Devices by Gallium Focused Ion Beam Implantation Enabling Flexible Fabrication Routes at Moderate Temperatures

A maskless approach of forming p‐doped regions in Si wafers using the Ga source of a standard focused ion beam (FIB) system and the moderate activation temperatures of 400–700 °C is demonstrated in this work. This simple and flexible route is accessible to many research labs and is successfully used to fabricate Si‐based diodes and field‐effect transistors (FETs). For the diodes, tunneling is found to be the forward current transport mechanism. The fabricated p‐FET structures show excellent switching behavior with a high ID,ON/ID,OFF current ratio of 5 × 106.


Introduction
Gallium is used as a p-type dopant of silicon for various applications, including long-wavelength IR silicon detectors in the atmospheric window between 8 and 14 μm [1] and in photovoltaics as a substitution for boron substrate doping to extend the minority carrier lifetime and to reduce degradation. [2,3] Already in the 1980s, Ga implantation with an acceleration energy of E ¼ 275 keV [4] and for focused ion beam (FIB) implantation with E ¼ 50 keV [5] together with moderate activation and annealing temperatures of 400-700 C have been demonstrated. While the previous studies [4,5] analyzed doping profiles, sheet resistances, and a structural analysis of the Si crystal, a performance test in real devices has not been conducted. While the FIB technique is increasingly used for micro-and nano-analysis, ion microscopy, and the repair of interconnects, [6] its application for direct doping in semiconductor device manufacturing is strongly limited by the low throughput. [7] However, maskless doping is of interest for experimental devices and research or academic institutions where an FIB tool is available as imaging equipment and lamella preparation. It brings superior design flexibility, allows structures in the 100 nm range, and eliminates photomask purchasing costs. In this regard, bipolar transistors, [8] junction gate field-effect transistors (JFETs), [9] in-plane gate transistors, [10] and also metal-oxide-semiconductor fieldeffect transistors (MOSFETs) [11] have already been realized using a Ga FIB tool. However, electrical data of the MOSFETs have not been shown by Wanzenboeck et al., [11] and the same applies to an insight into a possible integration flow for the fabrication of the p-field-effect transistor (FET). Our work closes this gap and additionally expands the presented output and transfer characteristics by simulations in LTspice. We use FIB implantations of gallium for the fabrication of diodes and an active device in the form of a p-FET. An additional investigation of diodes allows to compare our process to previous studies. [12,13] While the FIB-based implant is fully capable of defining doped regions with lateral dimensions down to the 100 nm range, this exceeds the limits of the i-line contact lithography system used to define the metal contacts of source, drain, and gate of the FET. Therefore, we realized doped areas with dimensions in the micrometer range. A possible application is the realization of a p-through-silicon via FET (TSVFET) with a hole diameter of several tens of micrometers that was only published as an n-FET before. [14] Through silicon vias are often introduced in the presence of the metallization, [15] allowing only low thermal budgets for its fabrication. The moderate activation temperature of implanted gallium in silicon enables the fabrication of active device inside these holes.

Preliminary Considerations
An FEI Expida 1285 FIB system has been used, allowing acceleration voltages between 3 and 30 kV. Simulations using the SRIM [16] software revealed a projected range R p of 29.6 nm and a longitudinal straggling ΔR p of 9.3 nm for the highest possible ion energy of 30 kV. The implantation of Ga using very high ion fluences leads to the formation of a very shallow continuous amorphous Si layer. This critical fluence was found to be 8-10 Â 10 13 ions cm À2 for 50 keV Ga implantations. [5] To form a The copyright line for this article was changed on 17 December 2020 after original online publication. DOI: 10.1002/pssa.202000511 A maskless approach of forming p-doped regions in Si wafers using the Ga source of a standard focused ion beam (FIB) system and the moderate activation temperatures of 400-700 C is demonstrated in this work. This simple and flexible route is accessible to many research labs and is successfully used to fabricate Si-based diodes and field-effect transistors (FETs). For the diodes, tunneling is found to be the forward current transport mechanism. The fabricated p-FET structures show excellent switching behavior with a high I D,ON /I D,OFF current ratio of 5 Â 10 6 .

ORIGINAL PAPER
www.pss-a.com continuous amorphous Si layer using a lower implantation energy of 30 keV, the fluence must be larger and was, therefore, chosen in the range of 10 16 ions cm À2 . This allowed low activation temperatures in the range of 400-600 C by regrowing the Si crystal from the amorphous layer and incorporating the Ga via solid phase epitaxy. [4,17] This temperature is rather low compared with vacancy-mediated self-diffusion, which usually requires above 750 C. [18] Grove reported an activation energy of E A ¼ 3.31 eV and a preexponential factor of D 0 ¼ 8.21 Â 10 À5 m 2 s À1 for the diffusion of Ga in Si. [19] For Ga diffusion in SiO 2 , an activation energy of E A ¼ 4.17 eV and D 0 ¼ 1.04 Â 10 1 m 2 s À1 could be calculated from the previous studies. [20,21] This allows the determination of the diffusion length L D of gallium in Si and SiO 2 during the activation anneal, that is required after implantation, by the following equations where t is the diffusion time, D is the diffusion coefficient, k is the Boltzmann constant, and T is the diffusion temperature.
The fabrication steps are shown in Figure 1. The implantation was performed with an acceleration voltage of 30 kV with no tilt angle, and the fluence varied between 1 and 8 Â 10 16 cm À2 , while using a low ion current (5900-8250 pA) to limit the Si layer removal to <10 nm. Due to this superimposed sputter effect of the surface, the concentration maximum shifts to deeper regions. The roughness was below 5 nm, as obtained by measurements using a Veeco Dektak 8 profiler. The so-called "TV Mode" of the FEI Expida 1285 was used, whereby an optimal resolution was achieved using a beam diameter of 10 nm for implantation of a rectangular area in multiple scans. A maximum activation temperature in the range of 400-700 C was applied for 15 min in N 2 atmosphere in a conventional furnace. As shown in Table 1, the change of the implantation profile is negligible at these temperatures (e.g., diffusion length of 1.1 nm in Si at 700 C). Table 1 summarizes the calculated diffusion lengths of Ga in Si and SiO 2 , indicating the fast diffusion in SiO 2 . The real values are expected to be slightly higher, because the samples additionally experienced the upward and downward ramps of the furnace (T max was reached after 30 min, cool down within 30 min to T < 100 C).   of the diodes. The high leakage currents of samples 6 and 7 occur due to a so-called "reverse" annealing effect, [12] namely, a decrease in the electrical activity of the implanted ions when a critical annealing temperature is exceeded. As Figure 2b shows, the highest on-current density ( J on at 1 V) was obtained for the activation temperature of 400 C, and it is also accompanied by the largest on/off current ratio of all diodes. The higher the activation temperature, the more Ga will escape from the silicon, and the lower is the resulting surface dopant concentration. This is detrimental to the contact resistance of the metal-semiconductor interface. The effective resistance of this Schottky barrier is, among other things, determined by the doping concentration at the interface. The expected result of an increasing contact resistance is a reduction of the output current density J on of the diode, which is exactly what our experimental observations in Figure 2b show for the annealing temperatures of 650 and 700 C. The sample that was annealed at 500 C should be viewed with caution, because the activation energy of the saturation current density differs strongly from the other samples, as shown in the following.

Temperature Dependence
I-V-T measurements have also been performed to gain insights into the current transport mechanism dominating the p-n junction. In general, the forward current density of a p-n junction can be expressed as with and where J 0 is the saturation current density, A is the temperaturedependent coefficient, n is the diode ideality factor, and k is Boltzmann's constant. Typical current transport mechanisms that have been proposed are diffusion, recombination, thermionic emission, and tunneling (see Table 2). By comparing the measured activation energies E a of J 0 (T ), n as well as A(T ) with the model prediction (see Table 2) conclusions about the conduction mechanisms in the devices can be drawn. Figure 3a shows the exponential term A as a function of 1000/T for selected devices, which were annealed at different temperatures (400-700 C). As it is shown, the exponential term A is almost independent of the measurement temperature (1000/T). This demonstrates that the temperature-independent conduction mechanism of tunneling [22] dominates the devicesindependent of the dopant activation and annealing temperature. This is in contrast to the study of Mogul and Steckl, [12] where diffusion and generation currents were identified for p-n diodes based on Ga implantation of lightly doped n-Si substrates. However, the annealing conditions and Ga fluence in the present study were different compared with Mogul et al., [13] which might also lead to different electrical transport across the p-n junction. The saturation current density J 0 as a function of 1000/T is shown in Figure 3b. Here, J 0 is extracted from a fit of the exponential part of the J-V curves between about 0.1 and 0.4 V. The exponential relationship between J 0 and 1000/T is matching most with multistep tunneling capture emission (MTCE) as the tunneling model, comparing it with data from the previous study. [23] The extracted activation energies E a in Figure 3b span a range of 0.56-0.71 eV, except for the sample annealed at 500 C, that exhibits a much lower value of 0.17 eV, which we believe is an outlier. The relatively high activation energies for the majority of the samples indicate that the electron capture rate is larger than the hole emission rate. [22] Table 2. Current transport mechanisms of p-n diodes with saturation current density J 0 (T ), temperature-dependent exponential term A(T ), and diode ideality factor n.

p-FET Fabrication
Si wafers (100) with phosphorous n-doping (1 Â 10 15 ions cm À3 ) and a thickness of 525 μm were used as a substrate. A SiO 2 layer of 1000 nm thickness was thermally grown at 1000 C in H 2 O atmosphere to serve as field oxide (FOX). Alternatively, a plasma-enhanced chemical vapor deposition (PE-CVD) process as the one described in the following could be used in the case of a restricted thermal budget. The source and drain areas were patterned using a first lithography mask. Wet etching was done with buffered hydrofluoric acid (BHF). Subsequently, gallium was implanted, utilizing an FEI Expida 1285 FIB system. The resist was left on top of the oxide to protect it from the ion bombardment. A rectangular area, overlapping source and drain, was scanned by the ion beam, as shown in Figure 4a.  www.advancedsciencenews.com www.pss-a.com 6.5 Â 10 16 cm À2 , and the ion current was again kept very low at 600 pA, leading to a very thin Si layer removal of about 10 nm and a Si surface roughness of <5 nm. An acceleration voltage of 30 kV was used, and there was no tilt angle between the wafer surface normal and the ion beam. The resist was subsequently removed, and 500 nm of SiO 2 was deposited via the PE-CVD process using silane and nitrous oxide at 340 C, as shown in Figure 4b. This cover layer should primarily prevent a contamination of the silicon originating from the furnace tube during thermal activation and annealing performed in N 2 for 15 min at 600 C. Subsequently, the CVD oxide was removed with BHF. During that treatment, the underlying thermally grown SiO 2 layer serving as FOX was thinned down from originally 1000 to 890 nm. With a second mask, the active area was defined (patterning of the FOX) by removing the remaining silicon dioxide in the channel area between source and drain and in a small section around them (Figure 4c).
The gate dielectric was made of a stack of SiO 2 and Al 2 O 3 . The oxide was grown at 700 C for 60 min, resulting in a layer of 8 nm thickness. As shown by preliminary experiments, Ga tends to agglomerate under very high temperatures; therefore, it had to be kept moderate for the gate oxidation.
This higher thermal budget is expected to negatively affect the performance of the source/drain junctions and contact resistances (compare with Figure 2a, diode reverse current density is several orders of magnitude higher for 650/700 C anneal than lower temperatures). However, the corresponding MOSFETs show an excellent switching behavior. To safely prevent a degradation at this point, an even thinner chemically grown interface oxide (SC1 or piranha treatment) could be an alternative. As mentioned in Section 2, gallium diffuses fast in SiO 2 (segregation coefficient m > 1), and a diffusion length of 4.4 nm is expected for annealing at 700 C for 60 min. Thus, most of the Ga diffusing into the SiO 2 also escapes into the furnace atmosphere, and the surface concentration in the silicon is reduced. A layer of 30 nm Al 2 O 3 was deposited on top of the SiO 2 by thermal atomic layer deposition (ALD) at 300 C with tri-methyl aluminum (TMA) and H 2 O as the precursors. [24] As shown in Figure 4d, a third mask was used to structure contact holes, which was again done by wet etching with BHF.
A stack of titanium (20 nm, as Si diffusion barrier to prevent spiking [25] ) and aluminum (300 nm) was deposited by e-beam evaporation and structured by a fourth mask as the gate metal as well as the source and drain contact metal. Wet etching was done by an etchant containing phosphoric acid (for Al) and 0.5% HF (for Ti). The backside of the wafer was metallized by Al (500 nm) to ensure a good body contact. The fabrication was concluded by a forming gas anneal at 400 C for 45 min (5% H 2 in N 2 at atmospheric pressure) to reduce the contact resistivity and to passivate oxide and interface defects. The transistor structure is shown in Figure 4e.
The gate lengths of the transistors ranged from 10 to 25 μm. The top view microscope image of a transistor with a gate length of 15 μm is shown in Figure 5.

p-FET Characterization
The p-FETs were electrically characterized with a Keithley 4200 Semiconductor Characterization System. Output curves I D (V D ) and transfer curves I D (V G ) were measured in direct current mode. The results for transistors with a gate length of 15 μm are shown in Figure 6a,b. Output curves with a very stable saturation could be measured, and a very high I D,ON /I D,OFF ratio was found at 5 Â 10 6 (V D ¼ À6 V and V G,on ¼ À4 V/V G,off ¼ 0 V), representing an excellent switching behavior. The threshold voltage was À0.61 V, and a maximum field-effect mobility of 480 cm 2 V À1 s À1 was calculated from the transfer curve using a gate capacitance per unit area of 1.53 Â 10 À3 As V À2 m À2 . The sub-threshold swing was found to be 73 mV dec À1 , which is a typical value for silicon MOSFETs.

Simulation in LTspice
Simulations of the p-FET were done in LTspice. [26] The following parameters were defined for the model.  www.advancedsciencenews.com www.pss-a.com The simulated saturation currents are in good agreement with the measurements, as shown in Table 3. To achieve this good fit, the source and drain resistances (RS and RD) had to be set to very high values of 24 and 13 kΩ, respectively. Under the assumption of single crystal Si, an average doping concentration in the range of 3 Â 10 17 -7 Â 10 17 cm À3 was calculated for the estimated junction depth of 39 nm (%R p þ ΔR p ), a source/drain width of 29 μm, and also, a contact hole distance of 29 μm from the transistor channel. The activated carrier concentration of gallium is expected to exceed these moderate values, because the S/D resistance is negatively affected by the grain boundaries and crystal defects resulting from incomplete annealing after implantation. [5]

Conclusion
We report the maskless doping using a standard FIB instrument for Ga implantation into silicon. The capabilities of this approach were assessed in Si diodes and p-FETs as demonstrator devices. The activation of the implanted dopants could be done at moderate temperatures between 400 and 700 C. This makes gallium an interesting alternative dopant for low thermal budgets. Independent of the annealing temperature, the mechanism of tunneling is dominating for the manufactured diodes as the forward current transport mechanism. An integration flow for the transistors is shown that yields devices with a very low off-current below 10 À11 A and a very high I D,ON /I D,OFF ratio of 5 Â 10 6 for V G ¼ À4 V. While we used micrometer-sized "lab-scale" devices in this work due to limitations of our metal lithography process, we believe that the process can be transferred to more advanced scaling nodes enabling design flexibility and low activation temperatures. A lateral scattering of 7.2 nm was obtained for an ion energy of 30 keV from SRIM simulations for the impinging Ga ions-a radius of 3.6 nm surrounding the point of impact. With a minimal beam diameter of about 10 nm, the lateral dopant distribution could be kept at a minimum of <15 nm. As the minimal point-to-point distance is in the range of several 10 nm (typical for transmission electron microscope lamella preparation), a minimal source/drain spacing (representing the channel length of the FET) in the same range is expected.