Surface Preconditioning and Postmetallization Anneal Improving Interface Properties and Vth Stability under Positive Gate Bias Stress in AlGaN/GaN MIS‐HEMTs

Trap states at the dielectric/GaN interface of AlGaN/GaN‐based metal–insulator–semiconductor high electron mobility transistors (MIS‐HEMTs) can cause threshold voltage (Vth) instability especially under positive gate bias stress. Herein, the influence of O2 plasma surface preconditioning (SPC) before the atomic layer deposition of the Al2O3 gate dielectric and of N2 postmetallization anneal (PMA) after gate metallization on the Al2O3/GaN interface quality is investigated. The interface is characterized by multifrequency capacitance–voltage measurements which show a smaller frequency dispersion after the employment of SPC and PMA treatments with a reduction of the interface trap density Dit to a value in the order of 2 × 1012 cm−2 eV−1 near the conduction band edge. The effectiveness of SPC and PMA is demonstrated in Al2O3/AlGaN/GaN MIS‐HEMTs by pulsed current–voltage measurements which reveal improved Vth stability.


Introduction
AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next-generation high-efficiency and high-voltage power applications. [1] This is a result of the excellent physical properties of GaN-based materials in terms of critical electric field and carrier saturation velocity, combined with the high carrier density and large mobility of the two-dimensional electron gas (2DEG) confined at the AlGaN/GaN interface which enables a low on-state resistance. [2] Moreover, the employment of an insulator in MIS-HEMTS compared to Schottky-Gate HEMTs gives the additional advantage of significant gate leakage reduction, enabling larger gate bias swing and better immunity to gate breakdown. [3,4] However, the insertion of a gate dielectric can cause operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. [5][6][7][8] Interface trap states can lead to dynamic charge/ discharge processes which are critical especially in the case of wide bandgap GaNbased materials where traps can be deeply located in the bandgap and can result in a significant threshold voltage (V th ) instability due to their extremely slow detrapping behavior. The V th instability under different bias conditions in AlGaN/GaN-based MIS-HEMTs has been often reported. [9][10][11][12][13] In particular, serious V th shift induced by forward gate bias stress due to electron trapping at the dielectric/ III-N interface is one of the major concern in terms of device reliability. [14][15][16][17] Therefore, the minimization of trap states at the interface is a critical issue for GaN-based MIS-HEMTs. Although a reduction of the interface trap density (D it ) has been reported after various surface treatments and postdeposition annealing, [6,[18][19][20][21][22][23][24] still few reports have dealt with the effects of surface and postdeposition treatments in terms of D it and their related implications on V th stability during forward gate bias stress conditions.
In this context, this work investigates the interface of Al 2 O 3 /III-nitrides structures where atomic layer deposited (ALD) Al 2 O 3 is used because of its promising properties as gate dielectric in MIS-HEMTs in terms of large bandgap (7-9 eV), high dielectric constant (8)(9)(10), and large conduction-band offset to GaN (%2.1 eV). [25,26] In particular, the effects on the Al 2 O 3 /III-nitrides interface of an O 2 plasma-based surface treatment applied before the Al 2 O 3 deposition and of a N 2 annealing after gate metallization are investigated. The Al 2 O 3 /GaN-cap/ AlGaN/GaN interface is characterized using multifrequency capacitance-voltage (C-V ) measurements from which the D it is determined. The combination of the O 2 plasma-based surface treatment and N 2 annealing is shown to reduce the frequencydispersion in the C-V curves which indicates a better Al 2 O 3 / III-nitride interface quality with reduced D it in the range of 2 Â 10 12 cm À2 eV À1 . The effectiveness of the O 2 plasma-based surface treatment and N 2 annealing is then demonstrated and discussed in AlGaN/GaN MIS-HEMTs using ALD-Al 2 O 3 as gate dielectric by positive gate stress pulsed measurements which show improved V th stability. Afterward ohmic contacts are formed using an evaporated Ti/Al/Ni/Au metal stack by lift-off technology and subsequent rapid thermal annealing (RTA) in N 2 ambient at 850 C for 30 s. The gate structuring is then carried out using a 16 nm-thick Al 2 O 3 deposited by thermal ALD as gate dielectric, followed by evaporation and lift-off of a Ti/Au gate electrode. Details of the ALD process conditions are reported in a previous study. [27] For this study, a surface preconditioning (SPC) treatment is applied before the Al 2 O 3 deposition to the GaN surface which consists of a sequence of low power (100 W) O 2 plasma treatment for 90 s at 100 C followed by HCl wet treatment for 1 min. In addition, a postmetallization anneal (PMA) is carried out after gate electrode formation in N 2 ambient at 350 C for 10 min. The influence of both SPC and PMA on the Al 2 O 3 /III-nitride interface quality in MIS diodes ( Figure 1a) and on the threshold voltage stability in MIS-HEMTs (Figure 1b) is investigated by multifrequency capacitance-voltage measurements and positive gate-stress pulsed sweep measurements, respectively. Capacitance-voltage (C-V ) and pulsed current-voltage (I-V ) measurements are carried out using an Agilent B1505A Power Device Analyzer. The GaN surface morphology before and after SPC is investigated by atomic force microscopy (AFM). Figure 2a shows the AFM image of the as-grown MOCVD GaN-capped AlGaN/GaN heterostructure surface which shows the typical smooth surface with terraces of mono-or bilayer high step edges. [10] Pits at the step edge terminations which are associated to dislocations are also visible. As comparison, the GaN surface of a sample after ohmic contacts patterning, organic wet cleaning and subsequent annealing is shown in Figure 2b.

Surface Preconditioning
The surface morphology appears rough and covered by particles which is attributed to a partial surface contamination and decomposition after lift-off and to the high temperature annealing for the ohmic contact formation. As the optimization of the device performance depends on the surface condition especially before the ALD-Al 2 O 3 dielectric deposition, it is very important to obtain a clean surface by removing contaminants without damaging the crystal order or introducing additional defect states. For this purpose, an SPC consisting of a partial surface oxidation by O 2 plasma and a subsequent wet cleaning by HCl is applied to the GaN surface after ohmic contact formation. Figure 2c shows that the SPC is effective in removing contaminants and restoring  www.advancedsciencenews.com www.pss-a.com the flat step-like terrace structure of the surface resulting in a template similar to the usual as-grown GaN surface ( Figure 2a). In the next sections, the impact of the SPC on the electrical properties of the Al 2 O 3 /III-nitride interface in MIS diodes and MIS-HEMTs is investigated.

C-V Characteristics of ALD-Al 2 O 3 MIS Structures
The ideal C-V characteristic of an Al 2 O 3 /GaN-cap/AlGaN/GaN diode consists of a double-step curve which is a typical feature of a metal-insulator-heterostructure with a double-interface structure (Al 2 O 3 /GaN and AlGaN/GaN), as shown in Figure 3. [6,7] In the subthreshold region (below V th ) the 2DEG is depopulated and the capacitance is very small. Near V th a rapid change in the capacitance starts to occur due to the electron population of the 2DEG at the AlGaN/GaN interface. In this region, the capacitance is almost bias independent and is given by the series capacitance of the AlGaN, GaN-cap, and Al 2 O 3 layers. By applying a positive bias, electrons start to overcome the AlGaN barrier layer and accumulate at the Al 2 O 3 /GaN interface resulting in a second step in the C-V characteristic. This region is referred to as spill-over regime and its onset voltage is here indicated as V spill-over . The capacitance value of the flat part in the spill-over region is given by C Al 2 O 3 . The ideal C-V behavior is modified when interface trap states are present at the Al 2 O 3 /GaN interface. [6,7,28] In the spillover region, once electrons are trapped at the interface the negatively charged states screen the gate electric field resulting in a shift of V spill-over toward the positive bias direction. Second, they lead to a drastic decrease in the C-V slope of the second step due the dependence of the traps occupancy as a function of the gate voltage. A schematic illustration of the conduction band diagram of an Al 2 O 3 /GaN/AlGaN/GaN structure at zero bias applied compared with the spill-over case is shown in Figure 3. In case of very high interface state densities, the second step might not be visible even at very high positive bias voltages due to a large positive shift of V spill-over which cannot be detected due to the increase in leakage currents. On the contrary, near threshold voltage the trap occupancy of D it does not depend on the gate voltage and results in a parallel shift of the corresponding C-V step without any stretch out. [29] The experimental C-V characteristics of Al 2 O 3 /GaN-cap/ AlGaN/GaN diodes with 16 nm thick Al 2 O 3 in the cases that no treatment is applied, with SPC and with the combination of both SPC and PMA are shown in Figure 4. The first flat part in the C-V curves is in accordance with the described capacitance model considering 22, 2, and 16 nm of AlGaN, GaN, and Al 2 O 3 , respectively. However, in the case no treatment is applied, the second step is instead not visible in the voltage range considered because the amount of interface traps is probably so large that the second step is shifted beyond 4 V, after which the leakage current becomes too large to perform accurate measurement. Conversely, the typical double-step C-V curves are observed in the case of samples treated by SPC and SPC combined with PMA. By applying only the SPC, even though the presence of the second step indicates a reduced amount of interface states compared with the untreated case, as shown in Figure 4, the ideal value of C Al 2 O 3 is not reached because of a large amount of traps still present at the interface causing a stretch out of the C-V curve. When the PMA is applied in combination with the SPC, the change of the capacitance of the second step becomes  www.advancedsciencenews.com www.pss-a.com very steep by reaching the ideal value C Al 2 O 3 and a slight shift of V spill-over toward 0 V is also visible. This is a qualitative indication of the effectiveness of SPC combined with PMA to improve the interface quality by reducing the amount of traps at the Al 2 O 3 / GaN interface.

D it Extraction Using Frequency Dispersion in C-V Characteristics
The extraction of D it in MIS-HEMT structures is challenging due the presence of two interfaces which complicates the potential distribution over the structure and a low emission rate of electrons in the wide bandgap semiconductor. [13,30] The conventional conductance method may lead to an underestimation of D it due to the presence of the additional capacitance introduced by the AlGaN barrier. [31] As Yang et al. reported, [31] the frequencydependent C-V method is a better technique to map the interface traps at the dielectric/III-nitride interface, and it is used in our study to determine the interface trap density D it .
In particular, the interface trap analysis is carried out using the frequency dispersion of the C-V characteristics in the spill-over region of the Al 2 O 3 /GaN/AlGaN/GaN diode structures. In forward bias region, E F is moving upward toward the conduction band at the Al 2 O 3 /GaN interface and its energy position is defined by the voltage applied ( Figure 3). Once E F is located at a certain energy position, the only electrons which can respond to the alternate current (AC) signal and be detected are the ones which are trapped and re-emitted from trap states with an emission time τ e smaller compared with the period τ related to the frequency of the AC signal (τ e < τ). The emission time constant for a trap level using the Shockley-Read-Hall statistics is where N C , υ, σ, E C , E T , k b , and T are the effective density of states in the conduction band, the thermal velocity, the capture cross section of the trap, the conduction band minimum, the trap energy, the Boltzmann constant, and the temperature, respectively. The period of the AC signal is given by where f is the frequency of the AC signal. Combining Equation (1) and (2), the maximum trap energy depth E T,f with respect to E C which can be probed by a certain frequency f can be deduced as At a certain frequency f, only charged trap states (depending on the position of E F ) which are in the energy range between E C and E T,f contribute to the capacitance and lead to the onset of spill-over at V spill-over in the C-V characteristic. Higher frequencies can therefore only probe energetically shallow states and lead to a positive shift of V spill-over because a higher voltage is required to raise E F towards E c . As a consequence, a smaller-frequency dispersion indicates a reduction of the interface state density. [6,31] In addition, a D it -E T energy map can be obtained using the voltage shift of the second step in the C-V curves using the following equation [31] with where C AlGaN and C Al 2 O 3 are the capacitance values of the AlGaN and Al 2 O 3 layers determined by their physical thicknesses, q is the elementary charge, and ΔV f 1 , f 2 is the voltage shift in the second step between C-V curves at frequencies f 1 and f 2 . ΔV f 1 , f 2 is determined at the midpoint of the capacitance in the second step of the C-V characteristics. Using Equation (3), the difference between E T,f 1 and E T,f 2 is instead given by In Figure 5, C-V curves with frequencies ranging from 1 kHz to 1 MHz are shown in the cases of no treatment applied, with SPC and with the combination of both SPC and PMA. In this case the bias voltage is swept from positive to negative direction to initiate each measurement in a defined state of maximum electron trapping. Note here that as shown from the comparison of the C-V characteristics measured at 1 kHz of Figure 4 and 5, the latter condition leads to a rigid shift toward positive direction of the C-V curve due to electrons trapped in deep energy states which are not re-emitted during the measurement time. www.advancedsciencenews.com www.pss-a.com Figure 5 shows that in the untreated case the second step is still not visible at all frequencies. Conversely, different frequency dispersions are obtained in the other two cases with a smaller frequency dispersion in the case of the combination of SPC and PMA. A smaller V spill-over and a steeper C-V slope are also revealed which indicates a reduction of the trap states at the Al 2 O 3 /GaN interface. Figure 6 shows D it -E T energy maps in the case of structures fabricated with SPC and with the combination of SPC and PMA which are determined accordingly to Equation (3) and (4) assuming a capture cross section σ of 10 À14 cm 2 . The combination of the SPC and PMA treatments improves the Al 2 O 3 /GaN interface by reducing the D it compared with the sample where only SPC is used. In the next section, the effectiveness of this approach is demonstrated to improve the electrical properties of MIS-HEMT using ALD-Al 2 O 3 as gate dielectric which is subjected to positive gate stress by pulsed measurements.

Pulsed I DS -V GS Measurements
For a comprehensive study, pulsed I DS -V GS sweep measurements of Al 2 O 3 /GaN/AlGaN/GaN MIS-HEMTs fabricated on the same samples as the capacitive test structures are carried out to investigate V th instability and for trap state analysis under positive gate stress condition. [8,11,12] The measurement consists of a stress phase during which a positive voltage (V GS,stress ) is applied to the gate, whereas source and drain are kept at 0 V (V DS,stress ) to ensure that trapping mainly occurs at the Al 2 O 3 / GaN interface. [9] In between each stress phase, short measurement pulses are applied to minimize detrapping from interface states consisting of a gate pulse of increasing height V GS and a low drain-source pulse V DS . A low V DS is used to reduce fieldassisted detrapping of the interface states. Figure 7 shows the pulsed transfer characteristics of the Al 2 O 3 /GaN/AlGaN/GaN MIS-HEMTs fabricated without and with SPC and PMA. The measurements are obtained by sweeping V GS from À10 to 0 V at V DS ¼ 1 V for gate stress voltages V GS,stress from 0 to 4 V and V DS,stress ¼ 0 V. The pulse period and pulse width are 50 and 1 ms, respectively, with 1 ms being the time limit of the measurement system. It is observed that the V th stability of the MIS-HEMTs improves for the devices fabricated by applying the SPC and PMA treatments. To better visualize the effectiveness of the treatments, Figure 8 shows the threshold voltage shift ΔV th as a function of the gate bias stress applied. Although the V th drifts in the positive direction for larger positive gate bias stress in all samples, the amplitude of the V th shift is significantly reduced in case of the MIS-HEMT treated by SPC and PMA. It is important to note here that the contribution of the interface traps to the V th shift obtained using pulsed I DS -V GS sweep measurements only reflects the occupancy of traps with an emission time τ e longer than the measurement pulse width. In fact, interface traps with emission time constants shorter than the pulse width are able to emit electrons before the sampling and cannot be detected using this method. The upper energy range limit which is detectable can be deduced from Equation (1) by considering  www.advancedsciencenews.com www.pss-a.com the measurement pulse width of 1 ms and it is calculated to be E C -E T ≥ 0.5 eV. Therefore, the obtained pulsed I DS -V GS measurements are sensitive to deeper interface states in energy compared with the frequency-dependent C-V method.
In addition, the V th shift obtained after positive bias stress is not only correlated to interface traps but also to border traps as already reported. [32] In fact, during the stress time both interface states and border traps can be filled and can contribute to the V th instability due to their longer emission time. Even though the separate contributions of border and interface traps cannot be disentangled, an effective interface charge density accounting for D it and border traps can be determined by The n it as a function of the gate stress voltage is also shown in Figure 8 which portrays a reduction of border and interface states for samples fabricated by combining SPC and PMA treatments. The effectiveness of the SPC and PMA treatments to reduce interface states at the Al 2 O 3 /III-nitride interface reveled by the frequency-dependent C-V method is also demonstrated by the smaller relative change with increasing gate bias stress in pulsed I DS -V GS to contribute to the improvement of the electrical properties of the GaN-based MIS-HEMTs under forward gate bias stress.

Conclusion
In summary, high-quality interface in terms of interface trap states between ALD-Al 2 O 3 and GaN-capped AlGaN/GaN heterostructures have been achieved by the combination of an O 2 plasma-based surface preconditioning and N 2 postmetallization anneal. The O 2 plasma-based treatment has been shown to effectively restore the morphology of the GaN surface which is affected by the fabrication processes before the ALD-Al 2 O 3 deposition. Moreover, MIS diodes treated by SPC and PMA showed a smaller-frequency dispersion of the C-V characteristics than the samples without treatment or only SPC applied which indicates a reduction of interface trap states. The D it was estimated to be reduced to a value in the order of 2 Â 10 12 cm À2 eV À1 near the conduction band edge. The reduction of interface trap states was also shown to improve the electrical properties of MIS-HEMTs which showed a better V th stability in pulsed I DS -V GS sweep measurements. www.advancedsciencenews.com www.pss-a.com