Black Phosphorus Nanosheets in Field Effect Transistors with Ni and NiCr Contacts

Herein, the fabrication and electrical characterization of multilayer black phosphorus (BP)‐based field effect transistors with Ni or NiCr alloy contacts are reported. The devices show p‐type conduction and hysteresis in the transfer characteristics that enable their use as nonvolatile memories. The differences between Ni and NiCr contacts are investigated and the Y‐function method is applied to extract the channel mobility up to 112 cm2 V−1 s−1 and the contact resistances. Ni contacts present specific contact resistance of 6.3 k Ω μm that increases to 18.1 k Ω μm for NiCr. These findings are important for the technological exploitation of multilayer BP in a new class of electronic and optoelectronic devices.


Introduction
In the last decade, black phosphorus (BP) has attracted a great interest as a layered material with several important properties, that can be exfoliated up to the monolayer form (phosphorene). [1][2][3][4] BP presents a direct bandgap that ranges from 0.3 eV in the bulk to 2 eV in the monolayer form. [5][6][7] Because of its tunable bandgap, BP is collocated between the transition metal dichalcogenides, which are characterized by large bandgaps up to 3 eV, and the semimetallic graphene with zero bandgap. [8][9][10] Thanks to the high charge-carrier mobility, few-layer BP can be used as channel material of high-speed field effect transistors (FETs). [1,9,[11][12][13][14] Moreover, the tunable and direct bandgap, ranging from infrared to visible frequencies, together with the high absorption coefficient in the ultra-violet (UV) region, make BP a suitable material for optoelectronic applications, such as photodetectors [15,16] and photovoltaic devices. [17][18][19] BP's electronic, optical, and thermal transport properties are highly anisotropic since it presents a strong structural in-plane anisotropy. [20][21][22] The anisotropic properties have already promoted its use in polarized light detectors [23][24][25] as well as in other applications such as synaptic devices. [26] BP has remarkable applications also in the domain of memory devices. [27][28][29] The operation of common nonvolatile memories based on FETs depends on the charge-trapping mechanism that uses a charge-trapping layer to accumulate and retain the electric charge induced by a gate pulse. BP-based FETs can operate as memory devices without the addition of a charge-trapping layer by exploiting trap states present at the BP/SiO 2 interface and in BP's defects. [28] The applications of BP in electronic and optoelectronic devices are mostly limited by its surface chemistry and its interaction with metals used as electrodes. The chemical degradation of BP remains a hard task to overcome. [30,31] BP is highly reactive to oxygen, which spontaneously dissociates on its surface at room temperature, quickly reducing the material quality. [32] Furthermore, the oxidization of BP favors the interaction of its surface with H 2 O molecules, which bind to BP surface through hydrogen bonds. [33] Therefore, to protect the material, the interaction with oxygen must be avoided. There are several strategies to overcome this issue and make BP accessible for electronic applications and fundamental research. [34] Among the most common strategies, the deposition of a protective layer of polymethylmethacrylate (PMMA), which is widely used in laboratories and industries, has proved to be an efficient approach. Another important challenge, common to several 2D materials, is the choice of a metal contact to achieve good ohmic contacts. [35][36][37][38][39][40][41] Indeed, the performance of BP-based FETs depends on the metal used as the source and drain. Telesio et al. investigated BP FETs with contacts made of nickel, titanium, and chromium, and found that Cr makes the contacts more resistive than Ni. [39] In addition, it was demonstrated that vacuum annealing below 250°C can improve the linearity of the output characteristics of BP monolayer-based devices. [42] DOI: 10.1002/pssb.202200537 Herein, the fabrication and electrical characterization of multilayer black phosphorus (BP)-based field effect transistors with Ni or NiCr alloy contacts are reported. The devices show p-type conduction and hysteresis in the transfer characteristics that enable their use as nonvolatile memories. The differences between Ni and NiCr contacts are investigated and the Y-function method is applied to extract the channel mobility up to 112 cm 2 V À1 s À1 and the contact resistances. Ni contacts present specific contact resistance of 6.3 k Ω μm that increases to 18.1 k Ω μm for NiCr. These findings are important for the technological exploitation of multilayer BP in a new class of electronic and optoelectronic devices.
In this work, we report the fabrication and electrical characterization of back-gated BP transistors, either with Ni or NiCr alloy contacts. We observe higher current in Ni-contacted devices than in transistors with NiCr contacts. We extract the contact resistance between the metal and BP by using the Y-function method (YFM) applied to current-voltage measurements in two-probe configuration. The contact resistance of the two metals can be related to the higher density of states of Ni. We also report the dependence of the contact resistance on the gate voltage, showing that the contact resistance increases for positive gate voltage. In both cases, we exploit the presence of trap states to enable non-volatile memories, highlighting memory stability and endurance.
We remark that while Ni has been largely used, NiCr alloy is unexplored for metal contacts in BP transistors. [43][44][45][46] Our findings are important for the technological exploitation of multilayer BP as the channel material in electronic and optoelectronic devices.

Experimental Section
All devices were fabricated following the same procedure and using the same materials, apart from the metals for the contacts. Multilayer BP flakes were mechanically exfoliated by the scotch tape method from bulk BP crystals (by Smart Elements). The flakes were transferred onto a SiO 2 /p þþ -Si substrate (oxide thickness 90 nm). After a standard photolithography process, the Ni and NiCr (50:50 alloy) contacts with a thickness of 5 nm were deposited by electron-beam evaporation with a deposition rate of 0.01 nm s À1 . Subsequently, Au contacts with a thickness of 75 nm were deposited by thermal evaporation with a deposition rate of 0.1 nm s À1 on both devices. All metal deposition processes were carried out at a base pressure of 1 Â 10 À5 mbar. Finally, the devices were covered by a PMMA capping layer with a thickness of about 60 nm to preserve the BP quality. A back-gate contact was formed by covering the scratched area of the degenerate p-type Si substrate with silver paste.
We note that atomic force microscopy (AFM) images of the surface of Au contacts with thicknesses larger than 25 nm are dominated by the surface features of the Au layer, [47] that is, the possibly different growth mechanisms of the underlying Ni and NiCr are not accessible after device fabrication.
Flakes with comparable dimensions were selected for the fabrication of Ni-and NiCr-contacted transistors. Figure 1a  www.advancedsciencenews.com www.pss-b.com depicted in Figure 1c, which were obtained by the AFM measurements (Nanosurf AG, Liestal, Switzerland) performed on the area of the flake of main interest. Specifically, for the device in Figure 1a, the measurements were performed just outside the channel as that part is more representative of the thickness that limits the current flow below the drain contact; for the device in Figure 1b, the thickness was measured in the channel area between S and D, where the flake is more uniform. The PMMA protective capping layer was removed in acetone and isopropanol immediately before the measurements. After that, the unprotected device was kept in the probe station chamber at a pressure below 2 mbar to prevent BP degradation.
The schematic of the device and the measurement setup are reported in Figure 1d. The electrical measurements were carried out at room temperature using a Janis ST-500 probe station connected with a Keithley 4200 SCS having current and voltage sensitivity of about 0.1 pA and 2 μV, respectively. For the electrical measurements, the source was grounded while the drain and/or gate voltages, V ds and V gs , respectively, were swept or stepped to monitor the drain current I d . The current was measured in two probe configurations and includes the effects of the contact resistances. Gate bias was applied on the highly doped Si back-gated electrode.

Results and Discussion
The BP devices with Ni and NiCr contacts were first characterized as field effect transistors by measuring the output (I d -V ds curves at given V gs ) and transfer characteristics (I d -V gs curves at given V ds ). Then, we used the transfer characteristics to extract the BP/Ni and BP/NiCr contact resistance using the YFM (see Appendix). In the end, we investigated their memory behavior by applying sequences of gate pulses while monitoring the drain current at a fixed drain bias. Figure 2a shows the output characteristics at V gs = 0 V of the Niand NiCr-contacted transistors. The linear behavior of the I d -V ds curves suggests that, in both cases, there are ohmic contacts. The linear dependence excludes the presence of Schottky barriers at the interface Ni/BP or NiCr/BP which would result in asymmetric I d -V ds curves. [48][49][50] The two-terminal resistance is R tot % 1.3 kΩ for Ni contacts and R tot % 5.2 kΩ for NiCr contacts. R tot accounts for the channel and the contact resistance; it is the sum of two contributions: R tot ¼ 2R C þ R CH , where R C is the contact resistance between metal and black phosphorus and R CH is the BP channel resistance. [51] R tot suggests that NiCr contacts are more resistive if the channel resistance is comparable for the two devices. However, further investigation will be performed in the following to distinguish between the contact and channel contributions. Figure 2b,c shows the device transfer characteristics with Ni and NiCr contacts, respectively, under a drain bias of 2 mV, over growing loops of the gate voltage, up to AE40 V. The transfer curves show that the channel current increases as the gate bias becomes more negative revealing a p-type conduction for both Ni-and NiCr-contacted transistors. We notice that, at a fixed V gs , the current is about one order of magnitude higher in devices with Ni contacts, confirming the better performance with respect to devices with NiCr contacts.

Transistor Characterization
The transfer curves enable the extraction of the effective charge carrier mobility. The field effect mobility can be obtained from the transconductance of the FET in the linear regime, g m ¼ ∂I d ∂V gs . By considering the maximum slope of the transfer curves, charge carrier mobility was calculated by using the following equation The gate dielectric capacitance per unit area is C ox ¼ 3.84 Â 10 À8 F cm À2 for 90 nm thick SiO 2 substrate. Figure 2d shows the charge carrier mobility as a function of V gs . Both Ni-and NiCr-contacted transistors show a decreasing mobility for higher gate voltages. A gate-dependent mobility has been reported for transistors with 2D or organic channels. [52][53][54][55][56] The plot shows that the transistor with Ni has higher mobility than the one with NiCr contacts (80 cm 2 V À1 s À1 versus 34 cm 2 V À1 s À1 , respectively). Importantly, different contact resistance of Ni and NiCr can significantly contribute to discrepancy between the mobilities of the two devices, as will be discussed next. Impurities located at the interface BP/SiO 2 , intrinsic defects in the material, and residual adsorbates on top of the channel, acting as scattering or trapping centers, can deteriorate the mobility. Furthermore, it has been shown that room-temperature BP mobility decreases with the increasing number of layers and can be below 100 cm 2 V À1 s À1 for more than 20 layers. [57] The achieved mobility is slightly lower than that is typically reported in the literature for similar devices with thinner BP [58][59][60][61] while mobilities up to a factor 5 higher have been reported for BP on a high-k gate dielectric. [62,63] As the BP channel had limited exposure to air during both the fabrication and measurement process, the mobility is mainly affected by interfacial and intrinsic defects as well as the number of layers.
The ON/OFF ratio, reported in Figure 2e as a function of the gate voltage range, ΔV gs , is higher in Ni-contacted transistors, which present better switching behavior. The low ON/OFF ratio is due to the thick flake which is poorly controlled by the gate voltage, consistently with the current increase and ON/OFF ratio decrease recently reported for thicker BP flakes. [64] Similarly, Figure 2f displays the hysteresis width versus ΔV gs for the two types of transistors, showing an increasing hysteresis width for increasing ΔV gs . The hysteresis width, H W , is defined as the gate voltage difference corresponding to the middle current value I m between the ON and OFF state, Hysteresis is due to charges trapped at the BP/SiO 2 interface, in BP at intrinsic defects and in residual adsorbates. [52,56,65] Remarkably, H W grows with ΔV gs , indicating that charge trapping occurs mainly across the SiO 2 capacitor. As measurements are performed in vacuum, BP/SiO 2 interfacial traps and intrinsic defects are expected to be the main charge-trapping centers. We highlight that the two devices show the same H W À ΔV gs trend; the slightly larger H W for the NiCr-contacted device points to an increased charge trapping in the NiCr/BP device, probably due to www.advancedsciencenews.com www.pss-b.com a flake with higher defect density which would also affect the mobility in the way as observed.

Contact Resistance
The field effect mobility μ eff obtained using the maximum transconductance from the transfer characteristic measured in two-probe configuration can be underestimated because it includes the effects of the contact resistance R C 38] . To extract the contact resistance R C from the two-terminal measurements and estimate the field effect mobility deducted by the effects of R C , we applied the YFM that is detailed in the Appendix. The YFM is an effective technique that allows to evaluate R C and the mobility μ 0 , unaffected by R C , from two probe measurements. [66][67][68] The Y-function, defined as Y ¼ I d ffiffiffiffi g m p , was obtained for all the measured transfer curves for both Ni-and NiCr-contacted transistors (Figure 2b,c). As an example, Figure 3a shows the Y-function corresponding to the transfer curves in the range V gs = AE10 V.
The extracted mobility μ 0 as function of V gs is reported in Figure 3b showing that the maximum mobility is now μ 0 ¼ 112 cm 2 V À1 s À1 for BP with Ni contacts and μ 0 ¼ 40 cm 2 V À1 s À1 for BP with NiCr. Compared to μ eff , the subtraction of the contact resistance effects in μ 0 , results in an over 30% increase in the estimated mobility, consistently with previous results on MoS 2 transistors. [69] Similarly, the plots of 1 ffiffiffiffi g m p versus V gs , displayed in Figure 3c, allowed the evaluation of the contact resistance as a function of V gs (Figure 3d). The maximum contact resistance is R c ¼ 218 Ω for Ni/BP and R c = 871 Ω for NiCr/BP. To correctly compare the contact resistances of the two different interfaces, it is necessary to consider the specific contact resistance, that is, the www.advancedsciencenews.com www.pss-b.com contact resistance per unit width, ρ c ¼ R c W, which results 6.3 k Ω μm for Ni/BP and 18.1 k Ω μm for NiCr/BP. Ni contacts exhibit a contact resistance three times lower than their NiCr counterpart. Figure 3d shows also that the specific contact resistance has a weak dependence on the gate voltage. A gate-dependent contact resistance has been reported for several nanomaterials; [38,70] for the devices under study the increase of ρ C for positive V gs can be easily understood considering that a positive gate depletes holes in the materials, yielding a higher resistance. As regards the Ni/BP interface, Du et al. extracted the contact resistance by using the transfer length method at different back gate voltages. [58] At V gs = 10 V, they got a value of 8 k Ω μm, which is higher than the 5.5 k Ω μm estimated by YFM in our case. The metal deposition process has a strong impact on the quality of the BP/metal interface and affects the contact resistance. [71] The growth of metals on BP can result in either a 2D, that is, Frank van der Merwe, or 3D morphology, i.e., Vollmer-Weber, depending on several conditions, such as energetics factors and substrate (BP in this case). From first-principle calculations, it was shown that both Ni and Cr disturb the BP lattice rather strongly. [72] This is in agreement with their similar surface-free energies of %1,700 mJ m À2 [X,Y]. Because this value is way higher than the surface free energy of BP at %100 mJ m À2 [Z], one would expect a strong tendency for a 3D growth for both metals. While the details of the deposition process play a role as well, it seems rather unlikely that the growth mode is the dominant factor for the observed differences. More likely, the differences in the electronic structure, for example, the much larger density of states (DOS) in the case of Ni, [72] play a major role.

BP Transistor Memory
BP has remarkable applications in the field of memory devices. [28,73,74] The presence of deep trap states can be exploited for charge-trapping to enable nonvolatile memories. [75] Due to the large hysteresis width, Ni-and NiCr-contacted devices exhibit a memory behavior. Figure 4a,c shows the transient behavior of the two devices subjected to AE30 V gate voltages pulses. The drain current I d is monitored over time and changes its value according to the V gs pulses. The channel current is set to the lower value by a negative gate pulse and is changed to the higher value by a positive gate pulse. The retention time, that is, the time the current stays in the low/high state, is longer than 40 s. Figure 4b,d demonstrates that the high/low current level switching can be repeated without degradation indicating good endurance. [76] These features make BP-based transistors promising for nonvolatile memory applications. The obvious advantage is that the devices can store charges in nonvolatile way even without a dedicated charge-trapping layer. [77,78] Without adding any charge-trapping layer, but exploiting the intrinsic transistor hysteresis, we demonstrated memory applications for both Ni-and NiCr-contacted devices. Despite the shorter retention time, we highlight the benefits of the easy fabrication procedure and low cost. Moreover, we were able to achieve good endurance and stability even in the absence of a dedicated charge trapping layer. www.advancedsciencenews.com www.pss-b.com 2D materials or carbon nanotubes have been used as materials for the fabrication of memories exhibiting performance comparable or superior to that observed in the presented BP memory. [52,[79][80][81][82] However, we remark that, with an optimized BP device, faster programming and erasing time can be expected due to the higher mobility of BP.

Conclusion
We fabricated back-gated transistors based on BP nanosheets with Ni or NiCr alloy contacts and performed electrical measurements highlighting similarities and differences. Both types of devices show a p-type conduction with a hole mobility up to 112 cm 2 V À1 s À1 . We applied the YFM to extract the contact resistance finding a specific resistance of 6.3 k Ω μm for Ni/BP and 18.1 k Ω μm for NiCr/BP contacts. We argued that the contacts with the NiCr alloy are more resistive likely because of the larger DOS for Ni. The transfer characteristics show hysteresis that was exploited to demonstrate nonvolatile memories. Our results are important for the development of BP-based devices for electronic and optoelectronic applications.

Appendix Y Function Method
The Y-function method (YFM), which was first proposed by Ghibaudo [66] to extract field effect mobility in Si transistor, is based on the use of the transfer curves, I d À V gs , and the transconductance. The technique is valid also in the presence of Schottky barriers at the interface metal/semiconductor. The MOSFET parameters extraction is conducted within the strong inversion regime of the linear region, where the drain current expression is as follows Where W and L are the channel width and length, respectively, C ox is the gate oxide capacitance, μ 0 is the low field mobility, θ is the mobility reduction coefficient, V t is the threshold voltage, and V gs and V ds are the gate and drain voltage, respectively. The threshold voltage V t is determined from the linear variation of the inversion charge with gate voltage. The idea is the construction of a function that does not depend on the mobility attenuation factor θ. Considering the definition of transconductance, g m ¼ ∂I d ∂V gs , that is the slope of the I d versus V gs curve The Y-function can be defined as follows, eliminating the θ dependence Plots of the Y versus V gs curves lead to the determination of the mobility μ 0 , unaffected by the contact resistance. Subsequently, it is possible to extract the θ parameter, which in turn enables the estimation of the contact resistance. Indeed, the mobility reduction factor θ consists of the sum of the contributions from the channel interface θ 0 and the contact resistance θ Ã , θ ¼ θ 0 þ θ Ã . If θ 0 is comparatively negligible, then θ % θ Ã ¼ μ 0 C ox R c W L . To extract θ, Equation (A2) can be rewritten as where G m ¼ W L μ 0 C ox . A fit of 1 ffiffiffiffi g m p versus V gs allows to extract the mobility attenuation factor θ and then calculate R c .