2D Linear Trap Array for Quantum Information Processing

An ion‐lattice quantum processor based on a two‐dimensional arrangement of linear surface traps is presented. The design features a tunable coupling between ions in adjacent lattice sites and a configurable ion‐lattice connectivity, allowing one, for example, to realize rectangular and triangular lattices with the same trap chip. Detailed trap simulations of a simplest‐instance ion array with 2 × 9 trapping sites are presented and the fabrication of a prototype device in an industrial facility is reported on. The design and the employed fabrication processes are scalable to larger array sizes. Trapping of ions in rectangular and triangular lattices and transport of a 2 × 2 ion‐lattice over one lattice period are demonstrated.


Introduction
Trapped ions are one of the most successful platforms for quantum information processing to date, with high gate fidelities and long coherence times. [1][2][3][4][5] Trapped-ion quantum processors have been used to implement quantum algorithms, such as Grover's and Shor's algorithms, [6,7] to implement quantum error correction protocols, [8,9] and have also been successfully employed as quantum simulators, for instance, for the observation of manybody dynamical phase transitions, [10,11] the simulation of particleantiparticle generation in lattice gauge theories, [12] or to calculate molecular ground state energies of simple molecules. [13] Currently, the biggest challenge for trapped-ion quantum processors is to scale-up the number of qubits. One approach toward DOI: 10.1002/qute.202000031 scalable systems is to distribute the quantum register over several trapping zones using a so-called QCCD-architecture (quantum charge-coupled device) [14][15][16] and to eventually modularize the processor. [17][18][19] In such a QCCD processor, each trapping zone contains only a small number of ions that can be manipulated with high-fidelity, while exchange of quantum information among the zones requires splitting, shuttling, and merging of ion strings. [14][15][16]20] Complementary to this approach, one can also couple and entangle ions in different trapping potentials utilizing adiabatic well-to-well interactions [21][22][23][24] or, as recently proposed, broadband pulse sequences with high-power lasers. [25] Following this idea, microfabricated ion trap arrays have been realized in order to create 2D ion lattices on a microchip, [26][27][28][29][30][31] and recently, first quantum simulations have been performed in such a system. [32] Arrays of individual traps have the advantage that the ions are not subjected to excess micromotion, in contrast to 2D ion lattices naturally forming in a single trapping potential. [33,34] In addition, microfabricated trap arrays offer a much finer control of the confining potential landscape and allow one to set the structure of the ion lattice by choice of the electrode geometry and control voltages.
Previous designs of ion-lattice quantum processors have mainly investigated surface point traps as fundamental building block of the trap array. [26,27,[29][30][31] An exception is the work of Tanaka et al., [28] where two parallel linear traps have been used. In our article, we further develop this latter approach: realizing a scalable trapped-ion quantum processor based on parallel linear surface traps. Our design enables tunable site-to-site coupling by combining the concepts of variable radio-frequency (RF) voltages [28,35] with island-like electrodes, where static (DC) voltages are applied. The usage of linear traps as building block of the array thereby offers additional advantages compared to point traps. First, ions can be shuttled along the linear trap axes, giving rise to a configurable ion lattice connectivity and allowing for transport of quantum information, physically encoded in the ions, over large distances through the lattice. These points will be further discussed in the next sections. Second, due to the linear nature of the RF traps, multiple ions can be trapped in each site of the ion lattice without subjecting them to excess micromotion. Storage of multiple ions per site could be useful to increase the dipole-dipole coupling across adjacent sites, [22] thereby reducing the gate time for inter-site entangling operations. Furthermore, one could use sympathetic cooling techniques and apply standard quantum gate operations to ions within one site, [36] potentially allowing for even more complex quantum simulations to be run. Our design employs variable RF voltages to temporarily decrease the ion spacing, allowing for an enhanced site-to-site coupling in the ion lattice. For an array of parallel linear traps, such RF shuttling requires only two independent RF voltages, independently of the array size. This is a drastic reduction compared to our previous work with point trap arrays where the number of required RF voltages scales linearly with the array size. [30] Furthermore, the use of RF voltage tuning allows one to use an ion-electrode separation d that is significantly increased compared to the one required in an array with sufficiently small ion-ion distance and fixed RF voltage. The separation d thereby remains basically constant during RF tuning. This point will be further discussed in Section 2 and in Appendix D. Larger separations d can help reduce the motional decoherence rate (ion heating rate), which is a limiting factor in previous 2D ion lattices. [24] The article is structured as follows: In Section 2, the conceptual design and functionality of the proposed trap array are outlined. In Section 3, we consider a minimal instance array consisting of two parallel linear traps with segmented DC electrodes. This minimal instance design possesses the core functionality of the proposed processor, which we show by trap simulations in Section 3.1. In Section 3.2, we describe the fabrication process and show electrical characteristics of the fabricated trap chips. In Section 3.3, we demonstrate ion-trapping in multiple trapping sites and characterize a trap chip in terms of electric stray fields and motional heating. Future improvements of the trap design and fabrication, as well as an outlook on future designs are discussed in Section 4. This discussion is complemented by simulations of a trap array with 10 × 10 trapping sites, shown in Appendix C.

Conceptual Design
The electrode geometry of the proposed quantum processor is a linear trap array, as illustrated in Figure 1. Colinear rails for radiofrequency (RF) voltage (green) are alternated with segmented rails (blue) that are grounded in the RF domain. This configuration creates parallel linear traps for ions with a spacing s x at a distance d above the chip surface. Within each linear trap, an additional multiwell potential with periodicity s z is established along the z-direction by applying spatially periodic static voltages (DC) on the blue electrode segments. The combination of RF and DC fields thus creates a 2D lattice of trapping sites with trap spacings s x and s z . The quantum states of ions confined within the same trapping site are manipulated using state-of-the-art protocols. [2,16] Quantum operations between ions in adjacent trapping sites, such as entangling gates or effective spin-spin interactions, are realized via the coupling of their motional states. [23] Of central importance for this is the motional coupling strength [22,23] 1 for j = z (coupling along z) 1 2 for j = x (coupling along x) (1) Here, M is the mass of the ions in each site, Q their charge, and z their (resonant) axial frequencies. [37] The motional coupling strength Ω c depends crucially on the trap spacings s x and s z , respectively. This has important consequences for the design of the trap array. For the proposed quantum processor, Figure 1, we can envision two distinct design choices: (i) the ion lattice has small trap spacings with sufficient motional coupling Ω c at all times; (ii) the ion lattice has relatively large trap spacings which need to be temporarily decreased to realize an inter-site quantum operation.
Feasible parameters for design choice (i) would be a trap spacing s j ≈ 40 μm with a coupling rate Ω c ≈ 2 × 1 kHz, as used in ref. [31]. Furthermore, the coupling strength Ω c between any pair of adjacent trapping sites could be tuned by adjusting the values s j . This can be achieved by controlling the RF and DC voltages in the trap array as explained later on. A downside of design choice (i) is the required small ion-surface separation d ≲ s j (see Appendix D for details). Such a close proximity to the trap surface typically entails a large motional decoherence rate (heating rate) Γ h . [38] High heating rates Γ h ≳ Ω c are a serious impediment for realizing inter-site quantum gates with high fidelity. [23,24] While cryogenic trap operation and surface cleaning have been demonstrated to strongly reduce the heating rate, the physical origin of the electric field noise remains unknown, and there exists no general procedure that would guarantee a small Γ h . [38] Even if an ion-surface separation d ≫ s j with a lower Γ h could be realized, for instance by using an electrode geometry different to that in Figure 1, such a trap array would unavoidably have inefficient operating conditions due to the exponential decrease of electrode potentials for distances d much larger than the electrode dimensions. [39] Indeed, trap arrays typically operate in the regime d ≲ s j . [26,27,[29][30][31] For design choice (ii) one picks modest trap spacings s j ≈ (100-150) μm that allow for a larger electrode-ion separation d ≈ s j . The increased distance between ions and trap surface can lead to significantly lower heating rate, since Γ h ∝ d −4 for many sources of electric field noise. [38] In the remainder of this article, we will therefore focus on design choice (ii). The potential reduction in ion heating rate is traded for having only small motional coupling strengths Ω c ≈ 2 × 100 Hz between adjacent trapping sites (cf. Equation (1)). Quantum operations between adjacent trapping sites hence need to be realized in a sequential fashion using ion-shuttling operations that temporarily decrease s j . This is illustrated in Figure 2. Starting from the default configuration (Figure 2a), the trap spacing s x can be strongly reduced by lowering the RF voltage on the RF rail between two adjacent trapping sites (bright green) (Figure 2b). Similarly, adjacent ions can be brought close along the axial direction z by adjusting the DC Figure 2. Tunable ion-ion interactions and configurability of the lattice. In the default configuration, ions (red spheres) are stored on a rectangular lattice (a). The distance s x between adjacent trapping sites along x is controlled by adjusting the RF voltages (b). Similarly, the DC voltages are adjusted to control the distance s z along the z-direction (c). These shuttling operations can be applied to multiple trapping sites simultaneously. A small distance facilitates the creation of entanglement between adjacent ions (white lines). After a sequential application of entangling operations, a nearest neighbor connectivity can be established on the rectangular lattice (d). Additional shuttling operations of every second column of ions by one lattice period along z, with subsequent entangling operations along x, allow for the creation of a triangular lattice connectivity (e).
voltages on the DC segments (Figure 2c). At a reduced distance s j = (30-50) μm, coupling strengths Ω c in the kHz range can be achieved, sufficient for coherent operations. [21][22][23][24] The ability to reduce the trap spacing can now be employed to sequentially realize inter-site quantum operations such as entangling gates: Once the desired coupling strength is reached, the secular modes are tuned into resonance and the ions' electronic states are entangled under simultaneous irradiation with laser light (see e. g., ref. [23]). Parallelized entangling operations of pairs of nearest neighbor ions across the array are possible using a global laser field; unwanted coupling between non-nearest neighbors could be drastically reduced by choosing different resonance frequencies for adjacent pairs, [21][22][23]40] as outlined in Appendix E. Subsequently, the lattice spacing is restored to the original value. Entanglement between all nearest neighbors on a rectangular lattice of ions, illustrated in Figure 2d, can thus be created using four parallelized shuttling-steps. We emphasize that the ion entanglement, once established, does not depend anymore on the physical arrangement of the ions. This enables the realization of different lattice connectivities using additional ion-shuttling operations along the trap axis z. For instance, starting from the connected rectangular lattice, a shift of ions by one lattice spacing along z followed by additional entangling operations along x allows one to establish a triangular lattice connectivity, illustrated in Figure 2e. In a similar fashion, z-translations of ions can be used to enable entanglement between more distant ions, for example, next-nearest neighbors on the rectangular lattice or even ions at different ends of the lattice.
The sequential coupling scheme outlined above is useful for various applications. For instance, the motional coupling between ions in adjacent trapping sites could be used for the simulation of spin models in a sequential way (digital quantum simulator). [23,41] Another possibility might be to extend recent studies of entanglement propagation in a linear ion chain [42] to a 2D ion lattice. Furthermore, one could create cluster states by applying a controlled phase gate (e. g., realized by an entangling operation and single qubit rotations) to every pair of neighbor-ing sites in the rectangular ion lattice. [43] The cluster states could then be used as a resource for a measurement-based quantum processor. [44] In addition to qubit-qubit operations across adjacent trapping sites, the envisioned quantum processor will need single qubit gates, requiring laser-addressing of individual trapping sites. For small and moderate-sized arrays, this could be achieved with a Raman gate, [45] employing a crossed Raman beam geometry to address a specific ion. Cross talk could be reduced by moving untargeted ions along the trap axes, out of the beam path. For larger arrays, more scalable solutions will eventually be required: integrated optics such as waveguides with Bragg couplers integrated into the trap chip, [46] or global microwave radiation fields in combination with magnetic field gradients. [47]

Simplest Instance: Linear Twin-Trap
The simplest instance of the linear trap array outlined in the previous section is given by two parallel linear traps with segmented DC electrodes, referred to as linear twin-trap in what follows. Figure 3a gives an overview of the electrode geometry. The twintrap has a central region, surrounded by four identical quadrants (NW, NE, SW, SE). Confinement in the radial (xy-) plane is produced by the three RF rails (green), that stretch over the entire length of the trap. In between the RF electrodes, there are two segmented DC rails with segment lengths l DC , (Figure 3b). The RF and DC rail widths w o , w i, and w DC are optimized for maximum trap efficiency , which also leads to close-to-optimal trap depth. [48,49] Within each trap quadrant, the DC segments are periodically connected as indicated by the different tones of blue. This enables the creation of multiwell potentials for axial confinement along the z-axis with a lattice spacing s z = 3 l DC . Additional outer DC electrodes at the edge of the structure (dark blue) are needed to overlap the two DC multiwells with their respective RF null. Within each trap quadrant, the DC segments and outer DC electrodes can be controlled independently. The periodic assignment of voltages to the DC segments, shown in Figure 3b, allows one to control the DC multiwells with only 4 DC channels each (3 DC segments and 1 outer DC). Furthermore, the DC multiwells in the left and right linear trap can be independently translated along the z-axis, as required for establishing different lattice connectivities. Ion transport within one linear trap thereby employs the periodicity of the DC segments, similar as in other surface trap designs. [50,51] The independent transport in two parallel linear traps relies on the fact that the left multiwell is mainly controlled by DC segments in the left linear trap, while the segments in the right trap have a significantly weaker influence due to the larger spatial separation, and vice versa. This principle should be easily extendable to a larger number of parallel traps.
The DC islands at the trap center, shown in Figure 3c, are further split in three segments of length l DC ∕3, and also the outer DC rails have an independent segment of length l DC,D . The finer segmentation in this axial interaction zone allows one to reduce the lattice spacing s z locally for the central pairs of trapping sites. Alternatively, the three central segments can be treated as one electrode of length l DC for a seamless transport of the DC multiwells across the central region during axial shuttling operations.
The twin-trap design ( Figure 3) is similar to the trap used by Tanaka et al., [28] where parallel ion strings with different RF configurations, leading to different string distances, were demonstrated. We extend that work by adding segmented DC electrodes, which is indispensable for a scalable design and requires multilayer fabrication techniques (described in Section 3.2). The segmentation of the DC rails is also essential to investigate the core functionality of our approach: nearest neighbor interactions within the ion lattice in two spatial dimensions and a configurable lattice connectivity. In ref. [28], different RF amplitude values have been realized using mechanically tuned capacitors. In contrast, the realization of entangling operations in the twin trap design requires to dynamically adjust the RF amplitudes. Dynamic control can be achieved using two phasestabilized RF resonators [30] ; a prototype of such an electrically tunable resonator that can be operated at cryogenic temperatures is described in ref. [49]. We note that the number of required RF resonators does not scale with the size of the trap array (see the section on RF shuttling in Appendix C).

Trap Simulation
We demonstrate the functionality of the twin-trap design by trap simulations, [52][53][54] considering 40 Ca + ions. First, we analyze the trap confinement in the default configuration of a rectangular lattice with 2 × 9 sites and trap spacings s x ≈ 105 μm and s z ≈ 306 μm. Second, we characterize an independent axial translation process where the two adjacent DC multiwells are shifted continuously over one lattice period relative to each other. Such translations are a key requirement for the envisioned configurable lattice connectivity. Third, we simulate tuning of the trap spacings down to values s x = 40 μm and s z = 50 μm, respectively, giving rise to a motional coupling rate between single ions in adjacent sites of Ω c ≳ 2 × 1 kHz in both directions. For all simulated configurations, we obtain suitable trapping parameters, that is, secular frequencies on the order of 1 MHz, a trap depth of several tens to hundreds of meV, and required voltages of U RF ≈ (100-400) V at RF and a few to a few tens of V DC.

Default Trapping Configuration
In the default trapping configuration, the inner and outer RF rails are set to the same RF voltage and the DC voltages are applied periodically across all DC segments, with a mirror symmetry between the left and right linear traps. Details on the calculation of DC voltage sets are given in Appendix A. The total confining potential Φ in this configuration is shown in Figure 4. The potential has 18 individual trapping sites that are arranged in two columns along the two RF nulls, forming a rectangular lattice with trap spacings s z = 306 μm and s x = 105 μm (the sites at |z| ≈ 1500 μm are not confined). The ion-surface separation is d ≈ 120 μm. An RF voltage of U RF = 142 V at Ω RF = 2 × 23 MHz yields a stability factor q = r √ 8∕Ω RF ≈ 0.4, where r is the radial frequency in absence of DC fields (details of the determination of RF parameters are given in Appendix A). The DC voltages for axial confinement are on the order of 1 V and give rise to an axial frequency z = 2 × 1.0 MHz. The DC confinement leads to a splitting of the radial frequencies, r,1 , r,2 = 2 × (3.1, 3.3) MHz, and causes a tilt r = 41.2 • of the radial modes with respect to the vertical direction y. The tilt allows for almost equal laser cooling conditions for both radial modes, assuming laser beam propagation parallel to the trap surface. The axial mode is aligned with the z-axis, z = 0. The trapping sites are separated from each other by multiwell barriers U (l) mw = U (r) mw = 59 meV along the z-direction and the RF barrier U b = 48 meV along the x-direction. The barrier U 0 = 102 meV defines the global trap depth for ions in radial direction. These trap depths are significantly higher than the depths in other ion-lattice processors, [31] and allow for an operation of the trap at room temperature. Deviations in the trapping parameters across the lattice due to finite-size effects are relatively small, with variations of the secular frequencies of about 10 kHz and of the radial mode tilt r by about 5 • . The biggest deviations are found at the outermost sites, z ≈ ±1230 μm, where the trap depths U 0 and U mw are reduced by about 25%. The outermost sites are also slightly displaced from the RF null leading to a residual RF electric field E ∥ ≈ 730 V m −1 in the laser plane (xz). This field causes excess micromotion with a micromotion modulation index = kz mm ≈ 0.73, [55] where z mm is the micromotion amplitude and k is the wavenumber of the 729 nm laser beam driving the 4 2 S 1∕2 ↔ 3 2 D 5∕2 qubit transition in 40 Ca + . For the next inner trapping sites, z ≈ ±920 μm, the shift off the RF null is already notably smaller, with E ∥ ≈ 270 V m −1 and ≈ 0.27. These finite size effects result from the finite lengths of the RF rails and the fact that DC fields calculated for the central sites are non-ideal for sites at the trap edges. In future trap designs, such effects could be reduced by increasing the number of independent DC segments and by elongating the RF rails.

Independent Axial Translations
One of the goals of the twin trap is to demonstrate a configurable ion lattice connectivity, for example, switch from a rectangular to a triangular lattice. This requires that ions in the left and right linear traps can be moved relative to each other along the trap axis z by at least one lattice period s z . The ions in each linear trap are confined in DC multiwell potentials created by the periodic assignment of voltages to the DC segments. The basic principle of independent axial translations in this setup is illustrated in Figure 5a.
Grouping the DC electrodes in eight groups (six periodically repeating segments and two edge electrodes), as indicated by the different segment colors, we calculate voltage sets that simultaneously create axial confinement for two trapping sites at axial positions z These voltages, displayed for electrodes DC1l and DCEl, are on the order of (1-10) V. [56] The axial frequency, shown in Figure 5d, maintains the nominal value z = 2 × 1 MHz with high accuracy for all pairs of positions. The radial modes (Figure 5e,f) show a variation of ≈10% across the full parameter space. [57] Other trap parameters (not shown) show slight variations as well. For instance, the radial mode tilt relative to the y-axis varies between r ≈ 30 • -40 • . For the trap depths, values U b , U mw > 48 meV, and U 0 > 98 meV are maintained, similar to the default configuration. More information is given in ref. [49]. We note that one can choose the axial frequencies z independently, even to the point that one multiwell is switched off. However, trap depths are maximized when both multiwells are operated with similar z .
Any trajectory through the simulated parameter space (z (l) 0 , z (r) 0 ) ∈ [−s z ∕2, +s z ∕2] 2 corresponds to a specific axial translation process. The ability to maintain the multiwell confinement for the entire parameter space demonstrates that translation processes with arbitrary multiwell positions are possible. Furthermore, the simulation of such a wide range of control parameters has the advantage that promising parameter space trajectories, for instance those with a minimal variation in secular frequency or mode tilt, can be quickly identified. However, the approach does not deliver a time-dependent voltage sequence that implements a specific temporal dependence z  Typically, the aim is to maintain low motional excitation during the shuttling (adiabatic transport) [58,59] or to cancel excitations at the end of the sequence (diabatic transport). [60,61] The full parameter scan presented here may serve as a starting point for the calculation of such sequences.
We emphasize that the grouping of DC segments significantly reduces the required number of DC control voltages for axial translation processes. In the present design, only eight control voltages are needed to independently move the two multiwells over arbitrary distances. Other adjustments of the trapping potential can be realized using additional groups of segments, foremost the independent segments in the axial interaction zone that allow one to reduce the trap spacing s z (see next section). In future designs, one could add even more DC segments to improve on the control of the trapping potential at individual sites, for example, for micromotion compensation and secular frequency adjustments.

Adjustment of Trap Spacings
The creation of entanglement between ions in adjacent lattice sites requires a reduction of the trap spacings to enhance the coupling rate Ω c . Along the x-direction, the trap spacing s x is reduced by attenuating the RF voltage U (i) RF on the inner RF rail relative to the voltage U (o) RF on the outer RF rails. Figure 6 shows the trapping potential in such an "attenuated RF" configuration for a reduced trap spacing s x = 40 μm. The axial multiwell confinement is preserved for all 18 trapping sites with an axial frequency z = 2 × 1.0 MHz. The corresponding motional coupling rate for two 40 Ca + ions in adjacent trapping sites across the RF barrier is Ω c = 2 × 1.4 kHz (cf. Equation (1)). The RF double well potential, shown in the inset (Figure 6b), is well defined with a radial barrier of U b = 8.5 meV. [62] The required RF voltages in this configuration are U RF on the outer rails, required by the decreased efficiency of the trap, significantly improves the trap depth to U 0 = 702 meV. Other trap parameters are similar to the default configuration. The radial frequencies are r,1 , r,2 = 2 × (3.1, 3.3) MHz, the multiwell barrier is U mw ≈ 60 meV. The axial mode remains aligned with the z-axis, z = 0, and the radial mode tilt is r = 10.2 • . The DC voltages required to sustain the axial multiwell potential remain on the order of 1 V. We note that the trap spacing s x slightly differs along the trap axis, with values s x = 40 μm at the trap center, z = 0, and s x ≈ 43 μm at the outermost sites, z ≈ ±1200 μm. The difference in trap spacing is caused by finite size effects in the trap and leads to a variation in coupling strength of about ΔΩ c ≈ 2 × 0.3 kHz. The finite size effects could be decreased in future designs (see section 3.1.1).
Along the axial direction, the trap spacing s z can be reduced in the axial interaction zone at the trap center where the DC island electrodes have a finer segmentation. Ions outside the interaction zone remain in a periodic DC multiwell potential as in the default configuration. Figure 6c shows the confining potential for a configuration where the axial distance in the interaction zone is reduced to s z = 50 μm; Figure 6d shows a magnified view of the two central sites forming a double well. These sites have radial frequencies r,1 , r,2 = 2 × (3.1, 3.3) MHz identical to the default configuration. The axial mode has a frequency z = 2 × 0.91 MHz and is tilted by z = 8.0 • relative to the z-axis (currently, z is an unconstrained parameter, which could be improved in future designs by adding additional DC electrodes). The central sites are separated from each other by an axial double well barrier U (ax) b = 1.1 meV, shown in (Figure 6e). The expected motional coupling between single 40 Ca + ions in these sites is Ω c = 2 × 1.5 kHz, (cf. Equation (1)). The axial frequencies in the two central sites can be tuned independently. Micromotion compensation, however, is limited to shifting both sites simultaneously due to the small axial separation s z = 50 μm. On the other hand, given that s z is substantially smaller than the ion-surface distance d = 120 μm, stray fields should be relatively homogeneous across the two sites. Due to the condition s z < d, the double-well potential in the axial interaction zone is not created efficiently, and up to 34 V must be applied to the central DC segments. The outer 16 trapping sites, |z (o) 0 | ≳ ±459 μm, are maintained by the periodically connected DC segments with trapping parameters similar to the default configuration. We note that the configuration with reduced axial distance (Figure 6c) can be seamlessly transformed to the default configuration in Figure 4 using a two-stage shuttling process. In the first step, the initial separation s z = 50 μm between the innermost sites is increased to 306 μm = 3l DC , realizing a multiwell configuration with constant lattice spacing across the entire length of the chip. The second step then uses an axial translation of the ion lattice to shift the central multiwell site into the origin at z = 0.

Trap Fabrication
The linear twin-trap design requires multiple metal layers and vertical interconnect access (via) due to the presence of island-like electrodes. The fabrication is carried out at the industrial facilities of Infineon Technologies in Villach, Austria. In general, our fabrication is similar to the CMOS foundry processes recently used for ion traps. [63] However, while typical CMOS processes are set up for low-voltage logic applications, our processes are optimized for high power and high current applications more suited for ions traps. We also employ a dedicated workstream for the trap fabrication and are therefore not affected by the requirements of other technologies on the same wafer. Established design rules, continuous process monitoring, inline testing, and analysis capabilities provide high precision and reproducibility of the devices. For the fabrication of a prototype version of the linear twin-trap, 90 process steps were applied on top of a 725 μm thick silicon substrate [64] to produce six main functional layers as sketched in Figure 7: First, a 1300 nm thick SiO 2 layer is created by thermal oxidation of the Si substrate. This bottom oxide has low defect density and low interface roughness and serves as electrical insulation between substrate and the metal 1 layer. Subsequently, three metal layers are deposited, separated by two 2200 nm thick inter-metal oxide layers (imox). The 750 nm thick metal 1 layer provides i) shielding of the substrate from RF fields and lasers, [63] and ii) shielding of the ion from charge fluctuations in the substrate. The 1000 nm thick metal 2 layer is mainly used for routing of the island-like electrodes to the bonding pads. Metal 3 has a thickness of 2000 nm and defines the trap electrodes.
All metal layers are made from AlSiCu, an alloy consisting mainly of aluminium. 1% silicon and 0.5% copper are included to suppress eutectic mixing with the silicon substrate and to increase the resilience to high currents, respectively. The metalization for electrodes and routing has to be low-ohmic in order to minimize RF pickup voltages on the DC electrodes, to minimize Johnson noise, and to minimize heating of the RF rails by capacitive loading currents during trap operation. The imox layers consist of SiO x , x ≈ 2, created by low-temperature plasma deposition since the thermal budget of AlSiCu is limited to a maximum temperature T max ≈ 400 • C.
Standard optical lithography followed by etching is performed to define the structures within each layer. Vias between the metal layers are defined by etching a funnel-shaped aperture into the separating imox layer which guarantees reliable coverage of the vias' sidewalls by the upper metal. The structuring of the imox layers is optimized using a focus exposure matrix. In order to guarantee process stability, in-line data of layer thicknesses, critical dimensions, reflectivities, and overlay precision are measured and recorded automatically.
After mechanical dicing into individual chips, electrical analysis (resistance and DC breakdown measurements at room temperature and T ≈ 20 K) as well as physical analysis (inspection of cross sections) are performed for quality control. The cross section of a via between metal 2 and 3 is shown in the scanning electron microscope (SEM) image in Figure 8. In order to provide high material contrast, the sample has been cut and polished followed by a 10 s exposure to hydrofluoric acid which etches a few nanometers of SiO x and emphasizes the material boundary of SiO x . Finally, the sample is sputter-coated with about 2 nm of palladium to maximize the total contrast in the SEM image. The cross section confirms the reliable via connection between metal 2 and 3.
A microscope image of the full prototype device is shown in Figure 9a. The 80 trap electrodes (bright) in the metal 3 layer are separated by 9 μm-wide gaps (dark) and are connected to the bonding pads on the left and right sides of the chip. Vias and traces in lower layers are visible due to the surface topology of the chip. Figure 9b shows a magnified view of the island-like DC segments DC1, DC2, and DC3 in one of the trap quadrants. Every third segment is connected to the same lead on metal 2, as required for the creation of DC multiwell potentials and axial translations. The color code in Figure 9c and in the cross section (Figure 9d) illustrates the routing to the DC segments on metal 2. RF-pickup on the segments is minimized by two measures: First, vias at both ends of each segment reduce the lead resistance R lead, since the metal 2 and metal 3 layers are routed in parallel. Within the segmented rail region, the calculated reduction of the lead resistance is about 27%. Second, additional shield electrodes connected to GND reduce the parasitic coupling capacitance C p between the DC segments and the adjacent RF electrodes. We quantify the shielding with finite element simulations of a trap cross section: The presence of the metal 1 GND layer reduces C p by about 92%; the grounded shields on metal 2 lead to an additional reduction of about 19%. To further minimize the coupling capacitance, crossing of DC leads below the RF rails is avoided whenever possible. Figure 9e shows a magnified view of the axial interaction zone at the trap center. The routing to the individually connected central DC segments has to cross the RF rails, as shown in Figure 9f,g. Therefore, the routing is moved to the metal 1 layer to make room for a shield electrode on metal 2. This minimizes RF-pickup on the lines while maintaining the screening of the Si substrate from laser light. From finite element simulations, we estimate a parasitic coupling capacitance to the RF rails of C p ≲ 0.01 pF for any DC electrode.
The trap chips are produced on wafers with a diameter of 200 mm (8"), holding more than 700 chips. Multiple trap geometries are fabricated simultaneously. In addition to the design with ion-surface separation d = 120 μm described in this article, a slightly adapted geometry with d = 80 μm is on the wafer. Additionally, both electrode geometries are realized in two versions. In one version, metal 1 is unstructured, apart from the routing to the central DC segments. The continuous metal  1 layer ensures shielding of the substrate from laser light and reduces the penetration of RF fields into the substrate. [63] In a second version, about 79% of the metal 1 layer is removed below the RF electrodes. This trades substrate shielding for a lower capacitance of the RF lines (≈11 pF instead of ≈29 pF, estimated from a parallel plate capacitor model), allowing for a larger voltage gain of a step-up resonator, [65] provided the substrate has negligible RF loss. [66][67][68] The wafer layout also contains structures dedicated to the electrical testing of the resistivity of the metal layers and of the resistances of the intermetallic vias. These quantities are used to estimate the amount of RF pickup and Johnson noise on the trap electrodes. The layer resistivities and via resistances are determined in a 4-wire measurement at T ≈ 20 K. [69] The results are listed in Tables 1 and 2. We find reproducible values of the AlSiCu bulk resistivity of ≈ (2.4-2.6) × 10 −9 Ω m, which is comparable to other low-resistivity alloys of aluminium at T = 20 K. [70] The via resistance depends on the aspect ratio of the metallized via sidewalls and the distance between the connected metal layers. Vias connecting metal 1 to metal 3 are realized with one metal 2 to metal 3 via and two metal 1 to metal 2 vias in parallel to reduce the resistance. All via resistances are on the order of a few mΩ, demonstrating a good electrical connection across metal layers. [71,72] From the measured resistances, we estimate the amount of Johnson noise on the trap electrodes and the corresponding heating rate for a trapped ion (details in Appendix B). The dominant contribution to the Johnson noise seen by an ion comes from the metal 2 leads for the periodically connected DC segments. These leads have a resistance of R lead ≈ 0.46 Ω at T ≈ 20 K; the via resistances can be neglected. The axial ion heating rate caused by Johnson noise across R lead is Γ (JN) h ≈ 0.015 phonons∕s, calculated for a 40 Ca + ion with an axial frequency of z = 2 × 1 MHz (in radial direction the heating rate is on the same order of magnitude). Such a low heating rate is negligible for all practical purposes.
The RF pickup voltage U p on the DC electrodes is estimated from an electrical model, considering the electrodes' grounding in the RF domain (details in Appendix B). Large pickup voltages can induce significant RF electric fields at the ion position, which in turn result in excess micromotion that cannot be compensated. [55] We estimate a very small amount of RF pickup | p | = |U p ∕U RF | ≈ 1 × 10 −6 , where U RF is the applied RF volt-age at a frequency Ω RF = 2 × 25 MHz. Excess micromotion from the corresponding RF electric fields should therefore be negligible.
The maximum required RF voltages on the trap are about U RF = 400 V, needed in the configuration with reduced trap spacing s x between the two linear traps (cf. Section 3.1.3). For a reliable trap operation, the dielectric imox layers need to withstand such RF voltages without electrical breakdown. We measure the DC dielectric breakdown voltage between metal layers 2 and 3 directly on the d = 120 μm prototype chips at room temperature and in vacuum. From a set of ten devices, we observe dielectric breakdown voltages of 800 V < V BD < 1000 V. This is in reasonable agreement with the typical dielectric strength 5.6 MV cm −1 of sputter-deposited SiO 2 , [73] given the ≈2 μm thickness of the imox layers. Furthermore, the measured V BD is well above the required voltage of 400 V assuming similar dielectric breakdown mechanisms for DC and RF.

Trap Characterization
We have performed tests of the fabricated linear-twin traps by means of ion measurements with 40 Ca + ions. The tests include trapping and axial translations of multiple ions, as well as a characterization of stray electric fields and heating rates. The experiments are performed in a closed-cycle cryostat with a base temperature of T ≈ 10 K, [74] while the ion trap is at an operation temperature of T ≈ 50 K. The elevated temperature of the trap is due to RF absorption in the Si substrate at the location of the RF rails' bonding pads, where there is no grounded shield layer on metal 1. This heating effect could be significantly reduced in future designs by extending the metal 1 shield layer to the bonding pads, thereby inhibiting the RF field penetration into the substrate while adding only slightly to the trap capacitance. 40 Ca + ions are produced from a neutral atom flux by a two-step photoionization process using overlapped laser beams at 422 and 379 nm wavelength. In order to cool the ions into the motional ground state, we use Doppler and resolved sideband cooling techniques. [75] The 4 2 S 1∕2 ↔ 4 2 P 1∕2 dipole transition at 397 nm is used for Doppler cooling and detection. The 4 2 S 1∕2 ↔ 3 2 D 5∕2 quadrupole transition at 729 nm is used for resolved-sideband operations and spectroscopy. Additional lasers at 866 and 854nm are employed to repump population from the D states back to the P levels. The 397, 866, and 854nm beams are shaped by a set of cylindrical lenses to obtain highly elliptical beams with a beam waist w 0 ≈ 900 μm in the horizontal plane and (20-30) μm in the vertical direction. These elliptical beams are used to cool and image ions in multiple lattice sites simultaneously, as well as during ion shuttling. All other laser beams are circular and address a single trapping site at a time. For trap operation, we apply an RF amplitude U RF ≈ 180 V at 25 MHz to all three RF rails, resulting in radial frequencies r ≈ 2 × (2-3) MHz. Axial multiwell confinement with z ≈ 2 × 1 MHz is achieved by applying DC voltages on the order of 1 V, using the segment connectivity shown in Figure 5a: The periodic assignment of voltages to the DC segments is extended across the entire length of the trap chip to allow for seamless axial translations of ions in the left and right linear trap. However, due to a short in one of the cables of the cryostat, electrodes DC2l and DC2r had to be connected to the same supply line. Thus, the freedom of moving the two chains independently was limited in the experiments.
In a first experiment, we investigate the ability of the twin-trap to confine ions in different lattice configurations. Figure 10 shows images of ions, simultaneously trapped in multiple trapping sites. The ion-surface separation is d = 120 μm. In Figure 10a, six ions are trapped in a rectangular lattice with trap spacings s x ≈ 100 μm and s z ≈ 300 μm. Ions at the center (sites 1 and 2) are brighter than the ions further out, mainly due to a small tilt of the major axis of the elliptical imaging beam relative to the trap surface and partly due to different micromotion conditions. Figure 10b shows five ions trapped in a triangular lattice configuration, which results from the rectangular lattice in Figure 10a by a shift of the left and right DC multiwells by a quarter lattice period in opposite directions. To trap ions in multiple lattice sites, we employ a combination of two loading techniques. First, the two photoionization beams at 422 and 379nm are sequentially directed to the trapping sites where single ions are to be trapped. Loading ions in some of the trapping sites was difficult, which we attribute to stray electric fields. These sites were filled using shuttling of ions from adjacent sites.
We further demonstrate shuttling of an entire ion lattice: In Video S1, Supporting Information, we show a simultaneous translation of a rectangular lattice of four ions over a distance of one lattice period, s z = 306 μm. While all ions remain trapped during the transport, three of the four crystallized ions temporarily melt. This mainly happens due to an asynchronous update of the different DC voltages provided by the supply; in parts also due to a variation of the stray electric field. We emphasize that during the shuttling we applied only a constant, global micromotion compensation field. The successful transport thus indicates a relatively constant stray electric field over the entire shuttling distance of 600 μm. A total of only eight DC control voltages is used for the shuttling process. The low shuttling speed of about 6 μm s −1 is limited by the slew rate of the stable DC voltage supply used to drive the electrodes. After several weeks of trap operation, we observed a substantial change of the stray electric field, resulting in ion loss during shuttling operations. Using a single ion as a probe, we characterized the spatial variation of the stray electric field at sites 4, 2, and 5 (cf. Figure 10a). The measurement is done by adjusting the micromotion compensation voltages to maximize ion fluorescence at 397 nm close to the atomic transition frequency. The stray field is then given by the compensation field, with opposite sign. The data, listed in Table 3, reveal that the stray field component E x in the central site 2 has a five times larger amplitude than in sites 4 and 5 and is pointing in opposite direction. The component E y is significantly smaller than E x and approximately constant for all sites. The precision of the measurement of E y is lower than that of E x . The 397 nm beam used to detect stray-field induced micromotion propagates in the xz-plane, parallel to the trap surface, and is not sensitive to micromotion in the y-direction. One axis of the RF quadrupole field is tilted by only ≈ 22 • from the y-direction.
In addition, ions could be loaded in sites 1 and 2 at the chip center without applying axial confinement. The residual axial frequency z ≈ 2 × 600 kHz, independent of the applied RF voltage, stayed approximately constant over the whole trap operation period. As zones 1 and 2 where often used for ion loading, this stray confining field may have been caused by laser-induced charges or by inhomogeneous contamination arising from the loading process. [76][77][78][79]  Finally, heating rate measurements were performed to further explore the potential of the linear twin-trap prototype for ionion coupling. The measurements were taken in sites 1, 2, and 3 (cf. Figure 10a) using the sideband-ratio method. [75] The results are listed in Table 4. The measured values, obtained at axial frequencies z ≈ 2 × (1.2-1.5) MHz, are in a range Γ h ≈ (100-500) phonons per second for the three trapping sites. Given the targeted ion-ion coupling rate Ω c ≈ 2 × 1 kHz, these heating rates should allow the observation of ion-ion coupling on a few quanta level. [21,22] However, to harness the coupling for spin-spin interactions or high-fidelity entangling operations between ions in adjacent sites, a significantly lower heating rate would be required. A further characterization is necessary to determine whether the measured heating rates are limited by technical noise that could be filtered out or by surface noise. In fact, surface contamination is a possible reason for the high heating rates. While the trap chip has been cleaned of photoresist residues and dicing debris at the Infineon facilities, no further cleaning steps were done prior to loading into the vacuum chamber. Additional chemical cleaning or ex situ surface treatments [80,81] could lower the observed heating rates. Also, a change in electrode material from AlSiCu to a noble metal might significantly reduce the experienced heating due to the absence of native oxide layers. [82] We currently work on a new chip version with gold electrodes. Another option would be in situ cleaning of trap electrodes by argon ion bombardment, which has been reported to drastically lower the heating rate. [83,84]

Conclusion
In summary, we have proposed, built, and operated a new design of an ion-lattice quantum processor based on 2D arrays of linear surface traps. A core aspect of our approach is the usage of ion-shuttling operations in two spatial dimensions that enable a dynamical configuration of the ion lattice in terms of lattice connectivity and ion-spacing. The latter enables tunable interactions between ions in adjacent lattice sites. We have shown the feasibility of our approach by means of detailed trap simulations of a simplest-instance version, consisting of two parallel linear traps with 2 × 9 trapping sites. The simulated trapping potentials facilitate interaction strengths between ions in adjacent sites in the kHz range, while maintaining a moderate ion-surface separation d = 120 μm to keep the electric field noise low. We demonstrate the scalability of this design with additional simulations of an array with 10 × 10 sites, shown in Appendix C. We have built several versions of the 2 × 9 array in an industrial facility using multilayer microfabrication. The employed fabrication processes are compatible with further scaling-up the array size where the growing number of island-like electrodes will require a more dense routing: Up to six metal layers can readily be realized, and even more layers are possible by adding planarization steps. In the fu-ture, our CMOS fabrication process could also be extended to include waveguide structures for integrated optical addressing of single ions and pairs of ions. [46] We have experimentally demonstrated the basic operability of a prototype device with 2 × 9 trapping sites, showing simultaneous trapping of ions in multiple lattice sites, DC voltage-controlled shuttling, and resolved-sideband operations (heating rate measurements). The cooling beams were elliptical to cover multiple trapping sites at once; in the future, steerable beams or multiple beams [85] may be employed to reduce the optical power needed. We have further demonstrated the ability to configure the ion lattice, showing trapping in a rectangular lattice and a triangular lattice configuration and translation of an entire ion lattice by one lattice period. This configurability is only possible in a linear trap array and is one of the principle points of our design. For shuttling along the trap axis, we have employed a periodic voltage assignment to the trap's DC segments, which allows one in principle to axially transport ion sub-lattices over arbitrary distances using only a small number of DC control voltages. The shuttling speed, being currently limited by the stable DC supply, could in the future be increased by orders of magnitude using a faster supply. [58,60,61] Axial translations can also be employed as a technique for fast sequential loading of an entire ion lattice: Ion loading takes place at one dedicated site per linear trap and loaded ions are subsequently shuttled together with all other ions in the multiwell to the adjacent site using axial translations (cf. Section 3.1.2). This technique does not require ionization beams to be steered across the array and could be combined with a precooled source of atoms to further increase the loading rate. [29] A draw-back of the periodic voltage assignment is the limited control of the trapping potential at different lattice sites. Lattice translations in our prototype design using only a global micromotion compensation field were successful at first, but were eventually limited by a spatially-varying stray electric field. Indeed, we find the vulnerability to stray charges to be the biggest limitation of our prototype device. This problem can be tackled in future chip versions: First, the creation of stray charges on exposed dielectrics can be inhibited by reducing the electrode gap size (currently 9 μm) and by using a noble metal for the top metal layer, for example, gold. Second, the electrode design can be adapted to allow for a larger number of control electrodes for independent micromotion compensation in more lattice sites. Another limitation of our prototype device is the relatively high heating rate Γ h ≈ (100-500) phonons per second at z ≈ 2 × 1.5 MHz, which is only slightly smaller than the targeted ion-ion coupling rate Ω c ∼ 2 × 1 kHz. Such a heating rate does not allow for the ion-ion coupling to be used for quantum simulations. We emphasize that the heating rate in our setup is not limited by Johnson noise from the trap electrodes as the electric field noise estimates based on the resistance measurements show. We have discussed several means to reduce the heating rate, particularly by changing the electrode material and by applying surface cleaning procedures.
inner RF rail (Figure 6a), where the trap efficiency is decreased, the drive frequency Ω RF is then set to yield a stability factor of q = 0.4. Keeping Ω RF constant, the RF voltage U RF is then adjusted to achieve q = 0.4 in the default configuration ( Figure 4).
For the simulation of DC multiwell confinement and ion shuttling, we use an algorithm that calculates DC voltage sets for axial confinement and micromotion compensation simultaneously at two arbitrary trapping positions r 0 . The voltage set for confinement at these two sites automatically creates additional sites with a spacing of 3 l DC along the trap axes due to the periodic assignment of voltages to the DC segments. Necessary conditions for a trapping site at position r 0 are a vanishing axial electric field, E z (r 0 ) = 0, and a positive curvature, 2 z (r 0 ) > 0. In addition, r 0 needs to be overlapped with the RF null, that is, E x,y (r 0 ) = 0. The sets for micromotion compensation require control over the radial electric field components E x,y (r 0 ). A shift of the trapping position along z can be realized by the axial field component E z (r 0 ). This amounts to eight field parameters (six electric field components and two curvatures) for the two trapping sites at r

Appendix B: Calculation of Johnson Noise and RF Pickup
In this section, the estimates for the ion heating rate due to Johnson noise in the trap electrodes, as well as the magnitude of the RF pickup voltage on the DC electrodes are derived. For the estimate of the heating rate, we consider the leads for the periodically connected island electrodes on the metal 2 layer, which have by far the largest resistance on the trap chip. These leads have a maximal length between bonding pad and furthest DC segment of about l = 3.56 mm and a width of w = 20 μm, result-  ing in a resistance of R lead = l metal 2 ∕(wt) ≈ 0.46 Ω at T ≈ 20 K, where t = 1000 nm is the thickness of the metal 2 layer. The via resistances can be neglected. The amount of electric field noise created by this resistance at the position of a trapped ion is [38] where k B is the Boltzmann constant and T = 20 K. The characteristic distance of the segmented DC electrode, c , is found by trap simulation and has a maximal value c = 2.19 mm along the axial direction for all axial positions (for the radial directions, c is at most about a factor 2 smaller). This electric field noise corresponds to an axial heating rate of [38] where Q and M and the charge and mass of a 40 Ca + ion, ℏ is the reduced Planck constant and z = 2 × 1 MHz is the ion's axial frequency.
For the estimate of the RF pickup voltage on the trap's DC electrodes, we consider the simplified electrical circuit in Figure A2. The RF drive voltage U RF is applied to the trap's RF electrode (green box). The parasitic capacitance C p between the trap electrodes couples the DC electrode (blue box) to the RF electrode, leading to an RF pickup voltage U p on the DC electrode. The value of U p depends on how well the DC electrode is connected to GND, U p = p U RF , with the complex RF pickup ratio and Z C = −i∕(Ω RF C) being the impedance of a capacitance C at frequency Ω RF . To give an upper bound on the pick up ratio p , we consider one of the periodically connected island electrodes which have the largest parasitic coupling capacitance C p and largest lead impedance Z lead . We estimate the parasitic coupling capacitance C p ≈ 0.01 pF from finite element simulations of the trap geometry [86] (cf. Figure 9d). The lead inductance L lead ≈ 0.2 nH is calculated from the simulated capacitance matrix. [87] The lead resistance, calculated above, is R lead ≈ 0.46 Ω and dominates the lead impedance Z lead = R lead + iΩ RF L lead ≈ (0.46 + 0.03i) Ω at the RF drive frequency Ω RF = 2 × 25 MHz. The grounding capacitance C f ≈ 330 nF [88] is given by the capacitance of the low-pass filters used in our setup. These filters are located on a printed circuit board (PCB) within the cryogenic setup, only a few cm from the trap chip. Finally, assuming that the connection line impedance is dominated by the lead impedance Z lead , we arrive at an upper bound for the RF pickup ratio of | p | ≈ 7.2 × 10 −7 .

Appendix C: Simulation of a Linear Trap Array with 10 × 10 Trapping Sites
In this section, we show that the twin-trap design (Figure 3) can be extended to a larger number of parallel linear traps. For this, multiwell confinement and RF shuttling in a linear trap array with 10 × 10 trapping sites are simulated. DC shuttling along the axial direction is not simulated since this aspect is already covered by the studies in the twin-trap: confinement with reduced axial distance ( Figure 6c) and independent axial translations of two adjacent DC multiwells with nine trapping sites each ( Figure 5). It should be emphasized that the simulations presented here are intended only as a proof-of-principle study. The electrode geometry is not optimized and can be further improved.
The geometry of the simulated 10 × 10 trap array is shown in Figure A3. RF confinement in the radial (xy-) plane is produced by parallel RF rails with alternating widths w e = 88 μm and w o = 70.4 μm, referred to as even and odd RF rails, respectively, in what follows. A total of 15 RF rails leads to 14 parallel linear traps, out of which the innermost 10 linear traps are used for ion storage. The widths of the even and odd RF rails differ by about 20%. This leads to a tilt of the radial modes with respect to the trap normal in the presence of DC confinement, allowing for simultaneous laser cooling of all secular modes with laser beams parallel to the trap surface. The segmented DC rails have a width w DC = 79.2 μm and a segment length l DC = 74.8 μm. Like in the twin-trap design, the segments are periodically connected, with the same voltage being applied to every third segment. This allows one to create DC multiwell confinement with a well period of 3l DC ≈ 224 μm.
Inhomogeneities of the RF potential across the array caused by edge effects are mitigated in three ways: First, an additional GND electrode at a distance y = 1.0 mm above the trap surface is introduced, which also increases the trap depth by roughly a factor 1.5, compared to a design without top GND layer. A top GND electrode could be realized for instance with a glass plate coated with indium tin oxide (ITO) and mounted rigidly above the trap chip. ITO remains conductive and optically transparent at cryogenic temperatures. [89] Second, an additional pair of linear dummy traps is added at either side of the array. The 10 central linear traps used for the quantum register are thereby increased to 14 linear traps. Ions loaded accidentally in the outer dummy traps could be deterministically pushed out by using, for instance, suitable DC control fields on the outermost DC electrodes. Third, the width of the outermost RF rails is increased to w edge = 228.8 μm. We note that the simplified geometry in Figure A3 only shows the minimum of DC electrodes necessary for creating a 2D ion lattice. For a realistic operation as ion-lattice quantum processor, a further segmentation of the DC rails would be necessary. In particular, control electrodes for stray electric field compensation (micromotion compensation) and for fine control of secular frequencies (and potentially mode orientations) would be required.

C.1. Multiwell Confinement
To simulate multiwell confinement, a voltage set for axial confinement is calculated for a single trapping site at the center of the array. Upon applying this set, the periodicity of the RF and DC electrodes automatically creates a rectangular array of trapping sites. DC voltages are applied to the DC segments as well as to the RF rails, in order to gain the required number of control parameters for axial confinement and micromotion compensation. In the default trapping configuration, an equal RF voltage U RF is applied to the even and odd RF rails and a DC voltage set for axial multiwell confinement is applied. The

C.2. RF Shuttling
Entanglement between ions in adjacent linear traps is facilitated by a reduction of the distance s x between adjacent RF nulls. This is achieved by reducing the RF voltage U RF on either the even or the odd RF rails. At a separation s x = 40 μm, one calculates a motional coupling rate Ω c = 2 × 1.4 kHz, using Equation (1) and assuming an axial frequency z = 2 × 1 MHz. Once the reduced distance s x is reached, the axial mode frequencies of ions that are to be coupled are tuned into resonance using DC control fields; unwanted coupling, for example, between nonnearest neighbors is avoided by detuning the frequencies of these wells, [21][22][23] as outlined in Appendix E. The trap confinement at the reduced distance s x is shown in Figure A5. The cross sections in panels (a) and (d) show how the 14 × 12 trapping sites are rearranged upon attenuation of the RF voltage on the even and odd RF rails, respectively. In both configurations, the sites form pairs of columns such that for any trapping site a reduced distance s x ≈ 40 μm to either the adjacent site on the right or on the left can be realized. [90] The ion-surface separation is in both configurations about d ≈ 100 μm, almost identical to the default configuration in Figure A4. In general, the ion-surface separation is practically unchanged during RF shuttling. The insets, Figure A5b,e, show a magnified view of the marked pairs of trapping sites. The double-well potentials connecting the two sites of each pair are shown in Figure 15c,f. In the two configurations, the RF voltage is either attenuated by about 59.4% on the even RF rails, or by 41.4% on the odd rails, relative to the respective other rail which is at U RF = 350 V. The difference in required RF attenuation for the two configurations stems from the different RF rail widths. In either configuration, the axial multiwell confinement can be maintained using DC voltages on the order of 1 V with standard secular frequencies of z = 2 × 1.0 MHz axially and r = 2 × (2.0-3.0) MHz radially. The axial mode remains aligned with the z-axis, z = 0, the radial mode tilt is increased to about r ≈ 35 • . The reason for the smaller radial frequencies in comparison to the default configuration is the decreased trap efficiency, just as in the case of the twin-traps. For the simulations, a maximally applicable RF voltage U RF = 350 V was assumed, limiting the stability q-values to 0.21 and 0.26, respectively. Likewise, the double-well barrier is limited to U b ≈ 3.9 meV and U b ≈ 6.1 meV. The multiwell barrier U mw ≈ 35 meV and the trap depth U 0 = (192, 334)meV remain at large values.
Concerning the homogeneity of the central 10 × 10 trapping sites, the most notable variation exists in the reduced trap spacing s x . For attenuation on the even RF rails, this distance changes from s x = 39 μm at the central linear traps, x ≈ ±158 μm, to s x = 44 μm at the next pair of traps, x ≈ ±476 μm. For attenuation on the odd RF rails, the distance changes from s x = 40 μm at the array center, x = 0 μm, to s x = 39 μm at the next pair of traps, x ≈ ±316 μm, and further to s x = 35 μm at the outer pair of traps, x ≈ ±632 μm. The variation in trap spacing s x is caused by the edge effects of the trap array along the x-direction and limits the possibility of parallelized entangling operations across the entire lattice due to the difference in expected coupling rate Ω c . Edge effects due to the finite number of RF rails also cause a variation in the stability q-factor and, therefore, in the radial frequencies. For attenuation on the even rails, the q values are between 0.21 and 0.35, allowing for simultaneous stable trapping, and the radial frequencies vary within r = 2 × (2.0-3.6) MHz. For attenuation on the odd rails, the effect is weaker, with the q-factor ranging between 0.26 and 0.22 and a radial frequency variation of r = 2 × (2.2-2.8) MHz. The differences in r and in trap spacing s x across the array cause a variation in the double-well barrier U b . However, U b does not fall below 2 meV across the entire array and in both configurations. For motional coupling between adjacent sites, the variation in radial frequencies is not a concern if the axial mode is employed. The finiteness of the array leads to additional inhomogeneities in conjunction with the fact that the voltage set for axial confinement is calculated only for a single site at the array center. This makes the axial multiwell potential nonideal at the array edges. Due to this, the axial frequency z varies by 74 kHz for attenuation on the even RF rails. For attenuation on the odd rails, the effect is significantly smaller with a variation in z of 7 kHz. Lastly, edge effects lead to small shifts of the trapping sites off the RF null of about 1 μm for both configurations, comparable to the default configuration.
We note that many of the above-mentioned limitations could be mitigated in an optimized trap geometry. In particular in the reduced RF configuration, one could achieve a much better homogeneity of the reduced trap spacing s x across the array, and therefore of the ion coupling strength Ω c , by adjusting the RF and DC rail widths. A first step in this direction was made by increasing the width of the outermost RF rails, allowing for a match of the stability q-values of the linear traps in the default configuration. Even with remaining variations in Ω c across the array, parallelized entangling operations could still be realized. The correct gate time for each Ω c could be set by the time that the trapping wells are kept resonant, using DC control fields, or the reduced spacing s x = 40 μm could be consecutively set for the different pairs of linear traps using multiple adjustments of the RF voltage. Another important improvement would be a further segmentation of the DC rails. This would allow for tuning of additional parameters such as the mode tilts and the axial trap spacing s z . the trap surface. [38] Therefore, one would like to maximize the ion-surface separation d while maintaining a small trap spacing s that yields a sufficient coupling rate Ω c (cf. Equation (1)). In this section, we consider a trap array without RF tuning and with a trap distance s x = 40 μm. For such an array, the ion-surface separation cannot exceed d max ≈ 30 μm, as we show below. In contrast, using RF tuning we achieve a more than three times larger ion-surface separation d ≈ 100 μm for the same ion-ion spacing s x (cf. Figure A5). This increased separation d corresponds to a two orders of magnitude lower ion heating rate Γ h , assuming a typical d −4 dependence of surface noise. [91,92] In addition, the use of RF voltage tuning in linear trap arrays can also lead to a greatly increased trap depth, as shown below.
We consider a linear trap array with alternating RF and GND rails, Figure A6a. An additional grounded plane at a distance y = 1 mm above the trap surface is assumed. [93] The important difference to the array in Figure A3 is that the RF voltage is identical on all RF rails, that is, there is no RF tuning. Therefore, the trap distance s x is simply given by the periodicity of the structure, s x = w GND + w RF , neglecting edge effects. We further consider a fixed ion-ion spacing, s x = 40 μm, the same value as proposed for the ion-ion coupling in Figure A5. We then simulate the trapping potential for different RF rail widths, spanning the entire range w RF ∈ (0, s x ). With w GND = s x − w RF , the electrode geometry is thus fully determined. In this way, we find all possible values for the ion-surface separation d that can be realized. As seen in panel (b), the maximum achievable ion-surface separation is about d max ≈ 30 μm. This is more than a factor 3 smaller than the ion-surface separation d ≈ 100 μm in Appendix C, where RF shuttling is used to realize the ion-ion spacing s x = 40 μm. In the limit of thin RF rails, w RF → 0, where d max is reached, the stable operation of the trap becomes increasingly inefficient. This is evidenced by the divergence of the RF drive voltage U RF required for a fixed stability q-factor ( Figure A6c). We further determine the global trap depth U 0 , shown in panel (d), which has a maximum value of U 0 ≈ 6 meV. While this is comparable to the double well barrier U b in Figure A5, it is significantly smaller than the global depth U 0 of several hundred meV in appendix C, making loading of ions extremely challenging.

Appendix E: Suppression of Parasitic Motional Coupling between Non-Nearest Neighbors
For the realization of parallelized pairwise entangling operations between ions in adjacent trapping sites, we suggest to employ the motional coupling of the ions' axial modes. Using RF shuttling, a motional coupling strength Ω c ≈ 2 × 1 kHz between nearest neighbor ions can be reached at a reduced trap distance s x = 40 μm (see Appendix C). However, the desired coherent evolution of the ions' motional states can be disrupted by additional unwanted motional couplings to non-nearest neighbors. While these parasitic couplings become rapidly weaker for higher order neighbors due to the 1∕s 3 scaling of the motional coupling strength Ω c (cf. Equation (1)), their presence can still degrade the gate fidelities. In this section, we outline a scheme to considerably reduce the parasitic coupling to non-nearest neighbor ions. The outline considers parallelized entangling operations along the x-direction; the scheme works in the same fashion for operations along the axial direction z.
The scheme makes use of the fact that a strong coupling of the ions' motion requires their axial well frequencies to be resonant; for a well detuning ≫ Ω c , the ion motion can be considered independent. [21][22][23] It is therefore possible to pairwise couple multiple ions simultaneously by picking a different resonance frequency for different ion pairs, effectively turning off the parasitic coupling between the non-nearest neighbors. To be more concrete, we consider the ion lattice illustrated in Figure A7. The ions are arranged in pairs with a nearest neighbor distance s 0 = 40 μm along the x-direction, giving rise to a coupling strength Ω (0) c = 2 × 1 kHz at a resonant axial frequency z ≈ 2 × 1 MHz. The distance to the next-nearest neighbor ions is assumed to be s 1 = 200 μm, similar to the trapping potential in Figure A5. For simplicity, we further assume an isotropic lattice, Figure A7. Suppression of parasitic motional coupling during parallelized entangling operations. The ion lattice is grouped in pairs of ions (black spheres) with distance s 0 and resonant confining double well potential. The trap electrodes are illustrated as gray lines. (a) First order parasitic coupling between ions at distance s 1 is suppressed by choosing alternating resonant double well frequencies z + (1) (red squares) and z − (1) (blue squares). (b) Second order parasitic coupling between ions at distance s 2 is suppressed by an additional detuning of rows of ions by + (2) (red stripes) and − (2) (blue stripes). For higher order couplings, additional detunings in successively increasing areas are required. The areas for the third and fourth order are depicted in (c) and (d), respectively. The detunings (i) decrease with the order of the coupling, scaling as 1∕s 3 i .
where the distance s 1 and the motional coupling strength Ω c are identical along the x-and z-direction. [94] For the suppression of the first order parasitic coupling between ions at distance s 1 , one can use a checkerboard pattern for the well detuning, as shown in Figure A7a. Axial well frequencies within a red or blue square are detuned by + (1) and − (1) , respectively, relative to the resonant well frequency z . For the required detuning, it holds (1) ≫ Ω c ≈ 2 × 100 Hz, a drastic reduction of the parasitic coupling should be observable. The second-order parasitic coupling is between ions at a distance s 2 = √ 2s 1 , along the diagonal of the lattice. This coupling can be suppressed with an additional detuning ± (2) , applied to adjacent rows of ions on a striped pattern as shown in panel (b). Here, (2) ≫ Ω (2) c = Ω (0) c (s 0 ∕s 2 ) 3 ≈ 2 × 2.8 Hz. It is important to note that the detuning (2) partially cancels the detuning (1) for some pairs of ions. To account for this cancellation, the detuning (1) must be increased accordingly. Hence, the suppression of both first-and second-order parasitic couplings requires four different well frequencies for the pairs of ions across the array: z + (1) + 2 (2) , z + (1) , z − (1) , z − (1) − 2 (2) . The scheme can be further extended to suppress higher order couplings by successively increasing the cell size of the checkerboard and striped patterns, as shown in panels (c) and (d) for the third-and fourth-order coupling, respectively. We note that a complete suppression of parasitic couplings up to infinite order is impossible due to the partial cancellation of detunings for different orders: the accumulated compensation for the cancellation leads to diverging well frequencies in the limit of infinite order couplings. In practice, however, higher order couplings i can be neglected once their coupling strength Ω (i) c falls below the ion heating rate Γ h , the fundamental limit for uncontrolled motional excitation. For instance, in the considered array, already the fourth order coupling has a strength Ω (4) c < 2 × 1 Hz. Suppressing parasitic coupling up to the fourth order requires 16 different well frequencies for adjacent pairs of ions with a maximum detuning from each other on the order of a few hundred Hz. Such detunings are small compared to the well frequency z ≈ 2 × 1 MHz and can be readily implemented using individual DC control electrodes below each trapping site.

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