Atmospheric Pressure Dry Etching of Polysilicon Layers for Highly Reverse Bias-Stable TOPCon Solar Cells

Single‐sided etching (SSE) of a‐Si/poly‐Si is typically considered a challenge for realizing a cost‐efficient TOPCon production sequence, as there is a certain degree of unwanted wrap‐around for poly‐Si deposition technologies such as low pressure chemical vapor deposition, plasma‐enhanced chemical vapor deposition, and atmospheric pressure chemical vapor deposition. To date, alkaline or acidic wet‐chemical solutions in either inline or batch configurations are used for this purpose. Herein, an alternative SSE process is proposed using an inline dry etching tool, which applies molecular fluorine as the etching gas under atmospheric pressure conditions. The developed etching process performs complete etching of both as‐deposited amorphous silicon and annealed polycrystalline silicon layers, either intrinsic or doped, and with measured etch rates of >3 μm min−1 at 10% F2 concentration allows etching of a typical layer thickness of 200 nm in just a few seconds. The etching process is also configured to perform excellent edge isolation while maintaining a low wrap‐around etching (d rear < 500 μm) at the opposing‐side. The etching process is successfully transferred to the industrial TOPCon solar cell architecture, yielding high parallel resistances (S shunt,avg. > 1500 kΩ cm2), low reverse current density (J rev,avg < 0.8 mA cm−2) measured at a bias voltage of −12 V, and independently certified conversion efficiencies of up to 23.3%.

DOI: 10.1002/solr.202100481 Single-sided etching (SSE) of a-Si/poly-Si is typically considered a challenge for realizing a cost-efficient TOPCon production sequence, as there is a certain degree of unwanted wrap-around for poly-Si deposition technologies such as low pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, and atmospheric pressure chemical vapor deposition. To date, alkaline or acidic wet-chemical solutions in either inline or batch configurations are used for this purpose. Herein, an alternative SSE process is proposed using an inline dry etching tool, which applies molecular fluorine as the etching gas under atmospheric pressure conditions. The developed etching process performs complete etching of both as-deposited amorphous silicon and annealed polycrystalline silicon layers, either intrinsic or doped, and with measured etch rates of >3 μm min À1 at 10% F 2 concentration allows etching of a typical layer thickness of 200 nm in just a few seconds. The etching process is also configured to perform excellent edge isolation while maintaining a low wrap-around etching (d rear < 500 μm) at the opposing-side. The etching process is successfully transferred to the industrial TOPCon solar cell architecture, yielding high parallel resistances (S shunt,avg. > 1500 kΩ cm 2 ), low reverse current density ( J rev,avg < 0.8 mA cm À2 ) measured at a bias voltage of À12 V, and independently certified conversion efficiencies of up to 23.3%.
In this work, we propose an atmospheric pressure dry-etching (ADE) process [14] to perform single-sided etching of amorphous/ polycrystalline silicon (a-Si/poly-Si) layers for fabrication of industrial TOPCon solar cells on n-type substrates. The process uses diluted molecular fluorine (F 2 ) as the etching gas to enable high throughput inline etching of silicon layers in atmospheric pressure conditions, avoiding the need of ion induced excitation. We first start discussing the etching property of the a-Si/poly-Si layer and aim to devise TOPCon cell processing routes to incorporate the ADE process in the cell processing flow. Using cell-like precursors prior to metallization, detailed microscopic investigations are used to discuss the progression of a-Si/poly-Si etching on the front side, which is followed by the investigation of the rear-side wrap-around and edge isolation. Finally, we present results of first bifacial TOPCon solar cells featuring the developed SSE process and discuss about the reverse bias property of the fabricated solar cells.

Etching Tool
The single-sided etching process is performed using the ADE tool, which previously has been used extensively for etching and texturing of crystalline silicon (c-Si) surfaces. [14] The schematic of the process is shown in Figure 1.
Here, c-Si wafers are loaded in a heated conveyer belt using an automation tool and transported through the reaction chamber in an inline fashion. The etching gas (F 2 /N 2 gas mixture) flows through a heated (T GDP ¼ 200-300 C) gas diffusion plate (GDP) into the reactor, which is kept effectively at atmospheric pressure conditions. As there is no plasma or reactive ion involved in the etching process, the process solely depends upon the thermal activation of F 2 directly at the silicon wafer surface that facilitates chemical reaction of fluorine species with the deposited silicon layer on the c-Si wafer substrate, which is heated to moderate temperatures of T wafer ¼ 200-250 C. The reaction products are transported away through the exhaust into a dry scrubber in our laboratory setup, which can be replaced, for example, by a wet scrubber in an industrial scenario. More details about the etching tool and its use in c-Si etching can be read in previous studies. [14][15][16]

Etching Property
To investigate the etching characteristics of the a-Si/Poly-Si in both as-deposited and annealed states, etch thickness and ERs are measured after varying the tool process parameters. A detailed analysis using design of experiments (DOE) is performed in parallel, the results of which will be discussed separately due to being beyond the scope of this article. For current study, half-etched fabricates were used to estimate the etch depths and the ERs. The results are shown in Figure 2.
For the experiment, n-type, saw-damage etched c-Si wafers are used as precursors. After wet-chemical cleaning, a thermal oxide layer (90 nm) is grown before depositing either intrinsic amorphous silicon (a-Si(i)) layer (160 nm) or in situ phosphorousdoped polysilicon (poly-Si(n)) layer (200 nm) in the LPCVD furnace. The task of the thermal oxide is to act as an etch stop during ADE and to enable thickness measurements of the deposited polysilicon layers. Intrinsic a-Si(i) layers are subjected to a POCl 3 diffusion process that simultaneously leads to phosphorous doping and crystallization of the amorphous layers into polycrystalline silicon (poly-Si(n)) in a so-called POCl 3 -anneal process. After a short HF dip (2%HF, 2 min), the precursors are passed through the ADE etching chamber with a preconfigured gas flux (F 2 concentration ¼ 10%), temperature and speed (v ¼ 23 mm s À1 ). When one-third of the wafer length has entered inside the etching zone, the gas flow is abruptly stopped so that the different positions of the wafer are exposed to the etching gas for different durations. This allows the determination of the etch depth for this test setup. Cross-sectional scanning electron microscopy (SEM) imaging (Zeiss Auriga 60) is used to estimate the layer thicknesses (20 points) on the etched and unetched (rear) sides of the sample to calculate the etch depth.
For calculating the etching duration for each position, we assigned a process starting position (t ¼ 0 s) on the wafer by looking for the furthest point from the wafer edge with no apparent   Plot showing etch depth and associated ERs for as-deposited in situ phosphorous-doped and annealed ex situ phosphorous-doped LPCVD deposited silicon layers. Here, the dashed line represents the linear fit of the dataset, the dotted line represents linear extrapolation of data points. The blue arrows show the data points where complete etching of layers is achieved. Apparent ERs are also shown for as-deposited (ER) and annealed (ER 1 and ER 2 ) layers. ER, ER 1 , and ER 2 are calculated from the respective slopes of the linear fits. ER 1  etching of a-Si/poly-Si layer based on visual inspection and SEM investigation. Error bars are included to reflect the inaccuracy in distance measurement (AE5 mm), which is translated to the process duration (X-error). Inaccuracy in estimation of layer thickness from cross-sectional SEM measurements is assumed as Yerror ¼ AE10 nm. It is observed that the etching starts faster in case of as-deposited layers in comparison with the annealed layers. The etch depth increases linearly with the process duration for the as-deposited layer, indicating a quasiconstant ER. In contrast, there are distinctly two etching regimes for the annealed layer-first with a slower etching rate (ER 1 ¼ 1 μm min À1 ) and second with higher ER (ER 2 ¼ 4.6 μm min À1 ). In fact, ER 2 exceeds the total ER achieved with as-deposited layer (ER ¼ 3.1 μm min À1 ). With increasing process duration, etch depth of annealed layer seems to steadily increase in linear fashion to converge with the extrapolated data for as-deposited layer. Note that, for annealed layers, the SEM measurements underestimate the etch depth and ER values, as it does not consider the increase in porosity of annealed poly-Si layers with increasing process duration (see Figure 4 in Section 2.4).
In Figure 2, a slower etching at the start of the annealed layers can possibly be attributed to a high selectivity of F 2 gas to silicon in comparison with the native oxide layer. [14] Although HF dip was performed after LPCVD deposition, even a short waiting time (%30 s) after HF dip is reported to grow native oxide layer on c-Si surface. [17] The experimental conditions in our experiments are similar, where the waiting time between HF dip and ADE process is even much longer (up to 1 h). Meanwhile, studies by Oshaki et al. show that native oxidation of amorphous silicon layers also occur in ambient air at room temperature. [18] Nevertheless, the oxidation phenomena might differ in case of amorphous and crystalline silicon layers. In amorphous silicon layers, oxygen atoms are reported to readily diffuse into the layer resulting in the oxygen incorporation not only on film surface but also inside the film. [18] This might lead to a constant etching rate of in situ doped amorphous silicon layers in our study. Nevertheless, more research is required to understand the exact role of oxidation on etching behavior of F 2 in amorphous and polycrystalline silicon layers.
Meanwhile, for annealed layer, the second etch regime showing quasiconstant ER (ER 2 ) that is higher than the ER of amorphous layers (ER) suggests an additional factor influencing the ER. It is suspected to be linked to the different structural nature of the annealed layer (single crystals with grain boundaries), which leads to different progression of etching in comparison with the as-deposited layer. This will be briefly discussed later in the Section 2.4. In summary, high ERs >3 μm min À1 could be reached for both layers with the applied process parameters, which could be further increased at higher F 2 flows and concentration. In addition, increasing process temperature is also known to exponentially increase the silicon ER, [14] which suggests further potential in increasing the process throughput and lowering the process costs in high volume manufacturing. However, even with the process utilizing 10% F 2 concentration at 225 C, the deposited silicon layer of around 200 nm thickness can be etched in just a couple of seconds. Note that the exact value of ERs calculated here using half-fabricates on saw-damage etched (SDE) surfaces are likely to vary from the full area etching of textured cell precursors due to following reasons: 1) prolonged etching of half-etched fabricates due to remaining F 2 in the reactor, even after switching mass flow controllers (MFCs), can cause error in approximation of the starting point (t ¼ 0 s), 2) higher surface area of textured surface could require longer process duration in comparison with flat surfaces. In fact, we achieved complete etching of 180-200 nm-thick polysilicon layer in M2 size (A ¼ 244.3 cm 2 ) textured and diffused solar cell-like precursors (rear-side after chemical edge isolation) in <6 s at T wafer ¼ 225 C and F 2 concentration ¼ 10%, whereas in <3 s at T wafer ¼ 245 C and F 2 concentration ¼ 30%, depending upon the used F 2 flux. This suggests an ER of 1.5-4.5 μm min À1 depending upon applied ADE process conditions. In comparison, the literature on wet-chemical etching of poly layer reports an effective ER of %0.3 μm min À1 for NaOH solution, [19] whereas %0.36 μm min À1 for a two-step etching process using HF-HNO 3 followed by KOH. [13] 2.3. Integration in TOPCon Solar Cell Processing Flow Figure 3 schematically shows two different TOPCon processing routes based upon LPCVD a-Si deposition technology. The process flows are also accompanied by the schematic cross-section of solar cell precursors at the important steps to facilitate the understanding of the requirements for a wrap-around removal process. Note that the two example process routes are designed mainly for demonstration of applicability of ADE process on both in situ or ex situ doped polysilicon layers, resulting in low reverse current densities. Leaner process flows with higher efficiency potentials are currently being investigated and will be discussed in future studies.
Here, the two TOPCon routes differ mainly by the method used to form doped a-Si/poly-Si layers. For both routes, boron doping is performed on alkaline textured surfaces using BBr 3 precursor in a tube diffusion furnace to form boron (p þþ ) emitter. This is followed by a chemical edge isolation (CEI) process to perform single-sided removal of rear-side emitter, whereas keeping the BSG layer in front-side intact before performing the cleaning sequence. This provides a wide process window that can be used for the a-Si/poly-Si etching process.
Afterward, tunnel oxide is formed in situ by oxidizing c-Si surface inside LPCVD furnace, which is followed by deposition of either intrinsic (TOPCon_ex situ) or phosphorus (n þ -) doped a-Si/poly-Si layer (TOPCon_in situ) process. The LPCVD a-Si/ poly-Si deposition by LPCVD is inherently both-sided, therefore leading to a parasitic deposition of layers on the undesired (front) side. For the ex situ route, a POCl 3 -anneal process is performed at high temperature (T ¼ 800-900 C) to incorporate dopants into a-Si/poly-Si layer, which simultaneously acts as a thermal annealing step required to cause phase change of predominantly amorphous layer to a polycrystalline layer, the so-called polycrystalline-silicon/ polysilicon (poly-Si). After PSG removal in wet-chemistry, ADE process can be performed to remove the wrap-around poly-Si layer.
As shown schematically in Figure 3, it is not only important to fully remove the poly-Si layer on the textured side, but also to isolate the edges to avoid the leakage current paths in a solar cell. We have observed that for both, as-deposited and annealed layers, the BSG layer acts as an excellent barrier layer against F 2 , and thus an etch-stop. In fact, no measurable etching of BSG layer is observed even after applying the maximum F 2 www.advancedsciencenews.com www.solar-rrl.com concentration possible in our setup (30%) to a substantially longer duration (>2.5 times) than the typical process time required to completely etch 180 nm poly-Si(n) layer. A high resistance of BSG layer against F 2 gas provides a wide process window while applying ADE for polysilicon etching. For ex situ route, ADE process is beneficial to perform after the POCl 3 -anneal process rather than in as-deposited state, as performing the ADE process before ex situ doping leads to the following drawbacks: 1) higher chances for shunt formation due to diffusion of the phosphorous atoms through the BSG layer; 2) phosphorous doping of the edges that would require an additional subsequent SSE process for edge isolation. For TOPCon_in situ, the deposition of phosphorus doped layers (a-Si(n)) is followed by ADE process for wrap-around removal of a-Si(n) layer on the textured-side, with a subsequent BSG etching and cleaning sequence. Afterward, a high-temperature annealing process is required to form poly-Si(n) layers at the rear.
For both routes, boron emitter passivation is then performed by depositing a passivation layer stack on the front side. In this work, the passivation is performed by first growing a thin low-temperature thermal oxide of 1-2 nm in a tube furnace before deposition of AlO x /a-SiN x :H using a PECVD tube furnace. PECVD a-SiN x :H is then deposited on top of poly-Si(n) layer in the rear-side as a hydrogenation source. Afterward, metallization is performed by screen-printing Ag (rear) and Ag-Al (front) grids, followed by a fast-firing process.

Etching Progression
The progression of ADE etching process is studied in case of both predominantly amorphous layers in as-deposited state (relevant to the TOPCon_in situ route), and for polycrystalline layers formed after high-temperature annealing (relevant to the TOPCon_ex situ www.advancedsciencenews.com www.solar-rrl.com route). For these studies, we used cell-like precursors that are prepared using the process flow shown in Figure 3 till the ADE process step. ADE etching is performed for various process durations, keeping other parameters constant, to observe various stages of a-Si/ poly-Si etching using high-resolution scanning beam electron microscopy (Zeiss Auriga 60). The results are summarized using Figure 4 and 5 for ex situ doped annealed poly-Si(n) and in situ doped as-deposited a/poly-Si(n) layers, respectively. In Figure 4, the SEM images clearly indicate that the etching of poly-Si layers preferentially starts on highly reactive sites such as defects/grain boundaries in the poly-Si layer. Indeed, the polycrystalline layers are known to comprise small grains of single crystals that are separated by thin grain boundaries consisting of extremely thin amorphous layer. [20] Depending upon deposition and annealing conditions, poly-Si layer is reported to have crystal grains that are either randomly distributed or have a columnar structure. [20,21] The cross-sectional image of the enhanced etch at boundary region (third image from left in Figure 4) indicates the columnar grain structure of poly-Si layer used in this work, with grain sizes in the range of 50-500 nm as estimated from the SEM images. A detailed estimation of the grain sizes is beyond the scope of this work.
Based upon the available literature on F 2 etching of silicon, preferential attack of F 2 on the reaction sites such as surface defects and grain boundaries is very likely to occur. [22,23] Once the etching leads to the opening of the grain boundaries, a larger surface area of poly-Si is exposed to the incoming F 2 species. Gradually, the crystal grains are etched in a preferential order, with the ERs  www.advancedsciencenews.com www.solar-rrl.com potentially decreasing with the increased packing of the atoms in the crystalline structure. Further investigations are required for the in-depth understanding of the etching mechanism. In Figure 5, it is observed that the etching progression for the as-deposited layers differs from the annealed layers in Figure 4. For such predominantly amorphous layers, it is expected that the etching also starts preferentially on reaction sites such as surface defects and atomic steps, leading to the formation of the etch pits and the nanostructuring of the a-Si layer, before gradually etching it completely. Interestingly, it is observed that the pyramid valleys are the areas that are etched in the end.

Rear-Side Wrap-Around
Apart from etching of parasitic a-Si/poly-Si layer on the undesired side (front/textured side), the wafer edges also need to be etched to avoid the shunt paths in the solar cell. One way to avoid the leakage currents, especially for the reverse bias state, is to perform slight wrap-around etching of a-Si/poly-Si layer on the rear while etching the front side.
During ADE etching of the front side, the BSG layer acts as an excellent barrier; therefore, the etching process is self-limiting once the a-Si/poly-Si layer on front side is etched. However, it is important to not substantially over-etch the rear-side as it would then negatively impact the electrical performance and reverse-bias property of the solar cell. In addition, the rear-side Ag-grid must be designed to avoid printing on the cell area portions that are devoid of any a-Si/poly-Si layer. Therefore, the ADE etching needs to be optimized in such a way that the process results in the complete etching of a-Si/poly-Si layer in the front side, while enabling edge isolation and acceptable rear-side wraparound. Figure 6 shows the microscopically measured rear-side wraparound for various ADE processes that differ in the F 2 concentration while keeping other parameters constant (v ¼ 28 mm s À1 , T wafer ¼ 225 C).
It is observed that for the constant process duration and temperature, an increasing F 2 concentration linearly increases the rear-side wrap-around distance. Although process A shows the lowest average wrap-around distance of 250 μm, the process is not able to yield complete etching of a-Si(n) on the front side, and thus not the ideal process. A slight increment in F 2 concentration to 6% yields a complete etching of a-Si(n) layer on the front side while at the same time also enabling a low average wrap-around distance of 300 μm. In contrast to this, a higher F 2 concentration leads to a further increment in the wrap-around distance. Nevertheless, the wrap-around distances shown here are still modest and are applicable in the solar cell manufacturing. For the sample with maximum F 2 concentration of 20%, SEM investigations of the rear-side wrap-around is performed, imaging the a-Si(n)/c-Si interface in every 500 μm distance from the wafer edge. The images are shown in Figure 7.
It is observed that the a-Si(n) layer is completely etched at the wafer edge. At 500 μm from the wafer edge, a thinner (40-50 μm) layer is found. At 1000 μm away from the wafer edge, no measurable thinning of a-Si(n) layer is observed although the images suggest slight roughening of the layer. The results suggest that, for the optimized ADE processes (example process B and C in Figure 6), a low rear-side wrap-around <500 μm can be expected.

Application in TOPCon Solar Cells
In Figure 8, photographs of solar cell precursors at different stages of solar cell production (TOPCon_in situ) are shown. It can be observed that the a-Si(n) layer on the textured side is completely removed after the ADE etching (Figure 8 (middle)), whereas the wrap-around of the rear-side (Figure 8 (right)) is maintained to be very small and is hard to notice visually.
First cell results achieved after integrating ADE process in both ex situ (TOPCon_ex situ) and in situ (TOPCon_in situ) processing routes, as shown in Figure 3, are show in Figure 9. Note that the ex situ and in situ cell results are not directly comparable as the  Table showing the respective process information. Here, deposition of 180 nm in situ doped a-Si(n) by LPCVD is followed by ADE etching. F 2 concentration is varied by changing gas flux ratios (F 2 /N 2 and N 2 ) and total gas flux, whereas all other parameters (T wafer , v) are kept constant. The red full diamond represents a process where a-Si(n) leftovers are identified on the front-side after ADE, whereas the blue empty diamond represents processes leading to complete etching of a-Si(n) layer on the front-side.
www.advancedsciencenews.com www.solar-rrl.com samples have been processed in different batches at different times, partly received different processing recipes in various process steps. The solar cells from these batches reach highest conversion efficiency (η) of 21.60% for TOPCon_ex situ and 21.95% for TOPCon_in situ routes, respectively. The cells from these batches are mainly limited by lower-than-expected FF and V OC values. The optimization of these parameters is ongoing in current batches, by mainly looking to improve the passivation and metallizationrelated process steps. Meanwhile, for the evaluation of the single-sided etching of a-Si/poly-Si, parallel resistance (S shunt ) is the important parameter to consider. Both batches showed excellent values of shunt resistance (S shunt,avg. > 1500 kΩ cm 2 ), which underlines complete removal of parasitic a-Si/poly-Si layers by the ADE process. Furthermore, high pseudo-fill factor (pFF) values also suggest no influence of shunt resistance on FF values. In Figure 10 (left), reverse current density (J rev ) measurement of solar cells performed at the reverse bias of À12 V are plotted for both TOPCon_ex situ and TOPCon_in situ routes. In both cases, ADE processing enables low reverse current density (J rev,avg < 0.8 mA cm À2 ) values, with no hotspots observed in thermography measurements. A representative infrared image of the fabricated TOPCon solar cell is shown in Figure 10 (right). In summary, cell results for both routes prove the effectiveness of the single-sided a-Si/poly-Si etching process developed in this work.
Very recently, the conversion efficiency of large area TOPCon solar cells (A cell ¼ 244.51 cm 2 ) with in situ phosphorous doped LPCVD polysilicon and applying ADE etching for wrap-around removal has been increased to 23.3% with following electrical parameters: V OC ¼ 702.7 mV, J SC ¼ 40.1 mA cm À2 , FF ¼ 81.3%, η ¼ 23.3%, independently certified by Fraunhofer ISE CalLab PV Cells. The optimizations performed in the process sequence to achieve this are beyond the scope of this article and will be discussed in future publications.

Conclusion
In this work, we present ADE to perform single-sided etching of amorphous/polycrystalline silicon (a-Si/poly-Si) layers to fabricate industrial-type TOPCon solar cells on n-type substrates. The etching process has been developed for LPCVD-deposited phosphorous-doped polysilicon layers either in as-deposited state or after the annealing step. High etching rates of >3 μm min À1 are achieved for a-Si/poly-Si layers in SDE surface at a low F 2 concentration of 10% and T wafer ¼ 225 C. On textured cell-like processors, the currently applied process leads to an etching rate of 1.5-4.5 μm min À1 , depending upon the applied process conditions. This means a typical a-Si/poly-Si layer thickness of 200 nm on large (M2) wafer size is completely etched within %3-6 s while maintaining excellent single-sidedness. Further increment in ER can be achieved by increasing the process temperature, the fluorine concentration, the fluorine flux, and enlarging the reactor size. Nevertheless, already the current process offers the highest etching rates in comparison with the other alternatives that are reported in the literature so far. The ADE process tool used in this work enables automated load/unload and inline transport of the wafer substrates, which underscores its applicability in high-throughput manufacturing scenario. ADE shows extremely high selectivity of silicon layers to the borosilicate glass (BSG) layer, which is typically formed during boron emitter diffusion step and can therefore be used as a perfectly stable etch-stop for F 2 etching. The ADE process also shows an excellent edge isolation property while limiting the wraparound of the rear-side to <500 μm. With considerations on the reverse-bias behavior of the cell and ensuring a lean process flow, we propose to implement ADE after POCl 3 annealing for ex situ doped layers, whereas in as-deposited state for the in situ doped layers. First TOPCon solar cells using ex situ and in situ doped poly-Si layers reach a maximum conversion efficiency of 21.6% and 21.95%, respectively. The cells presented in this work are mainly limited by a lower V OC and FF; nevertheless, the cells show excellent parallel resistance (S shunt,avg. > 1500 kΩ cm 2 ) and Distance from wafer edge Figure 7. SEM images showing presence/absence of a-Si(n) layer for an increasing distance from the wafer-edge for the process D in Figure 6.
www.advancedsciencenews.com www.solar-rrl.com high pFF values, confirming a successful transfer of the ADE process to the TOPCon solar cell processing. The process improvements have recently improved the electrical performance of TOPCon cells featuring in situ doped layer and ADE wrap-around removal with an independently certified conversion efficiency of 23.3%, featuring V OC > 700 mV. In addition, for several batches processed already in our pilot line, ADE process consistently shows reproducible results of low reverse current density ( J rev,avg < 0.8 mA cm À2 ) measured at the bias potential of À12 V, with no hotspots observed in thermography measurements. Although the current study is performed based upon current state-of-the-art LPCVD-deposited a-Si/poly-Si layers, the results are also applicable to alternative a-Si/poly-Si layer deposited by other technologies such as PECVD and APCVD. In fact, we have observed that the wrap-around of PECVD-deposited a-Si/poly-Si layers is etched even faster due to a lower wrap-around thickness in comparison with the LPCVD-deposited layers. The process developed in our prototype tool is swiftly transferable to the currently offered high-throughput version of the industrial tool, [24] thus making ADE etching highly relevant for the PV industry. Last but not least, the use of F 2 gas with zero global warming potential (GWP) and an easy abatement of waste products using existing wet scrubber systems help toward lowering the environmental footprint of PV production plants. www.advancedsciencenews.com www.solar-rrl.com