A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

MeitY, Government of India Abstract A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator (DSM) mode in 8‐bit to 15‐bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm. The ADC resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8‐bit to 11‐bit resolutions and as the first‐order DSM with a multi‐bit quantizer in 12‐bit to 15‐bit resolutions. The dynamic performance of the proposed ADC is verified through post‐layout simulations with a supply voltage of 1.8 V. It exhibits a signal‐to‐noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).


| INTRODUCTION
The 21 st century is marked as digital era by electronic industries which brought revolution in signal processing. Modern electronic systems employ sophisticated functional blocks which impact power consumption, cost, performance and reliability of the system. Digital signal processor (DSP) is able to implement complex algorithms and functions with high computational accuracy and power. Along with this, improved noise margin, error detection and correction codes made the transmission and storage of digital signals less prone to noise. Hence the analog circuit techniques in many applications were replaced by reliable, cost-effective, fast and flexible digital technologies. Thus, there is an extensive need for analog to digital converters (ADCs) and digital to analog converters (DACs) to avail benefits of digital signal processing as the realworld signals are analogue. Of late, design of ADCs has become critical, especially with technology scaling because the circuit noise is not decreasing as much as the technology/ supply voltage does.
The advancements in healthcare system make humans life better day by day. Biomedical devices [1] help to monitor the patient's body and provide support systems round the clock without causing much inconvenience on their day-to-day life. It not only reduces the length of hospital stay for post-operative care but also offers superior monitoring and reporting process. Moreover, the pre-diagnosis of functional disorders and deadly diseases by these devices might save the life and also reduces the cost of medical care to a greater extent. In many cases, to monitor the biological signals, a wireless body sensor network (WBSN) [2] with multiple nodes is used. To extend battery life, the power consumed by these nodes should be as low as possible. In each sensor node, ADC is a critical block that interfaces physical world with DSP block. Literature study suggests that successive approximation register (SAR) ADC is the most suitable one by virtue of its characteristics like conversion accuracy, ultra-low-power consumption, simple design and technology scaling amenability [3,4]. Typically, SAR ADC [5] is implemented with a binary-weighted capacitor DAC, dynamic comparator and digital logic. The number of capacitors used in the binary-weighted DAC is exponentially proportional to the resolution (N bits). The area, energy consumption and distortion due to mismatch are directly related to the number of capacitors used in DAC. Therefore, there are numerous switching techniques reported in literature to reduce the number of capacitors used in DAC circuit. Biomedical signals such as the electroencephalogram (EEG), electrocardiogram (ECG), breathing quality, measures of blood parameters such as oxygenation, glucose, cholesterol, c-reactive protein (CRP), erythrocyte sedimentation rate (ESR), platelet count, etc. have varying dynamic range and bandwidth. In addition, within a given application like ECG, to accomplish low-and high-resolution tasks at different intervals as shown in Figure 1, a variable-resolution ADC may be optimal. Hence, a power-efficient and fully programmable resolution ADC can substantially reduce the size and cost of the WBSN. In [7][8][9][10][11][12][13][14][15][16], adaptive-resolution ADC architectures are presented for implantable sensors. In all these papers, SAR ADC is designed with binary-weighted capacitive DAC using different switching methods.
The switched-capacitor integrator SAR ADC [7] is implemented using operational transconductance amplifier (OTA) with programmable unity gain bandwidth (UGB) and slew rate, dynamic comparator, capacitors, switches and control logic. The advantages of switched-capacitor integrator based SAR ADC over conventional SAR ADC are summarized as follows: the number of unit capacitors used in the binary-weighted DAC is exponentially proportional to the resolution (N bits). The area and energy consumption are directly related to the number of capacitors and the value of unit capacitor used in the DAC. One way to reduce the energy consumption is by reducing the unit capacitance. The large number of unit capacitors with the smaller unit capacitance makes the effect of capacitor mismatch more severe. Also, the binary-weighted capacitive SAR requires large number of switches which introduce more distortion. Whereas the differential switchedcapacitor integrator based SAR ADC requires 6 capacitors and 16 switches only. Also, the resolution of ADC can be programmable without much modifications to the architecture. F I G U R E 1 Segment depiction of an electrocardiogram signal [6] S/H Another advantage of switched-capacitor integrator based SAR ADC is that the reference voltages are sampled on the capacitors C 3 and C 4 in Figure 4a at the beginning of conversion. This makes the switched-capacitor integrator based SAR ADC less prone to any signal-dependent inaccuracies associated with the reference voltage compared to binary-weighted SAR ADC. This paper presents a hybrid ADC with programmable resolution from 8 to 15 bits for biomedical applications. This proposed ADC operates in two modes of operation: (1) SAR ADC mode for lower resolution of 8-11 bits, and (2) delta sigma modulator (DSM) with multi-bit quantizer for higher resolution of 12-15 bits. The organization of this paper is as follows. Section 2 explains the working principle and techniques used in the proposed programmable resolution ADC. Section 3 discusses the impact of circuit non-idealities on proposed ADC. Section 4 presents the design of building blocks such as OTA with programmable slew rate and UGB, dynamic comparator and digital control logic. Section 5 summarizes the performance parameters and compares with state-of-the-art designs. The paper is concluded with Section 6.

| OPERATING PRINCIPLE OF PROPOSED HYBRID ADC
The conventional SAR ADC is implemented using a sample and hold (S/H), comparator, serial-in-parallel-out (SIPO) register and N-bit feedback DAC blocks as shown in Figure 2a.
Here, f s is the sampling frequency and N is the resolution of ADC. The feedback DAC is implemented with a 1-bit DAC and discrete-time integrator as shown in Figure 2b. The discrete-time integrator accumulates the scaled reference voltage after every comparison cycle from 1-bit DAC and refreshes in each sampling phase. Thus, it fulfils the functionality of an equivalent N-bit DAC.    Figure 3a shows the block diagram of first-order multi-bit DSM ADC which can achieve high resolutions with oversampling and noise-shaping technique. The multi-bit ADC in the loop can be realized with a SAR quantizer which is shown in Figure 2b. In the block diagram shown in Figure 3b, there are two DACs, one operates at frequency Nf s used for SAR operation and another is an N-bit DAC which operates at a frequency of f s and used for noise-shaping purpose. This N-bit DAC can be implemented with a discrete-time integrator and 1-bit DAC as shown in Figure 2b. Since both the paths are using the same DAC structure, they can be reduced to one path. Further, by shifting the summing point towards the comparator, the integrator block operated at frequency f s added into both forward and feedback paths. The series connection of the integrator block and reset@f s blocks cancel with each other in the feedback path. Therefore, the reduced block diagram of first-order DSM with SAR quantizer can be redrawn as shown in Figure 3c. Hence the only difference between SAR quantizer of Figure 2b and the first-order DSM with SAR quantizer of Figure 3c is the reset@f s block. Therefore, it is possible to switch between SAR quantizer and first-order multi-bit DSM by controlling this reset@f s block. Further, the resolution of SAR quantizer is programmable by controlling the N value, and the DSM resolution is controlled with an oversampling ratio (OSR). Figure 4a shows circuit level implementation of the proposed 8-bit to 15-bit programmable resolution hybrid ADC which is controlled by a 3-bit input bus res [2 : 0]. The discrete-time integrator is implemented with a switchedcapacitor integrator with fully differential OTA; capacitors C 1 , C 2 , C 5 , C 6 ; and switches S 3:8 . The reset@f s block is implemented with two switches S 1 and S 2 . The feedback 1-bit DAC is implemented using capacitors C 1 , C 2 , C 3 , C 4 and switches S 11:16 . Figure 4b shows the timing waveform of the proposed hybrid ADC in the first-order DSM with SAR quantizer mode. The nodes v 1 and v 2 are connected to the left of capacitors C 1 and C 2 , respectively. Conversion procedure is depicted with a flow chart as shown in Figure 5. The proposed hybrid ADC configured as a switched-capacitor integrator based SAR ADC from 8-bit to 11-bit resolutions and a first-order multi-bit DSM from 12-bit to 15-bit resolutions. The control bus res[2 : 0] is used to select the resolution of ADC. The signal-to-noise ratio (SNR) for firstorder DSM with multi-bit quantizer is given by The resolution (N) for multi-bit DSM and OSR is chosen to target the corresponding SNR for each resolution from 12bit to 15-bit. For example, res[2 : 0] ¼ '100' configures the proposed ADC as the first-order DSM with 7-bit SAR quantizer and an OSR of 16 which targets 75 dB SNR. The sampling and clock frequency, targeted SNR, SAR quantizer resolution, and OSR for all modes are calculated according to the resolution mode chosen by res[2 : 0].
The conversion process starts when reset is 'high'. The total conversion can be divided into four phases as follows: Sampling phase: In this phase, switches S 5 , S 6 , S 9 , S 10 , S 11 and S 12 are 'ON'. Capacitors C 1 and C 2 sample the differential input signals V ip and V im through S 9 , S 5 and S 10 , S 6 switches, respectively. Also, capacitor C 3 samples the supply voltage V dd through switch S 11 and capacitor C 4 discharges to ground through switch S 12 . In 8-bit to 11-bit resolution modes, switches S 1 and S 2 are 'ON' thereby resetting the capacitors C 5 and C 6 . This phase exists for a positive half cycle of the clock after the end of conversion (EoC). Further, to avoid the distortion due to charge injection, bootstrapped switches with bottom plate sampling are used. Charge accumulation phase: This phase comes up during every negative half of clock cycle. In this phase, S 3 , S 4 , S 7 and S 8 switches are 'ON' and the remaining switches are 'OFF'.
Therefore, the capacitors C 1 and C 2 are connected between V cm and virtual short node. This forces the charge on capacitors C 1 and C 2 to transfer and accumulate on capacitors C 5 and C 6 , respectively. Comparison phase: This phase exists for a small interval which starts at the positive edge if EoC signal is low. In this phase, the differential outputs of OTA are compared and the decision bit is stored in SIPO register. Passive charge sharing phase: This phase starts after the comparison phase in positive half cycle, in which the capacitors C 1 , C 2 , C 3 and C 4 involve in passive charge sharing through switches S 5 , S 6 , S 13 , S 14 , S 15 and S 16 based on the comparator output. As shown in Figure 5, if the comparator output is high, capacitors C 1 , C 4 and C 2 , C 3 share the charge, otherwise capacitors C 1 , C 3 and C 2 , C 4 share the charge, respectively. This allows to decide the comparison level for the next cycle. The conversion starts with sampling phase and then followed by accumulation, comparison and passive charge sharing phases for N cycles. At the EoC, the capacitors C 5 and C 6 are discharged by closing switches S 1 and S 2 , when the proposed ADC is configured in SAR mode. In the first-order DSM mode, at the EoC of SAR quantizer, the capacitors C 5 and C 6 are left with the quantization error. Hence, the integration property allows noise shaping with an OSR. This characteristic allowed to obtain high resolutions.

| DISTORTION ANALYSIS
The ADC characteristics deviate from ideal due to nonidealities of OTA, capacitors' mismatch and switches. This non-linearity reflects as a distortion in the output and degrades the effective number of bits (ENoB). The estimation of distortion shows the effect of each sub circuit and the specifications needed to achieve the required resolution.

| Capacitor mismatch
The accuracy of SAR ADC depends on the matching of feedback capacitors. The physical design and manufacturing process control the variation of mismatch between capacitors. This kind of mismatch cannot be removed entirely but this can be viewed as a random statistical process and the variation in system characteristics can be estimated [17]. In fully differential circuits and charge sharing circuits, the relative values of capacitors are more important than absolute values. Therefore, the deviation or mismatch between the components is calculated as the normalized deviation from their mean value.
It is assumed that the capacitors C 1 -C 4 are matched well and α 1 , α 2 , α 3 and α 4 are the normalized deviations of capacitors C 1 -C 4 from their mean value, respectively.
Similarly, α 5 and α 6 are the normal deviations of C 5 and C 6 , respectively.
Therefore, from a statistical point of view, it can be assumed that the sum of normalized deviations is zero. Accordingly, The charge sharing between capacitors C 1 and C 4 determines the voltage reference levels, whereas capacitors C 5 and C 6 are involved in accumulation and comparison. Therefore, the group of capacitors C 1 -C 4 and C 5 -C 6 need to be matched well. The mismatch between them induces an error voltage in each comparison and causes non-linearity in ADC transfer characteristics. In SAR ADC operation mode, the deviation of reference voltages in each cycle due to the capacitors' mismatch is derived and tabulated in Table 1. The maximum integrated non-linearity (INL max ) can be derived as shown in Equation (4), and it occurs when the comparator POLINENI ET AL.
-145 output is '1' in all cycles. The standard deviation (σ) of this INL max relates to the standard deviation of capacitor (σ ΔC ) as shown in Equation (5).

| OTA non-idealities
In Section 2, operation of the proposed ADC is demonstrated by assuming infinite gain, bandwidth for OTA and also instant charge transfer between capacitors. In reality, due to the finite gain of OTA, during charge sharing, some charge will be left behind in capacitors C 1 and C 2 , which is known as static error voltage. Similarly, the finite UGB and slew rate of amplifier causes settling time error, which is known as dynamic error. These errors depend on the input signal, which causes harmonics at the output.

| Finite gain of OTA
The switched-capacitor integrator transfer function is derived as follows [18] In charge integration phase, it is assumed that the charge q flows out from C 1 to C 5 and the charge on C 1 becomes From Equation (7), the transferred charge q can be written as After, charge (q) transfer takes place, the charge on capacitor C 5 becomes v om ½n� ¼ q 6 ½n À 1� þ q 2 ½n� Abbreviation: SAR ADC, successive approximation register analog to digital converter.

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Voltage reference levels deviate from the ideal voltage references because of this repetitive gain error which results in non-linearity in ADC transfer characteristics. Equation (11) shows the voltage reference error due to the finite gain of OTA in the n th cycle of SAR ADC operation: The maximum integrated non-linearity can be calculated as From Equation (12), the OTA gain needs to satisfy the following relation to achieve INL less than 0.5 LSB: In DSM operation, the variation in integrator transfer function alters the signal transfer function (STF) and noise transfer function (NTF). By substituting Equation (6) and (9) and applying z transform results in Similarly, where Since C 1 ¼ C 2 and C 5 ¼ C 6 , the loop filter transfer function of DSM can be written as where g ¼ C 1 C 5 A Aþ1 and p ¼ 1 1þϵ are integrator gain and pole, respectively. Therefore, the STF and NTF become ST FðzÞ ¼ LðzÞ From Equation (17), it can be observed that the finite amplifier gain has two effects: a small reduction in the integrator's gain constant and an inward shift of the integrator's pole (z À 1). The change in integrator's gain constant is equivalent to a coefficient error (ϵ) and also causes the extra poles of both STF and NTF move away from the origin. Thus, this -147 change in integrator gain has a negligible impact on the in-band SNR degradation. In contrast to this, the second effect, the shift in pole location of loop filter is more problematic because the loop filter pole becomes an NTF zero. This movement of an NTF zero affects the attenuation of noise in pass band. This phenomenon is modelled in MATLAB for an integrator gain (C 1 /C 5 ) of 0.3. The pole-zero movement in STF and NTF with OTA gain (A) is observed and plotted in Figure 6. One can observe that the pole of STF is moving away from z ¼ 0.7 as OTA gain (A) decreases and zero stays at the origin. This results in the gain reduction in the signal path, as shown in frequency response of STF in Figure 7. In the polezero plot of NTF, shown in Figure 6, as OTA gain (A) decreases, the NTF zero moves from z ¼ 1 towards z ¼ 0 and pole moves away from z ¼ 0.7 which is similar to STF pole movement. The movement of NTF zero causes reduction of attenuation as can be observed in Figure 7. From all of the discussions above, it can be concluded that the finite dc gain of OTA is one of the limiting factors for modulator to achieve maximum SNR.
Further, a low-order modulator is susceptible to the nonlinear phenomenon of dead bands. A dead band is a range of inputs that yields the same periodic output sequence and hence the same post-decimation output. Therefore, in dead band, a dc input with a small magnitude appears as a zero input. The reason behind this is the shift in NTF's zero from z ¼ 1 to z ¼ p, which limits the NTF's DC gain to (1 À p)/ A) instead of zero. Thus, the modulator loses its ability to achieve infinite precision with dc signals. To register small dc input values (u), the following expression [18] should satisfy It is assumed that the OTA gain is constant over output swing in all the above discussions. In practice, OTA gain is a function of input voltage, which causes harmonic distortion. Since the magnitude of the associated input-referred error signal is no more than v outmax /A, the maximum output of OTA (v outmax ) is (C 1 /C 5 ) v inmax . Therefore, upper limit on the total harmonic distortion (THD) of the signal is Even if there is no explicit distortion limit for the ADC, it is needed to ensure that the loop filter is sufficiently linear so that the distorted out-of-band quantization noise does not fall in the noise notch. Based on these considerations, the amplifier is designed for a particular gain, followed by modulator simulations to verify that the amplifier's linearity is adequate.
Further, the programmable resolution ADC with finite OTA gain is modelled in MATLAB. The ADC is simulated with a sinusoidal signal of frequency 123 Hz for resolutions from 8-bit to 15-bit. As the OTA gain is varied from 0 to 80 dB, SNR, THD and signal to noise and distortion ratio (SNDR) are observed as shown in Figure 8. It can be seen that the SNR improves with the OTA gain. It is observed that, the gain around 80 dB ensures the THD below À 90 dBc, which is needed in case of 15-bit resolution. From this result it is concluded that, OTA with 80 dB gain serves our purpose of designing an ADC that is programmable from 8bit to 15-bit.

| Settling time considerations
In charge integration phase it is assumed that every conversion is given sufficient time for charge transfer to settle completely within the required resolution. This settling time must be less than half the clock period [19]. Typically, at large inputs, the OTA saturates and the charge transfer is limited by the bias current. This is known as slewing and the rate at which the TA B L E 2 Computation of capacitor size C 1 , slew rate and UGB requirements of PADC for various resolutions F I G U R E 9 Folded cascode operational transconductance amplifier with programmable bias circuit POLINENI ET AL.
-149 charge transfer happens is called slew rate. Once the OTA input voltage falls under the input range of OTA, the transconductance (g m ) decides the minimum time needed to settle within the required accuracy. This is known as linear settling phase. It is assumed here that, slewing phase exists for x part of T clk /2 and rest of T clk /2 is allocated for linear settling phase.
The boundary conditions for bias current and the transconductance can be derived as follows. The maximum charge that needs to be transferred from capacitor C 1 to C 5 is C 1 V dd in xT clk /2 time and therfore, the bias current should follow the relation as shown in Equation (22).
In linear settling phase, the time constant can be written [18] as The settling time required to keep normalized error voltage below À 100 dB is The required g m can be computed as From Equations (22) and (25), the g m /I ratio can be written as

| REALIZATION OF PROGRAMMABLE RESOLUTION ADC
The ADC works as SAR ADC for 8-bit to 11-bit resolution and a multi-bit quantizer DSM for 12-bit to 15-bit. Here, the SAR ADC works as a multi-bit quantizer. The proposed programmable resolution ADC is built with OTA, comparator, digital control logic, bootstrapped switch, capacitors and switches. This section discusses the design of each of these blocks. The total input-referred noise power for a switchedcapacitor integrator [20] is given as By considering the in-band mean-square noise, the value of capacitor C 1 is calculated and tabulated as shown in Table 2 using Equation (28) for a required SNR. Therefore, the capacitor C 1 is determined as 1 pF subject to the noise for 15bit resolution. The value of capacitor C 5 is determined as 3.3 pF from the integrator gain which is 0.3:

| OTA
The folded cascode (FC) OTA [21] is used to implement the switched-capacitor integrator as shown in Figure 9. In the previous section, it is discussed that a DC gain of 80 dB is sufficient to keep the third harmonic distortion below À 90 dBc. The slew rate and UGB requirements of OTA depend on the clock frequency used for a particular resolution from 8-bit to 15-bit. The designed ADC operates as SAR ADC from 8-bit to 11-bit resolutions and first-order multi-bit SAR quantizer DSM from 12-bit to 15-bit resolutions. Therefore, a first-order Nbit quantizer DSM requires (N þ 1) OSR clock cycles for conversion. The Nyquist sampling frequency is 2 kHz. Table 2 lists the quantizer resolution, OSR and frequency (f clk ) of the clock. The required slew rate and UGB of OTA are determined from clock frequency using Equations (22) and (23) and are tabulated. The bias current of FC OTA and clock frequency are chosen according to ADC resolution. The FC OTA is designed such that it operates in weak inversion region for all bias currents. The transistors are sized in such a way that, the flicker noise as well as the effect of transistor mismatch [22] are less. Figure 10 shows AC response of FC OTA for all bias currents. It is observed that, the DC gain of OTA is greater than 80 dB in all these cases and also the required slew rate and UGB have been achieved. Also, the phase margin is above 60 o for all cases which can be seen from Figure 10. Further, the DC analysis is carried out by varying the input voltage. Figure 11 shows the DC gain variation over output swing. It confirms the variation in DC gain is less than 1 dB over �0.54 V output swing, which helps to reduce the harmonics.

| Switches
The proposed programmable resolution ADC consists of a total of 16 switches. It is required to consider the effects like charge injection, clock feed-through and gate voltage dependent resistance while implementing switches, to reduce harmonic distortion. The NMOS transistor can switch 'ON' for voltages below V dd À V thn , and the PMOS transistor can switch 'ON' for voltages above |V thp | without distortion. In other cases, transmission gate is used as a switch when node voltages swing between 0 and V dd . Sampling switches S 9 , S 10 and S 3 , S 4 are implemented using bootstrapped switch [23] to reduce the input dependent non-linearity. Switches S 1 , S 2 , S 5 , S 6 , S 7 , S 8 , S 12 , S 15 and S 16 are implemented with NMOS transistors and S 11 , S 13 and S 14 are implemented using PMOS transistors. Figure 12 shows the output spectrum of bootstrapped circuit, which ensures that all harmonics are less than À 100 dBc.

| StrongARM dynamic comparator
The schematic diagram of a strongARM comparator [24] is shown in Figure 13, which is generally used in ADCs because of its positive feedback, high input impedance, rail-to-rail output swing and negligible static power consumption. In reset phase, the clk signal is low, thus the transistor M3 is in 'cut-off'  region and the output nodes outp, outm charged to V dd through the transistors M8 and M9, respectively. When clk signal goes high, the decision phase starts and output nodes start discharging at different rates depending upon the input voltages V ip and V im . Meanwhile, when one of the output nodes reaches V dd À |V thp |, corresponding transistor M6 or M7 switches 'ON' and the positive feedback between back-toback connected inverters (M4, M6 and M5, M7), also known as latch, enables and pulls one of the output nodes to V dd and other to gnd. This charge and discharge process takes some time to make decision which is known as a comparator delay. This delay can be classified into two parts: t on is the time required to discharge one of the output nodes to V dd À |V thp | and t latch is the time needed for latch decision.

| Digital control logic unit
The block level diagram of digital control logic circuit is shown in Figure 4a. It is designed using Verilog-A and then synthesized.

| RESULTS
The proposed programmable resolution ADC is laid out in UMC 180 nm 1P6M CMOS technology as shown in Figure 14 and occupies an area of 725 μm � 315 μm. The capacitors  Table 3. The proposed ADC offers adequate ENoB for each resolution mode. Figure 17 shows the plot of SNDR of the proposed ADC over a normalized input with respect to full signal swing for all resolution modes (8-bit to 15-bit). Also, Figure 18 depicts a consistent SNDR over an input signal frequency for all target resolutions. Figure 19 shows the stacking diagram of power consumption by OTA, digital control logic, DAC and comparator. Table 4 shows the comparison of the performance of proposed ADC with similar type ADCs. It can be seen that the proposed ADC is on par with many designs found in stateof-the-art and demonstrated a new approach to implement programmable resolution ADC. 8-bit 9-bit 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit F I G U R E 1 7 Variation in signal-to-noise and distortion ratio with input amplitude for various resolutions POLINENI ET AL.
-153 6 | CONCLUSION An 8-bit to 15-bit programmable resolution ADC has been presented in this paper. The proposed ADC is implemented with a fully differential switched-capacitor integrator and it can be operated in both SAR mode and DSM mode. A FC OTA is designed with tuneable UGB and slew rate is used in the design of proposed ADC. The effects of non-idealities of OTA, such as finite values of gain, UGB and slew rate on ADC characteristics are modelled and studied through behavioural simulations. Further, the non-linearity in ADC characteristics due to the capacitors' mismatch is also calculated. The proposed ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology and occupies an area of 0.228 mm 2 . Post layout simulations show that the proposed ADC achieves an adequate SNDR in all resolution modes (8-bit to 15-bit). The total design consumes 0.86 to 98 μW in 8-bit to 15-bit resolutions, respectively, from a supply voltage of 1.8 V.