Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Laxmidhar Biswal, School of VLSI Technology IIEST Shibpur. Email: laxmidhar.cvrce@gmail.com Abstract Decoherence is the greatest obstacle to the physical realization of scalable quantum computer, jeopardises coherent superposition of the qubit, and makes qubit extremely fragile. Quantum Error Correction Code (QECC), and Fault‐tolerant quantum computation collectively could protect qubit and improve scalability. On the other hand, the conventional logic circuit is no more useful in quantum computing due to much difference from quantum logic. However, quantum computer has to perform classical tasks which can be addressed by translating to its equivalent quantum algorithm. Herein, zero‐ garbage‐based reversible and fault‐tolerant quantum circuit for 1 : 2, and 2 : 4 Decoder with enable signal using Clifford + T‐group are proposed. Further, the design approach to implement n : 2 decoder on fault‐tolerant quantum logic in linear T − depth is extended. Besides, performance parameters likely T − count, T − depth, and garbage output have been evaluated for n : 2 decoder.


| INTRODUCTION
Quantum computer has the potential to carry out calculation beyond the ability of today's most powerful supercomputers and also has the impact to revolutionise in the field of computer and electronics science [1,2]. By contrast with classical computer, the quantum computer works on the principle of quantum mechanics and uses subatomic particles to encode two or more logical values [3]. Besides, the time evolution of subatomic particle of a time-invariant Hamiltonian system that is unitary in nature which leads quantum computation to lossless, reversible, and zero-power dissipation. On the other hand, power loss [4], quantum tunnelling, high leakage current beyond atomic limit [5] defaced the current CMOS technology to encode quantum algorithms. Unlike the bit in classical computer, the quantum computer relies on qubit which is the superposition of classical ortho-normal basis sates. The formal definition, and properties on qubit are presented in Section 2. (Table 1) Currently, substantial research and investments on a global scale are seeking to bring high scalable quantum computers to perform computation beyond today's most powerful classical computer. However, building quantum computers are incredibly difficult due to constraint in physical as well as in logical level as follows: � Quantum hardware is highly prone to noise, and interaction with the environment decays and eliminates the quantum behaviour of particles where the quantum states lose the coherent superposition called as Decoherence [6]. Due to the effect of Decoherence, the qubits are highly fragile and have a short coherence time [7]. � Forbids direct fan-in and fan-out due to the limitation posed by the no-cloning theorem [8] whereas; the copy circuit is the heart of the conventional Boolean logic. � Boolean logic and Boolean algebra are no-more useful in quantum computers directly. However, the quantum logic used in quantum computer is the Boolean observable in quantum mechanics [9].
Quantum circuits are an abstraction to interact physically with quantum computers. The objective of the designing quantum computer is to execute quantum algorithm as well as today's classical algorithm too. So, efficient quantum circuit is most desirable for high scalable quantum computers, which means robust to noise that is fault-tolerance properties along with low execution time, low qubit size, and low garbage output.
Basically, fault-tolerant property can be achieved by encoding physical qubit into logical qubit of quantum error correction code (QECC) which facilitate detection, and correction of error. But, each QECC has finite threshold level, for example most promising surface code has highest error rate threshold value per gate (approximately 0.75%) [10]. To contain error rate within the threshold limit of QECC, a set of primitive transversal gate set viz. Clifford + T-group [11] is used extensively where Clifford + T-group is special case and subset of Clifford + Z N -group [12]. Thus, surface code with Clifford + T-group becomes de-facto platform to design faulttolerant quantum circuit. Moreover, the phase gate (T-gate) has high latency [13] which impedes the performance of the computation due to random location and needs concurrent execution of non-Clifford phase gates [14]. In this work, we propose an efficient reversible and fault-tolerant quantum implementation of an important conventional logic circuit viz. decoder. It has multiple real-time applications such as; seven segment display, memory address decoding, core element of the D/A converter, instruction decoder in Arithmetic and Logical Unit (ALU) and etc. It is to be noted here that notation k-to-2 k is same as k : 2 k throughout the study while presenting the order of the decoder.

| Previous work, limitation, and problem statement
From the current state-of-the-art, none of the approaches provide decoder circuit in fault-tolerant quantum domain. But, there exists a multiple technique on reversible and quantum domain realization of decoder circuit.
Recently Saha et al. proposed n : 2 n R-decoder using nesting structure [15], and models higher order decoder with low quantum cost. In Ref. [16], authors proposed 2-to-4 R-decoder, and n-to-2 n with better quantum cost using Peres-gate, TR-gate and CNOT gate. Besides, few authors proposed R-decoder of different order using Fredkin-gate in Refs. [17][18][19][20]. It is to be noted here that except [20], all the stated design approach are always in operational mode due to lack of enabling control signal. Besides, all hardware of decoder circuit is in active mode even though lower order decoder can able to perform the task efficiently. However, the enable signal plays a pivotal role in quantum information processor due to multiple novel application such as in Switch Bounce and in Race Hazards, by reducing power consumption, ability to use decoder as multipurpose likely De-multiplexer, and helping to reconfigure of large decoder circuit as per the requirement.
On the other hand, most of the state-of-the-approaches contributed n : 2 n reversible decoder which is realized by single reversible decoder block. But, the decomposition of higher order reversible decoder into small size reversible decoder scales poly logarithmically with the precision of approximation as guaranteed by the Solovay-Kitaev theorem [21]. In this regard, enable signal plays pivotal role in the said decomposition. So, we focus on fault-tolerant quantum implementation of decoder circuit with enable input/signal.

| Contribution
Here, we are highlighting our key contribution herein as follows: � We propose reversible, and quantum logic design for two basic 1-to-2, and 2-to-4 decoder with enable, where quantum domain realization exhibits property of faulttolerance. � We model n-to-2 n Quantum decoder (Q-decoder) using proposed 1-to-2 and 2-to-4 Q-decoder. Furthermore, we have calculated all the performance parameter associated with fault-tolerant implementation in quantum domain.
Herein, in Section 2, quantum gate, quantum circuit and circuit performance parameter are discussed. In Section 3, our approach is presented. In Section 4, experimental result and Hadamard(H) 416comparative analysis are discussed. Finally, the work is concluded in Section 5.

| BACKGROUND
This section introduces basic concept of quantum gate, quantum circuit, reversible gate and conventional decoder with applications are discussed for better understanding of this study.

| Quantum circuits
Definition 2.1 (Qubit). It represents an entity of quantum information. Mathematically, it is expressed as the coherent superposition of classical ortho-normal basis states with complex probability. It is denoted by the Ket-function as jψ〉 .
where a, b ∈ C and |a| 2 + |b| 2 = one.  [22]. Any design on NCV gate library [23] can be mapped to the Clifford + Tgroup by using the identities presented in Figure 1. This NCV gate library was provided by Barenco et al. [24]. For better apprehension, here, a list of the quantum gates and its properties are illustrated in Table 1.

| Conventional decoder
Conventional digital decoder maps n-bit inputs into N (N ≤ 2 n )-unique output lines where n, N are positive whole numbers. Decoder provides one active high output based on the combination of inputs present that is the decoder detects a k-particular size of code and provides 2 k -numbers of distinct minterms of k-variables. decoder, for example the decoder is in active mode when E = 1 otherwise; the decoder is in off state. The input-tooutput lines are defined by the equation. 2, and three respectively.

| PROPOSED TECHNIQUE
Quantum logic is the basic foundation of the quantum computer to do computation and is inherently reversible in nature. Thus, reversible logic is the intermediary step while mapping of any conventional logic to its equivalent quantum logic. An efficient reversible architecture since 1:2, and 2:4 decoder with enable bit is proposed first and followed by the fault-tolerant implementation of the quantum domain. At the end, we have calculated the performance parameter that was associated with fault-tolerant quantum implementation of n : 2 n decoder.

| Implementation of 1:2 and 2:4 reversible decoder (R-decoder)
From equation 3, the outputs of the conventional 2:4 decoder are represented by four minterms of mixed polarity of three input variables viz. A 1 , A 0 , and E. According to the reversible domain paradigm, if each small block of one combinational circuit translates into its equivalent reversible logic circuit, followed by the replacement, then the overall circuit switches to reversible circuit [27,28]. It is to be mentioned here that AND (∧) operation can be realized by using Mixed-polarity multiple-control Toffoli (MPMCT) gate, where all the control lines represent input, enable bits of the decoder, and target line initiated with bit '0'. The minterm A 1 .A 0 .E can be realized using 4-qubit MCT gate directly but, same can be realized by using 3-qubit Toffoli gate and CNOT with low quantum cost. Besides, other minterms can be realized using 3-qubit MCT-gates too in lieu of the MPMCT-gate with the help of following Boolean equation.
Now equation. Four translates into circuital form using universal reversible MCT-gate and the resulting reversible circuit is presented in Figure 5a. Furthermore, the Toffoli-gates are decomposed into a set of elementary primitive quantum operators of NCV quantum gate library and followed by the circuit optimization rule. Figure 2b presents NCV-based equivalent quantum circuit of Toffoli gate and replaces all the Toffoli-gate of Figure 5a. After the due procedure of replacement, the out-coming quantum circuit is shown in Figure 5b and has incurred 19 QC which is less in comparison to 21 of [18].
A similar approach has been followed to realize 1-to-2 R-decoder. Equation. Five presents manipulation on Boolean expression to realize D 0 , and D 1 in terms of MCT-function. Figure 6a depicts the equivalent reversible circuit for 1-to-2 R-decoder and contains Toffoli gate along with two CNOTgate. Equivalent NCV-based quantum circuit is shown in Figure 6b and has incurred seven QC.

| Fault-tolerant quantum circuit implementation of 1:2 and 2:4-decoder
It is noteworthy to say that an equivalent fault-tolerant quantum architecture of conventional 1:2 and 2:4 decoder could be realized from proposed NCV-based quantum circuit of R-decoder by mapping all those CV/CV † into the universal transversal gate set viz. Clifford + T-group [22] followed by cancelation of redundancy gates using optimization algorithms like removal of two adjacent H-gate as net effect is identity. Now, apply inter-gate transfer relationship between NCV, and Clifford + T-group as depicted in Figure 1 and map each CV/C † into the equivalent Clifford + T-based fault-tolerant structure followed by optimization algorithms are adhered. After due procedure, the resulting fault-tolerant quantum circuit for 1:2 decoder and 2:4 decoder are shown in Figure 11a and Figure 9 respectively. Figure 5a contains three Toffoli-gate where each Toffoligate contributes 7 T − count, and 3 T − depth. Moreover, two rightmost Toffoli-gate in Figure 9 can perform independently as well as concurrently. Hence, Figure 9 has incurred 19 T − count, and 8 T − depth. Similarly, Figure 11a has incurred 7 T − count, and 3 T − depth.
Again, the key parameter that is, T − depth of the overall circuit could be lowered by executing all those Tgate concurrently which could be possible with four additional ancillary costs. Here, we use the two important switching properties of non-Clifford T-gate extensively for parallelism of all those T-gates and the same is presented in Figure 7 for better apprehension. So, the T − depth optimal fault-tolerant quantum circuit for 1:2 decoder and 2:4 decoder are shown in Figures 11b, and 10 respectively. On calculation, the 2:4, and 1:2 Q-decoder has incurred 3 and 1 T − depth respectively with addition of four ancillary cost.

| Fault-tolerant quantum implementation of n : 2 n decoder
Fault-tolerant quantum implementation of n : 2 n -decoder can be modelled from proposed 2 : 4, and 2 : 1 Q-decoder as a basic building block. From conventional logic, n : 2 n decoder can be formed by using either 2 : 4 or 2 : 1-decoder alone or together where 2 : 4 or 2 : 1-decoders are placed in π 2 radian anti-clockwise rotated pyramid structure. But, the hybrid of 2 : 4 and 2 : 1-decoder can model n : 2 n -decoder with low hardware cost when n is odd. Figure 8a and Figure 8b present n : 2 n -decoder using 2 : 4, and 2 : 1-decoder for even and odd value of n respectively.
According to the quantum domain paradigm, if each small block of a conventional logic circuit is replaced by its equivalent fault-tolerant quantum architecture then overall circuit becomes fault-tolerant.
Consider Clifford + T-based structure of 2 : 4, and 1 : 2decoder that depicted in Figure 9, and 11a as templates of one kind which do not use any ancillary line whereas; Figures 10 and 11b represent template of another kind which has low T − depth but, more additional four ancillary costs. Now, replace each small unit of n : 2 n -decoder using template matching scheme. In this template matching scheme, the conventional n : 2 n decoder scanned from left to right and from bottom to top approach and replace each conventional 2:4 decoder and 1:2 decoder by its equivalent Clifford + Tbased fault-tolerant templates. This template matching scheme provides scope to realize two kinds of fault-tolerant n : 2 n Qdecoder with different T − depth parameter without altering T − count. However, circuit with low T − depth is more preferable and powerful as it could contain the effect of decoherence.
Here, we skip Clifford + T-based resulting circuits of n : 2 n -decoder after replacing due to lack of space. However, we have calculated all the performance parameters that are associated with this design.

| Calculation of performance parameters
Performance parameters likely non-Clifford phase-gate count (T − count, phase-depth (T − depth), and the garbage output (g) associated with design architecture of fault-tolerant quantum circuit for n : 2 n -decoder are to be calculated.
Calculation of T − count (TC(n)) Figure 8 contains two different kinds of structure one for odd, another one for even value of n. Each 2 : 4-decoder has 4 outputs and 2 inputs along with an enable input, which follows either output of the single 1 : 2-decoder or 2 : 4-decoder whereas; 1 : 2-decoder has 2 outputs, 1 input, and 1 enable input, and each successive step of n : 2 n -decoder adds a column of 2 : 4-decoders beyond first decoder which may be either a 1 : 2-decoder or 2 : 4-decoder w.r.t. odd/even value of n. Again, each 2 : 4-decoder within the column takes a common pair of inputs in addition to an enable signal that is mutually exclusive leading to total n 2 numbers of successive steps/columns of 2 : 4-decoders.
Furthermore, beyond second column the number of 2 : 4decoder in each column of said decoder-pyramid is multiplied by a factor of four with the number of decoder in preceding column.
In other way, it can be stated that all 2 : 4-decoders are distributed over the n 2 numbers of rightmost-columns within the n : 2 n -decoder, begins with leftmost either 1 or 2 numbers of 2 : 4-decoders for even/odd value of n to the rightmost column with 2 n 4 that is 2 n−2 numbers of 2 : 4-decoder which provides 2 : 2 n -outputs, and the numbers of 2 : 4-decoders are increased by a factor 4 for each successive column. Let p, and q be the total number of 2 : 4, and 1 : 2-decoders participated in the realization of n : 2 n -decoder. Mathematically, p represents the sum of a G.P series where the first element (a), common ratio (r), and the number of terms (k) is given by 1 for even n 2 for odd n � , 4 and n 2 respectively and, q can be calculated using the reminder function that is n%2. So, the value of p is given by: F I G U R E 8 (a) Pictorial diagram of n − to − 2 n decoder using 1-to-2, and 2-to-4 decoder for n is odd. (b) Pictorial diagram of n − to − 2 n decoder using 2to-4 decoder for n is even F I G U R E 9 Equivalent Clifford + T-based quantum circuit for 2-to-4 decoder The value of q is given by: Moreover, T − count remains same irrespective of the type of templates which are used in the indicated template matching scheme. From above, the T − count of 1 : 2, and 2 : 4 Q-decoder is 7, and 19 respectively. So, TC(n) is given by: Calculation of T − depth (TD(n)) with no-ancillary line From above, T − depth of 1 : 2, 2 : 4 Q-decoder is given by 3 and 8 respectively. In this regard, an important observation is that at most one 2:4-decoder/1:2-decoder is active in each column according to the input qubit vector of the n : 2 n -decoder. Let n : 2 n decoder consists m, and n number of column of 2:4-decoder and 1:2-decoder which are given by: So, TD(n) can be calculated from the parameter m, n, and given by: Calculation of T − depth (TD(n)) with four ancillary cost From above, T − depth of 1 : 2, and 2 : 4 Q-decoder is given by 1, 3 respectively.
Again, four common ancillary lines are reused by each 1:2 Q-decoder as well as 2:4 Q-decoder according to the column location of the said pyramid of n : 2 n Q-decoder in different cycle. So, TD(n) can be calculated from the parameter m, n, and given by:  -421 The proposed design approach adhered to Bennett's laws of quantum information [30] where the input lines are available for the purpose of reuse and the total number of garbage output can be treated as NIL. As, garbage bits have no apparent use, and will cost energy dissipation.

| EXPERIMENTAL RESULT AND COMPARATIVE ANALYSIS
In this work, the 1-to-2, and 2-to-4 decoders have been implemented in reversible logic, as well as in fault-tolerant quantum logic, but none of the present-state-of-the-arts provided any fault-tolerant quantum implementation on 1-to-2, 2to-4 decoder. So, it is hard for us to compare work with other existing work directly. However, there exists multiple work on reversible logic as well as quantum circuit reported in [15,16,19,31] which has much limitation with compare to the features of this proposed fault-tolerant quantum implementation with enable input. In the design phase, 1 : 2-decoder can model n : 2 ndecoder, but more input line is required to design its equivalent in reversible logic. So, we use both 1 : 2, and 2 : 4-decoder to design n : 2 n Q-decoder in linear T − depth. Besides, our design approach lowering the T − depth of the overall quantum circuit of n : 2 n decoder into 33.33% using four additional ancillary cost only. Furthermore, the inputs are basis states and not like an arbitrary superposition, the copy operation of the CNOT gate does not violate no-cloning theorem. Last but not least, the opposite polarity realization of MCT-gates is also used to facilitate optimization of non-Clifford phase gate (Tgate) so as to combat the effect of decoherence.

| CONCLUSION
In this work, we have shown Clifford + T-based quantum implementation of conventional n : 2 n -decoder. In the design process, we have used the functional power of Clifford + T library to transform them into fault tolerant architectures. Basically, the circuit with low TD(n), Garbage line, and qubit size are more powerful as it is robust to decoherence which is necessary to protect coherence of fragile quantum state. Further to make these circuits more efficient, we have used low T − depth-based templates to contain the execution time below the coherence time of extreme fragile quantum state. Besides, the proposed design approach allows reuse of all input qubits as well as intermediary output for other purposes.