Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

The interface trap charges (ITC) associated reliability analysis of a charge ‐ plasma based asymmetric double ‐ gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high ‐ κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band ‐ to ‐ band tunnelling at the source ‐ channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high ‐ κ dielectric (HfO 2 ) have been used to maintain low off ‐ state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric ‐ field, electric potential, first ‐ , second ‐ , and third ‐ order transconductances ( g m1 , g m2 , and g m3 ), gate ‐ to ‐ drain capacitance ( C gd ), cut ‐ off frequency ( f T ), gain–bandwidth product, device efficiency, second ‐ and third ‐ order voltage intercept points (VIP 2 , VIP 3 ), third ‐ order input intercept points (IIP 3 ), and third ‐ order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC at the ‐


| INTRODUCTION
Apart from the improved functional capability of integrated circuits (IC), the unabated scaling of semiconductor devices [1] at the subnanometer regime also fosters challenges in fabrication, such as the requirement of highly doped abrupt junctions [2], thin oxide layers, and surface smoothness [3]. So, there is a quest for new devices [4], which can overcome the challenges mentioned above. In this pursuit, tunnel field effect transistor (TFET) has been advancing as an appropriate candidate due to its fundamental advantage of low off-state current (I OFF ), low subthreshold swing (SS), and insusceptibility against short-channel effects, and random dopant fluctuations (RDFs) [4]. However, TFET experiences the predicament of low on-state current (I ON ), ambipolarity, and substandard high-frequency characteristics. In this respect, different reports have been published in the literature, such as heteromaterial engineering [5], high-κ dielectric [6], gate work function (WF), pocket doping [7], gate-drain overlap/underlap [8,9]. Among them, a CP-based DLTFET [10] has engaged much attention, as it effaces RDFs and the requirement of thermal budget resulting in the formation of the abrupt junction without any chemical doping. However, Si-DLTFET demonstrates low I ON as Si possesses large effective masses for electron, which leads to the modest lateral electric field in the source-channel tunnelling junction, like conventional Si-TFET. To intensify I ON , a Si/Ge HJADGDLTFET has been reported earlier, in which germanium (Ge) and HfO 2 are used as the source region and gate dielectric instead of silicon (Si) and SiO 2, respectively [11]. The substitution of SiO 2 with a high-κ dielectric (HfO 2 ) precedes by a high leakage current as a result of direct tunnelling of carriers via SiO 2 and declined reliability against electrical breakdown [12].
Besides, from the TFET application aspect, the transfer characteristics, as well as its reliability, ought to be guaranteed. The reliability issues in the TFET are relatively severe because of the presence of trapped mobile ionic and fixed charges (in positive [PITC] as well as negative [NITC] polarity) at the semiconductor-oxide interface [13]. These trap charges are formed due to unsaturated fourth bond at the interface originated during the process- [14], stress- [15], and radiationinduced damage [16] in the fabrication process, along with bias temperature instability and hot carrier stress [17]. The term WITC is used to represent the undamaged device (or without ITC) throughout this study. The reliability issues of a conventional TFET have already been reported in [18,19]. However, there is hardly any published report on DLTFET for the same. Therefore, in this article, for the first time, to the best of authors' knowledge, the impact of ITC has been demonstrated by comparative analysis between a Si/Ge HJADGDLTFET and ADGDLTFET. A comparative analysis of DC performance in terms of energy band diagram (EBD), transfer characteristics, electric field, electric potential, and analog/RF performance in terms of transconductance (g m1 ), gate-to-drain capacitance (C gd ), cut-off frequency (f T ), gainbandwidth product (GBP), and device efficiency (DE). Additionally, a device must maintain linearity, so that, nonlinear fragments at the output do not interfere with the desired signal [20,21]. So, the performance parameters such as g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , and third-order intermodulation distortion (IMD 3 ), evaluate the variation in device linearity characteristics due to interfering unwanted noise signals with different frequency components and maintain minimal or negligible higher-order harmonics and IMD at the output [22]. The variation in these performance parameters represents the degree of the device immunity towards ITC.
The organization of the rest of the study is as follows. Section 2 describes the device structure, simulation methodology, and simulation parameters, along with the proposed fabrication process flow of the device. Section 3 describes results and discussions and investigates the DC, analog/RF, and linearity performance parameters of the ADGDLTFET and HJADGDLTFET. In the last, Section 4 concludes the highlights of this work.  Table 1. In HJADGDLTFET, the WF of the drain electrode is taken to be 4.6 eV to induce electron plasma, and the WF of the source electrode is taken to be 5.93 eV to induce hole plasma on the intrinsic semiconductor body [23,24]. The WF of the gate electrode is taken to be 4.5 eV. Furthermore, we have used Ge (low bandgap and high mobility material relative to Si) for the source region in HJADGDLTFET to intensify I ON.

| Device parameter description
Subsequently, HJADGDLTFET exhibits high I ON , while maintaining high I ON /I OFF simultaneously. However, to suppress the enhancement in off-current associated with Ge source, we have used 4.6 eV as the drain electrode WF in HJADGDLTFET [25], instead of 4.4 eV. Additionally, an equivalent oxide thickness (EOT) of 0.37 nm [8] (HfO 2 , ε = 22) is provided between the source electrode and the semiconductor body to avoid silicide formation and form large hole plasma [11,26]. We have the following reasons to do so: An EOT is the gate oxide thickness of the SiO 2 film of a transistor that would be essential to attain comparable capacitance density as the high-κ material is used. For device design, EOT can be defined as: where ϵ sio2 represents the dielectric permittivity of silicon dioxide film, ϵ high−κ signifies the dielectric permittivity of high-κ material, and t high−κ denotes the thickness of high-κ material being used. Additionally, t high−κ represents the high-κ material physical oxide thickness. The primary advantage of using high-κ material as a gate dielectric is that a low EOT can be obtained without decreasing the physical thickness of the gate, thus avoiding the problem of direct tunnelling of the carriers through the gate [27] and improvement in tunnelling current. The volume of ITC density (i.e., N f ) is carefully selected on the grounds of numerous simulated and experimental available reports, integrating damage due to hot carriers, process, and radiation-induced variations, resulting in the N f between 10 11 cm −2 eV −1 and 10 13 cm −2 eV −1 . The N f depends on annealing and oxidation processes occurring during fabrication. So, by efficient passivation of Si as well as Ge surface and then, atomic layer deposition (ALD) of HfO 2 [28], N f at the semiconductor-dielectric interface can be maintained between the range mentioned above .i.e., 10 11 -10 13 cm −2 eV −1 [29]. Therefore, to investigate the impact of ITC, we have considered the N f as 10 12 cm −2 eV −1 for both PITC and NITC [30].

| Simulation methodology
This uses Silvaco ATLAS as the two-dimensional device simulator so that HJADGDLTFET and ADGDLTFET can be simulated effectively [31]. Here, the nonlocal BTBT (BBT. NONLOCAL) model is used to take into account the spatial deviation of the energy bands, along with the spatial segregation between electrons and holes generated in the conduction band (CB) and valence band (VB), respectively. The tunnelling probability is estimated by Wentzel-Kramer-Brillouin (WKB) method, which uses an electron-hole wave vector across the tunnelling path. The FERMI, NI. FERMI models represent the integration of Fermi-Dirac characteristics so that the induced charge carriers do not exceed the limit of the effective density of states of the substrate material. Additionally, the temperature-dependent and field-dependent variations in mobility are modelled by the Lombardi mobility model (CVT). Furthermore, the concentration-dependent Shockley Read Hall (CONSRH) recombination model has been used to account for the generation and recombination of carriers. Withal, quantum mechanical confinement across the semiconductordielectric interface has been modelled by Hansch (HANSCHQM) model. Furthermore, trap-assisted tunnelling (TAT) model accounts for the tunnelling of electrons from the VB to CB through trap or defect states at the high electric field. The INTERFACE statement is used to analyze the density of ITC at the semiconductor-dielectric interface. All the simulation has been performed at V G = 1.0 V, V D = 1.0 V, and 1 MHz small-signal input frequency.

| Fabrication feasibility
The experimental demonstration of CP-based p-n junction [32], dopingless bipolar junction transistor [33], and junctionless TFET [34] has already been reported in the literature. The proposed fabrication process flow of the HJADGDLTFET does not involve ion-implantation and high-temperature annealing process, unlike the metal-oxide-semiconductor field effect transistor (MOSFET). The major fabrication steps using the state-of-the-art process technology for HJADGDLTFET are discussed below schematically. Initially, high-quality intrinsic Ge film can be grown on intrinsic Si substrate via molecular-beam epitaxy (MBE) [35], Ultra-high vacuum chemical vapor deposition (UHVCVD) [36], or DC magnetron sputtering [37] as shown in Figure 2(a). After that, bottom gate (BG) can be formed independently before the front gate (FG) formation [38]. So, reactive ion etching (RIE) is used to etch the epitaxy and then a high-κ gate dielectric layer (HfO 2 ) is deposited by using the ALD technique [39]. Then, patterning and wet etching of bottom side gate oxide in Hf are done, after which, the patterning of the BG region is done using lithography and at last, BG can be formed via the metallization process as shown in Figure 2(b). The same set of procedures as discussed previously is repeated to form FG as shown in Figure 2 (c). Additionally, both BG and FG can be aligned using the same alignment marks. Then at last, patterning and etching of the FG oxide is done to form drain and source electrode regions. Subsequently, metallization is done to form source and drain electrodes as shown in Figure 2(d). Thus, we have confidence that HJADGDLTFET will show good experimental results. Gate electrode WF eV 4.5 4.5

| Impact of ITC on DC performance
Length of asymmetric back gate nm 40 40 Silicon thickness (T Si ) nm 5 5 Oxide thickness (T ox1 ) nm 3 3 Oxide thickness at source (T ox2 ) nm 0.37 0.37 Therefore, it is imperative to feature that the EC in the intrinsic region reaches on the order of 10 19 cm -3 after the application of an appropriate WF at the gate electrode. Therefore, the carrier concentration is less affected by the presence of ITC in the case of HJADGDLFET, contrasting with ADGDLTFET. Figure 4(a) and (b) represents the outcome of NITC, PITC, and WITC on the EBD across the horizontal cutline at 1 nm below the interface. In the on-state, the tunnelling barrier width is reduced as compared to the ADGDLTFET at the source-channel interface, which results in more band bending and consequently higher electron tunnelling from the VB of the source to the CB of the channel.
The leading cause for the reduction in the energy barrier width of HJADGDLTFET is that we have considered a low bandgap material (i.e., Ge with E g = 0.7 eV) and a high-κ dielectric (HfO 2 having ε = 22), which provides a better coupling between the gate and the channel as compared to SiO 2 . However, from these EBD, it can be noticed that the variation due to the presence of ITC for the HJADGDLTFET under on-state is very tiny, unlike ADGDLTFET, in which energy bands are shifted more due to low-κ dielectric which exhibits more variation and makes the device less reliable. Figure 5(a) and (b) show the variation due to the presence of NITC, PITC, and WITC on the electric field along the horizontal cutline at 1 nm below the semiconductor-oxide interface for ADGDLTFET and HJADGDLTFET, respectively. The BTBT mechanism in TFETs results in a higher electric field at the source-channel junction as compared to the drain-channel junction. Therefore, it can be observed from Figure 5 that the PITC (NITC) results in the increased (decreased) electric field. Nevertheless, for HJADGDLTFET, the usage of HfO 2 results in further increment in the electric field at the source-channel tunnelling junction. Moreover, the alterations in the electric field for different ITCs are minimal in the case of HJADGDLTFET relative to ADGDLTFET. Figure 6(a) and (b) shows the variation due to the presence of NITC, PITC, and WITC on the electric potential along the X-direction at 1 nm below the interface for ADGDLTFET and HJADGDLTFET, respectively. It is detected from Figure 6 that the surface potential is high for a gate with lower metal WF. However, the high potential is required to improve band bending at the source-channel tunnelling junction so that a high drive current can be attained. Additionally, the high metal WF of the drain electrode decreases the surface potential and thus suppresses I OFF . Furthermore, the surface potential increases (decreases) due to the impact of PITC (NITC), and this impact is more pronounced in the ADGDLTFET.
The influence of different types of ITCs on transfer characteristics is illustrated in Figure 7(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively, on a logarithmic scale. The presence of PITC (NITC) results in the increment (decrement) of the peak of the electric field resulting in the decrease (increase) in the flat-band voltage caused by the presence of PITC (NITC) [1], defined as: where q is the electronic charge, N f is the ITC density, and C ox is the gate oxide capacitance. The presence of PITC (NITC), decreases (increases) the flat-band voltage and, thereby, increases (decreases) the effective gate bias (V eff = V gs −V fb ) at the tunnelling junction. The enhanced (reduced) V eff is caused by the occurrence of PITC (NITC), thereby, enhancing (reducing) the gate controllability and BTBT at the tunnelling junction. Furthermore, for lower gate voltages, V eff is dominated by V fb , resulting in more variation caused by ITC in comparison to high gate voltages [40]. From Figure 7(b), it is clear that HJADGDLTFET exhibits less variation and stronger immunity against ITC than ADGDLTFET as high-κ dielectric (HfO 2 ) used in HJADGDLTFET increases the gate capacitance and hence better gate controllability [41]. Furthermore, HJADGDLTFET displays an improvement in I ON by one order when equated to ADGDLTFET due to the usage of low bandgap material in the source region and high-κ dielectric material. The electrical coupling has been increased between the gate and the source-channel junction due to increased gate capacitance. Therefore, the HJADGDLTFET obtains an I ON ∼1.5 � 10 -5 A/µm, I OFF ∼1.5 � 10 -15 A/µm, and on-to-off ratio ∼10 10 for a drain voltage of V DS = 1 V and the gate voltage of V GS = 1 V.

| Impact of ITC on analog/RF performance
The effect of ITC on transconductance is demonstrated in Figure 8(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively. The transconductance (g m ) is a critical device criterion for analog applications which convert gate voltage into drain current and govern gain of the device [42] and is stated as: It is evident from Figure 8 that when PITC (NITC) is introduced at the semiconductor-dielectric, nonlocal BTBT increases (decreases), and hence g m1 increases (decreases) for HJADGDLTFET as well as for ADGDLTFET. However, the impact of ITC on g m1 for HJADGDLTFET is insignificant because of the introduction of low bandgap material for the source region, an asymmetric double gate structure, and a highκ dielectric.
At high frequencies, parasitic capacitances such as gateto-drain capacitance (C gd ) and gate-to-source capacitance (C gs ) affect device performance dramatically as these capacitances undertake a feedback path among output and input signal; ensuing the parasitic oscillations and hence signal distortion. For TFETs, C gd dominates due to the formation of the inversion layer of the electron at the gate dielectric interface in the channel region [43][44][45] and is expressed as: The effect of ITC on gate-to-drain capacitance is illustrated in Figure 9(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively, concerning the gate voltage, which shows that the C gd of HJADGDLTFET and ADGDLTFET is comparable and at high gate voltages, the increment in the density of states and capacitive coupling results in the formation of significant energy barrier at the drain-channel interface.
Furthermore, C gd of HJADGDLTFET is greater than that of ADGDLTFET because of the adoption of HfO 2 as gate dielectric and an increase in electron charges caused by heterojunction [46]. As illustrated in Figure 9, C gd increases (decreases) with PITC (NITC).
Moreover, cut-off frequency (f T ) is a significant factor of the device in wireless and RF applications. The frequency upon which the short circuit gain approximates to unity is known as cut-off frequency and is specified as: The effect of ITC on cut-off frequency is shown in Figure  10(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively. It can be shown from Figure 9 that for both devices, as the gate voltage increases, f T increases due to increment in g m1 . As illustrated in Figure 10, f T increases (decreases) with PITC (NITC). However, variation in f T due to ITCs is less in HJADGDLTFET, unlike ADGDLTFET.
In addition to cut-off frequency, the gain-bandwidth product is also a vital device design parameter for RF applications and provided for a DC gain of 10. It can be articulated as: The effect of ITC on the gain-bandwidth product is presented in Figure 12(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively. It is interpreted from Figure 11 that HJADGDLTFET obtains higher GBP in comparison to ADGDLTFET. As gate voltage increases, GBP increases due to substantial growth in g m1 . It is concluded that higher GBP illustrates a more significant gain as well as bandwidth for  HJADGDLTFET as compared to ADGDLTFET. Additionally, the graph of GBP trails to the trend of the cut-off frequency graph, and the reason is pronounced from Equation (6).
DE is a vital device design specification for analog, together with RF performance. DE can be described as the competence of the device to translate given current into its equivalent transconductance and is expressed as: The effect of ITC on DE is shown in Figure 12(a) and (b) for ADGDLTFET and HJADGDLTFET, respectively, outlining that the HJADGDLTFET shows better DE as it depends on transconductance and drain current.

| Impact of ITC on linearity performance
Besides high speed, the advanced communication system must provide a surety for minimum signal distortion and linearity to ensure better signal-to-noise ratio and to establish the aptness of the device for analog applications. The transconductances of the device must be constant concerning the applied gate voltage to acquire linearity. However, the transconductances of both MOSFETs and TFETs rely on the input gain voltage, resulting in the nonlinear characteristics [47]. Therefore, we investigate the linearity performance parameters of ADGDLTFET and HJADGDLTFET, where these parameters are stated as: V IP 3 ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi 24 � g m1 g m3 r ð10Þ where R S ¼ 50 Ω for almost all RF applications where R S ¼ 50 Ω for almost all RF applications The higher-order derivatives of transconductance are the primary reason for nonlinearity and distortion in the device and determine the minimum limit of the distortion. Hence, the amplitude of g m3 must be as small as possible, because, in the case of IMD 3 , it determines the amplitude distortion via adjacent band signals.  Figure 13(a) and (b) illustrates the second-order coefficient of transconductance (g m2 ) as a function of the applied gate voltage for different types of ITC for ADGDLTFET and HJADGDLTFET, respectively. It is observed that the g m2 increases (decreases) with PITC (NITC), and the peak of g m2 moves towards lower gate bias. The third-order coefficient of transconductance (g m3 ) of ADGDLTFET and HJADGDLT-FET concerning the gate voltage for different ITCs is shown in Figure 14(a) and (b), respectively. It is perceived that the variation in g m3 is smaller in HJADGDLTFET than the ADGDLTFET.
The values of VIP 2 and VIP 3 should be high for a device with improved linearity. Figure 15(a) and (b) illustrates the increment (decrement) with PITC (NITC). However, the peak of VIP 2 shifts towards lower gate bias, which suggests that a smaller gate bias is essential for holding better linearity. It is apparent from Figure 16(a) and (b) that the value of VIP 3 increases (decreases) with PITC (NITC). On top of that, the relative amplitude of VIP 3 is larger for HJADGDLTFET. For RF devices, IIP 3 is mainly the result of nonlinearity at the fundamental frequency and the frequency difference between two nearby signals. In literature, IIP 3 and IMD 3 have been studied as an essential linearity parameter [48]. Hence, we have also studied IIP 3 and IMD 3 .
The effect of ITC on IIP 3 with respect to the applied gate voltage for ADGDLTFET and HJADGDLTFET is illustrated in Figure 17(a) and (b), respectively. It is found that HJADGDLTFET is immune to the variations in IIP 3 and IMD 3 characteristics due to the presence of ITC. Nevertheless, the shifting of the peak of IIP 3 towards lower gate bias signifies that HJADGDLTFET can attain better linearity characteristics at a reduced gate voltage. Furthermore, IMD 3 denotes the third-order intermodulation distortion, where the power of fundamental and third-order intermodulation components is equal, which must be of low amplitude to achieve better linearity characteristics. Figure 18(a) and (b) illustrates the effect of IMD 3 concerning the applied gate voltage with different types of ITC for ADGDLTFET and HJADGDLTFET, respectively. Table 2 shows the comparative analysis of various device characteristics for ADGDLTFET and HJADGDLTFET.

| CONCLUSION
The interface trap charge impacts the reliability of the device. Therefore, an Si/Ge heterojunction DLTFET with a high-κ dielectric and asymmetric double gate has been used to examine the impact of ITC. The HJADGDLTFET provides  better driving capabilities, which can be used to enhance amplifier gain. Moreover, dopingless TFET based on the charge plasma concept can provide an integrated solution over its counterpart TFET in terms of fabrication steps. So, with the aid of TCAD-based simulation, a comparative analysis is performed between ADGDLTFET and HJADGDLTFET to investigate the DC, analog/RF, and linear distortion parameters for variations due to different types of ITC. The comparative results illustrate that small variations occur in HJADGDLTFET, making it more immune to variations caused by ITC. Additionally, the investigation of performance degradation due to the impact of ITC is essential to get an optimized device, as ITC is always present in physical devices.