Dual feedback IRC ring for chaotic waveform generation

Ashish Ranjan, Department of Electronics and Communication Engineering, National Institute of Technology Manipur, India. Email: ashish.ism@rediffmail.com Abstract The authors have proposed an inverter resistor capacitor (IRC)‐based simple chaotic ring oscillator with dual feedback for the generation of the chaotic waveform. The proposed chaotic system uses three coupled autonomous first‐order differential equations and it can be electrically demonstrated using the complementary metal oxide semiconductor (CMOS) inverters with few passive RC elements for the generation of the high‐frequency strange attractor. The basic dynamical characteristics and multistability property with complex bifurcation pattern in a wide range of parameters are well observed through theoretical as well as numerical simulation analysis using scaled inverse tangent function. In addition, a simple IRC chaotic model design is investigated using 0.18μm MOS transistor parameters with grounded capacitors and an equivalent CMOS‐based scaled inverse tangent function. Moreover, the Cadence post layout simulation gives useful information about the circuit sustainability for IC design with high frequency (MHz), low power dissipation (940 μW) and small chip area (826.3 μm).


| INTRODUCTION
A simple electronic circuit implementation of an autonomous chaotic system has been an active research area in the field of chaos theory since its inception. A system with complex behaviour in the three-dimensional phase space has been illustrated by a set of ordinary differential equations which contains at least one nonlinear function. Over the past few decades, many chaotic systems specifically, the Lorenz and Rossler system [1,2], the Chua's circuit [3,4], the hysteresis chaotic oscillator [5,6], chaotic jerk [7][8][9][10] and many more are reported in scientific study. The current scenario of electronics world uses unpredictable nature of chaotic waveform which is suitable for secure communication [11,12] in VLSI integration.
An electrical implementation of most of the scientific study comes with conventional operational amplifier (Op-Amp) with excess number of passive components with large chip area, high power dissipation in comparison to advance analogue building block in chaotic circuits [13][14][15][16][17][18][19][20][21][22][23][24][25][26]. However, a monolithic implementation of canonical mathematical model for generation of chaotic waveform using commercially available components as well as complementary metal oxide semiconductor (CMOS)-based operational transconductance amplifier (OTA) with comparator [13] and inverter [14] are well depicted. Also, a circuit implementation with two CMOS ring oscillator with a pair of diode is reported in [15,16]. After the advent of Chua's system, a large number of scientific studies have been reported on different methods for the realisation of chaotic circuit using current feedback operational amplifier (CFOA) in the study [17,18]. However, some other available designs for chaotic circuitry based on CMOS active blocks are OTA [19], current conveyor (CCII) [20], dual output second generation current conveyor (DO-CCII) [21] and differential voltage current conveyor transconductance amplifier (DVCCTA) [22] and few more. These low-frequency chaotic oscillator circuits consist of numerous electronic components and transistors to realise the active inductor and nonlinear element. Moreover, some attractive implementation approaches of chaotic system are also available as bipolar junction transistor (BJT) based R-C chaotic oscillator [23,24], CMOS chaotic jerk circuit [25], simple implementation of high frequency hyperchaotic circuit [26,27] and bistable nonvolatile elastic-membrane memcapacitor exhibiting a chaotic behaviour [28] with less number of components.
The dissipative chaotic flow with multistability property is an exceptional case in the chaos theory. Such systems are very limited in study [29][30][31] and found unwanted in some situations. Any sudden change in the states with parameters or external disturbance produces a new stable situation from the desired state and useful in chaos based secure communication systems. On the other side, the availability of such new lowfrequency system uses more number of quadratic nonlinearity function and multiplying terms [29,30], that make the system equation more complex and difficult to implement for monolithic design. However, a simple implementation of chaotic oscillator utilised hysteresis property of Op-Amp with only few passive components in [31].
The major challenge for the design of high frequency low power chaotic system with multistable property must have a simple implementation without passive inductor and multiplier. Thus, the main aim of this research article is to bring a new design for the implementation of chaotic circuit with minimum number of active and passive components count using fundamental IRC element. The major advantage of CMOS inverter based chaotic circuit provides an ease of integration for both analogue and digital perspective. A process parameter with 0.18 μm CMOS technology is used for CMOS inverter. The workability test of the proposed chaotic system is well verified using numerical analysis (MATLAB) as well as post layout simulation using a Cadence's Virtuoso tool.

| CIRCUIT DESCRIPTION
The proposed dual feedback loop ring oscillator based on third-order chaotic system can be demonstrated as a block diagram in Figure 1(a). Here, (x 1 , x 2 , x 3 ) represents the consecutive output of the first-order low pass RC filter with adjustable nonlinear element f(x). An IRC based simple CMOS chaotic wave generator is shown in Figure 1(b) and mathematically characterised by following a set of voltage differential equations as: The proposed circuit topology uses an IRC based ring oscillator with dual feedback in which one is used to establish the regular periodic oscillations using inverted phase while the other one provides in-phase feedback. Here, the charging and the discharging phenomena of capacitors with the CMOS inverter exhibit very interesting dynamical phenomena that will cause an incremental and decremental change in voltage and current. The implementation of proposed circuit using few resistor, CMOS inverter and RC pair makes a simple design in comparison to available study of chaotic circuit . In order to exhibit chaos, an autonomous circuit requires at least one nonlinear element. The proposed design uses an inverter as a simple nonlinear circuit which is equivalent to scaled inverse tangent function (0.5 −0.5tanh(10 * V− 5)) and provides nonlinear behaviour with parameter variation. This proposes a scaled realisation of basic inverter (Figure 2(a)) as a nonlinear element f(x) and Figure 2(b) is examined where the bistable operation of a modified CMOS inverter works as a nonlinear function. It fulfils the requirement of chaotic oscillation without using more number of external components for nonlinear element as compared to Chua's circuit [3,4], hysteresis chaotic oscillator [5,6] and chaotic jerk [7][8][9][10], CMOS ring oscillator [15,16].
In general, output of basic inverter switched from high bias voltage (V DD ) to low bias voltage (V SS ) by appropriate input that contributes the transition of inverter output. The switching threshold voltage (V th ) is also known as midpoint voltage (V mid ) where output voltage of inverter approaches for same input voltage. Thus, if the switching threshold voltage (V th ) is not equal to the V mid then one of the transistors will be in triode region which causes the nonlinearity in the proposed chaotic system. In order to calculate the V th as a function of electrical parameter of MOS by assuming transistor in saturation region and short circuit power dissipation condition (V th <V in <V DD − |V thp |) given I Dn = I Dp as: where k n ¼ μ n C ox 2 ð W L Þ n and k p ¼ By assuming a common input voltage (V in = V th ) yields the common voltage as a midpoint voltage V th as: Moreover, for a matched transistor and a typical assumption for ideal symmetric inverter by using μ n = μ p and V tn = |V tp | give the midpoint voltage (V tn ) as V DD /2. In practical terms, mobility and threshold voltages are important as they vary due to the fabrication process imperfections. So, it is almost impossible to set the V th to V dd /2 with infinite precision and always some nonlinearity exists which may cause the chaotic behaviour. Furthermore, the nonlinear characteristic of the nonlinear function f(x) can be adjusted with the input voltage and the aspect ratio. By utilising input voltage without any load in the inverter f(x), yields transconductance of N-channel metal oxide semiconductor (NMOS) and P-channel metal oxide semiconductor (PMOS) as: g mn = δI ds /δV gs , and g mp = δI sd /δV sg . Then, the output of f(x) as a current output I out was observed as I Dp −I Dn . By differentiating current output w.r.t. voltage gives the transconductance terms g m as: It should be noted that g mn increases when input increase (V gs n ¼ V in ) and g mp decreases when input increase (V sg p ¼ V dd − V in ). So the overall characteristic of the inverter will change w.r.t the capacitor voltage (V C ) and is accomplished by the charging and discharging of the capacitor. Moreover, tuning of aspect ratio (W/L) will cause a significant change in resistance value. Here, the inverter f(x) contributes a variable resistance termed as drain-to-source resistance (r ds ) and can be formulated in linear mode as: In the linear mode, r ds depends on the gate voltage as V in that allocates control over r ds . According to the proposed concept, r ds has to vary with respect to V in . Channel length (L) and width (W) are also an important parameter which also affects the inverter characteristics and needs to be scaled according to the output swing in order to convert the single attractor to a strange attractor. A modified inverter, as shown in Figure 2(b), uses a nonlinear element. However, strange attractor may be achieved by using transistor sizing. The device sizing may increase f(x) which will give more complex chaotic behaviour. Figure 2(c) shows input output characteristics of modified inverter with variation of aspect ratio, as the W/L increases or decreases the V mid shifted towards the high bias voltage (V DD ) or low bias voltage (V SS ).

| MATHEMATICAL MODEL AND STABILITY ANALYSIS
The set of three differential equations of the proposed design in Equation (1) is modelled in terms of three state variables (x 1 , x 2 and x 3 ) for basic dynamical analysis. The state space analysis of the proposed model can be approximated by the following scale variable and control parameters as The mathematical model in terms of the state variables for numerical analysis of the proposed chaotic system brings the following set of equation as: where control parameter values (α, β, γ, κ) are always positive.
Here, the nonlinear function f(x) represented by a scaled inverse tangent function as 0.5 −0.5tanh(10 * x 2 − 5).  Figure 2(c)). To examine the chaotic behaviour, basic dynamic characteristics analysis of the proposed system will exhibit invariance properties for transformation of coordinate (x 1 , x 2 , x 3 ) to (−x 1 , −x 2 , −x 3 ). One of the important properties termed as dissipativity can be characterised as: Therefore, for all positive values of the α bring the system dissipative. Furthermore, by putting condition ð _ (7) gives the equilibrium point of the chaotic system. We have found that system enables multiple equilibrium point E f(x) ((β/α)f(x), (βγ/α + κ)f(x), −(βγ/α + κ)f(x)) which depends on the control parameter and nonlinear function. A stability analysis at E f(x) can be carried out using the corresponding Jacobian matrix as: Moreover, the eigenvalues of the Jacobian matrix yields the characteristic equation |J − λI| at E 0,1 as: where, c 0 = f 0 (x). For example, let f(x) equal to − 1 and 1 gives the solution for the characteristic polynomial Equation (11) as (−2.53, −0.231 ±0.932i) and (−1, −1, −0.7) with instance control parameter (α = 1, β = 2.5, γ = 0.9, κ = 0.9) which supports both stable equilibrium. It gives the proof of multistability property at different equilibriums of the proposed system as [29,30]. On the other hand, an alternative proof of chaoticity with parametric values (α = 1, β = 2.5, γ = 0.9, κ = 0.09) and initial condition (0.1031, 0.3556, -0.356) generates the Lyapunov exponents (0.025, 0, -2.05) with the Kaplan-Yorke dimension 2.018. A numerical simulation for phase orbit of single scroll in x 1 −x 2 plane is shown in Figure 3(b). A series of investigation of the proposed chaotic system in Equation (7) by tuning individually α, β, κ or γ value by keeping other parameter constant produces bifurcation diagram as shown in Figure 4. In addition to the observed behaviour of the attractor w.r.t the initial condition, a plot of basin of attraction for the chaotic system with (α = 0.7, β = 2.5, γ = 0.9, κ = 0.09) is shown in Figure 5 using numerical simulation in MATLAB. It informs different attraction regions for the initial condition in the x 1 (0) vs x 2 (0) initial plan with x 3 (0) equal to 0.1. Here, different colours in local basins of attraction represent the different chaotic states in two initial plane viz. blue region leads to periodic behaviour and yellow region leads to chaotic behaviour. Local basin of attraction in Figure 5 indicates the absence of strange attractors of the system with initial conditions near the origin. Therefore, strange attractor of the system is hidden.

| WORKABILITY TEST
An implementation of the theoretical chaotic model is validated for the practical feasibility using post layout simulation. The circuit of a continuous-time MOS IRC chaotic system is integrated with 0.18 μm CMOS technology parameter and well simulated in Cadence Virtuoso platform. Figure 6 shows the chaotic system which involves only active MOS resistor for ease of integration and the appropriate value of the resistance can be achieved by adjusting the value of V R1 , V R2 and V R . To justify the theoretical investigation post layout simulation is performed with standard component values as C 1 = 10 nF, C 2 = C 3 = 1 nF, R = 10kΩ, R 2 = 2.5kΩ and R 1 as a potentiometer of 1 kΩ as a dominant parameter. By tuning the value of R 1 from 100 Ω to 300 Ω, system nature changes from a period doubling to a chaos.
To justify the numerical simulation results more precisely, we have performed the advance simulation using Cadence Virtuoso tool comprising a post layout simulation. Figure 6 shows the post layout high frequency (up to MHz) time series waveform (V C1 , V C2 and V C2 ) with R 1 =190 Ω. Figure 7  The proposed IRC based chaotic system offers both Rossler and Lorenz like dynamics with minimum number of active and passive components in comparison to available scientific study. Table 1 gives a complete comparative study of the existing chaotic system with the proposed one in terms of active and passive components count, CMOS technology parameter, power dissipation, frequency of operation and nonlinear function. In addition, the proposed chaotic system does not require any external nonlinear element as in [9] and [17][18][19][20][21][22][23][24][25][26]. However, the proposed chaotic system utilises minimum number of transistor as compared to [9,17,19,21,22,25,26]. Moreover, a simple IRC chaotic circuitry using MOSFET dissipates very less power (μW) and is suitable for high frequency operation (MHz). In comparison to available hidden attractors with multistable property [29][30][31], the proposed design is free from multiplier term and passive inductor unlike [17,19,24,26] and suitable for simple chaotic system with multistability property, less chip area and fully CMOS based design with only few grounded capacitors. Hence, the proposed design may be suitable for the monolithic integration.

| CONCLUSION
A new design of a simple MOS IRC ring oscillator-based chaotic system is implemented. The discovery of the proposed system with scaled inverse tangent function is striking, because of hidden attractor with a unique multistability property in an autonomous chaotic system. Various bifurcation diagrams are observed resulting in the formation of different types of chaotic attractors. The post layout simulation results follow numerical values and confirm the workability of the proposed chaotic model. It is important to note that proposed circuit provides the following attractive features as (i) simple and versatile design, (ii) utilisation of CMOS, (iii) compact structure without the involvement of inductor, (iv) high frequency and low power dissipation and (v) fully CMOS chaotic system suitable for IC fabrication as compared to previously suggested chaotic circuits. A major advantage of a fully CMOS-based chaotic circuit is having an integration capability which will be fully applicable for the analogue, digital and mixed-mode design.