An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

Natural Science and Engineering Research Council of Canada Abstract This study presents an 8‐bit delay line digital‐to‐time converter (DTC) with pre‐skewing and digital time interpolation. Pre‐skewing that lowers the per‐stage‐delay of delay lines beyond that set by the chosen technology is investigated. A cascode tri‐state inverter is proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC are examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator is analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing linearity, is obtained. The timing errors of DTC are investigated and the considerations of the layout of the DTC are examined. The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. Post‐layout simulation results show the DTC offers 3.6 ps resolution, 580 MS/s conversion rate, and consumes 383 μW.


| INTRODUCTION
Time-to-digital converters (TDCs) are the key blocks of timebased signal processing systems and TDCs with a high resolution are important in a broad range of applications. The resolution of popular flash TDCs is lower-bound by the minimum per-stage-delay set by the chosen technology. The resolution of Vernier TDCs can be an order of magnitude higher when compared with that of their flash counterparts. The large variation of per-stage-delay caused by process uncertainty, however, severely limits their ability to achieve a high resolution [1]. Although delta-sigma operations are capable of yielding a high resolution, the unavailability of high-order time integrators presently impose a stiff challenge in the realisation of high-order delta-sigma TDCs needed for achieving a high resolution [2][3][4][5][6]. Successive approximation register (SAR) TDCs shown in Figure 1a distinct themselves from others with a number of unique characteristics including a low sensitivity to process uncertainty, low power consumption, and full compatibility with technology. They are viable candidates for high-resolution TDCs [7][8][9][10]. The resolution of an SAR TDC is set by that of its digital-to-time converter (DTCs). DTC can be realised using a binary-weighted capacitor array with the drawback of a large area and a high level of dynamic power consumption [7,11,12]. DTC can also be realised using a delay line and a multiplexer, as shown in Figure 1b. These TDCs enjoy the advantages of a small area, a low level of power consumption, and full compatibility with technology with the limitation that resolution is lower bound by the per-stage-delay of the delay line set by the chosen technology [13,14]. This article investigates two techniques, namely pre-skewing and digital time interpolation, to improve the resolution of delay line DTCs beyond per-stagedelay set by chosen technology [15]. The article is organised as follows: Section 2 investigates pre-skewing in lowering the per-stage delay of delay lines beyond that set by chosen technology. Section 3 studies digital time interpolators. Section 4 presents the design of an 8-bit DTC utilising both pre-skewing and time interpolation. In Section 5, design considerations including the maximum slope of the input of time interpolators, timing errors, and the layout of the DTC are examined. Section 6 provides the post-layout simulation results of the DTC. The article is concluded in Section 7.

| PRE-SKEWED DELAY LINE
Pre-skewing that utilises the output of the earlier stages of a delay line to pre-charge/pre-discharge the load capacitor of the current stage of the delay line is effective in lowering the per-stage-delay of the delay line [16][17][18][19]. Figure 2a shows a pre-skewed delay line with one pre-skewed inverter per stage. Let V a and V b be the voltages beyond which NMOS or PMOS transistors conduct, respectively. If no pre-skewing exists, V E will start to rise at t 5 . When the pre-skewed inverter is present, V E will start to rise at t 3 at which the pre-skewing signal comes to effect, the charging process will then be accelerated at t 5 at which the primary input V D comes into action. It is noted that since the capacitance at node E increases due to the addition of the pre-skewed inverter, V E rises slower as compared with that without pre-skewing. Figure 2b compares the input and output of conventional and pre-skewed inverter. It is seen that the pre-skewing signal v 1a gives rise to an early drop of v o1 prior to the arrival of the primary input v 1b . v o2 ; on the other hand, will drop only after the arrival of v 2 . It was shown in [20] that preskewing will be more effective when the number of pre-skewed inverters is small and its effectiveness will fade away once the number of pre-skewed inverters becomes large. Also, the speed gain from pre-skewing is at the cost of more power consumption and silicon area.

| DIGITAL TIME INTERPOLATION
Time interpolators that generate sub-transition edges between two transition edges can be loosely classified into analogue time interpolators and digital time interpolators [21,22]. Analogue time interpolators obtain a fine time resolution using the digitally weighted tail current of differential amplifiers. They suffer from high power consumption, poor linearity, and poor compatibility with technology [23]. Digital time interpolation generates sub-transition edges using digital circuits only. It can be performed using resistor-based voltage division with the drawbacks of a low degree of interpolation and nonnegligible static power consumption [24,25]. It can also be performed using digitally weighted inverter arrays with the advantages of full compatibility with technology, no static power consumption, fast interpolation, and a high degree of interpolation [22,[26][27][28]. The output of a digital time interpolator with inputs x 1 and x 2 is given by where 0 < α < 1 is the interpolation word. By varying α, a set of sub-edges between x 1 and x 2 are obtained. The adjustment of α is typically achieved by gating a set of identical inverters such as gated inverters [26], switched inverters [27], tri-state inverters [22], or current-starved inverters [28], as shown in Figure 3. For example, for 3-bit interpolation, a total of 16 identical gated inverters are needed, eight connected to x 1 and eight connected x 2 . The interpolation word of x 1 is set by thermometer codes 00000000 ∼ 1111111, corresponding to α = 0/8 ∼ 8/8. Similarly, the interpolation word of x 2 is set by the thermometer codes 11111111 ∼ 00000000, corresponding to 1-α = 0/8 ∼ 8/8. The interpolation words of x 1 and x 2 are complementary to each other. When interpolation cell is inactive, its output should not be impacted by the signals to be interpolated ideally. Otherwise, the linearity of the interpolator will deteriorate. Gated inverter shown in Figure 4a offers good input-output isolation when the cell is not selected, or its input is grounded [26]. Switched inverter in Figure 4b suffers from poor input-output isolation due to the existence of a direct path from the input to the output formed by the gate-drain capacitance of the transistors [27]. Tri-state inverter in Figure 4c provides good input-output isolation [22,29]. Current-starved inverter in Figure 4d offers the advantage of a constant output current, and subsequently has a better linearity but suffers from the need for current sources of a constant current. In addition, it also suffers from poor input-output isolation [28,30,31]. Cascode tri-state inverter shown in Figure 4e is proposed here. It provides improved input-output isolation as compared with the tri-stage inverter in Figure 4c. Figure 5 compares the input-output isolation of a tri-state inverter and that of a cascode tri-state inverter. It is seen that due to the larger dimension of PMOS transistors, charge injection and clock feed-through cause the output voltage of the tri-state inverter cell to climb steadily whereas their impact on the output voltage of the tristate cascode inverter is negligibly small.
In the vicinity of the threshold-crossing of the inverters, transistors operate in saturation and function as current sources. The output current of the time interpolator is the sum of that of the inverters, yielding a good linear relation between interpolation word and the output current of the interpolator. Should the total output capacitance of the time interpolator be independent of the interpolation word, a perfect linear relation between the output voltage of the time interpolator and the interpolation word will exist. Consider the case where the time interpolator is made of a set of identical gated cascode inverters shown in Figure 3(e). The total output capacitance of the inverter is given by C gd,n + C gd,p when S = 1 and C db,n + C db,p when S = 0 where C gd,n and C gd,p are the gate-drain capacitance of NMOS and PMOS transistors in triode, respectively, and C db,n and C db,p are the drain-substrate capacitance of NMOS and PMOS transistors, respectively. Although C gd,n and C gd,p in triode are much larger as compared with C db,n and C db,p and since the total number of cascode inverters switched on and those switched off is equal to the number of the bits of the interpolation word, and the total output capacitance of the time interpolator is independent of the interpolation word, thereby ensuring that a linear relation between the interpolation word and the output voltage of the time interpolator exists.
In the vicinity of threshold-crossing, the transistors of the interpolator operate in saturation and function as the current source, however, with a non-zero output conductance g o , as shown in Figure 6. The dependence of the current flowing through g o on the output voltage of the interpolator and the input dependence of g o evidenced from where μ n is the surface mobility of free electrons, C ox is the gate capacitance per unit area, and λ is the channel length modulation coefficient with the signals to be interpolated giving rise to a nonconstant output current. This is a fundamental cause of the non-linearity of digital time interpolators.
The linearity of the digital time interpolators is also affected by the slope of the signals to be interpolated. If the rise time t r of the signals to be interpolated is small, the output of the interpolator y will remain unchanged in time interval [t 1 , t 2 ], giving rise to non-linearity, as illustrated Figure 6 [32]. To avoid this, a slope control block (SCB) that sets the slope of the signals to a desired value prior to interpolation is needed  [27]; (c) tri-state inverters [22,29]; (d) Current-starved inverters [28,30,31]; and (e) cascode tri-state inverters LEE ET AL. [31,33]. Lowering the slope of the output voltage of the SCB is at the expense of more power consumption due to the shortcircuit current of the downstream time interpolator. Figure 7 shows the schematic of a 2-bit digital time interpolator with cascode tri-state inverter cells. The load of the interpolator is an inverter. Figure 8 shows the output of the interpolator in TT and at FF and SS corners. It is seen that latency exists between the input and output of the interpolator, arising from the large capacitance at the output of the interpolator. It is also observed that the impact of the process uncertainty on the latency of the interpolator is the least at the FF corner and largest at the SS corner. Figure 9 plots the differential non-linearity (DNL) and integral nonlinearity (INL) of the interpolator. It is seen that both DNL and INL of the time interpolator are small, revealing its excellent linearity. It is also observed that the impact of the process uncertainty on DNL and INL is negligible. Figure 10 plots the DNL and INL of the interpolator with supply voltage varied by ±10%. It is seen that the fluctuation of the supply voltage impacts the DNL and INL of the time interpolator rather marginally. Figure 11 plots the DNL and INL of the interpolator at various temperatures. It is seen that temperature variation impacts the DNL and INL of the time interpolator negligibly. Figure 12 compares the DNL and INL of 4-bit time interpolators with switched inverters, tri-state inverters, and cascode tri-state inverters. It is seen that the time interpolator with cascode tri-state inverters outperforms the rest and was chosen.   Figure 13. Input bits D 8 D 7 D 6 D 5 are assigned to a 16-stage pre-skewed delay line for coarse digitalto-time conversion and D 4 D 3 D 2 D 1 are assigned to a 4-bit digital time interpolator for fine digital-to-time conversion. Dummy stages are added to both ends of the pre-skewed delay line to ensure that the per-stage-delay of the stages multiplexed by the downstream multiplexer is the same. A transmission-gate (TG) multiplexer is chosen for its ease of accommodating a large number of inputs [26]. Dummy TGs are added at both ends of the multiplexer to ensure the capacitance of every input node of the multiplexer is the same. Buffers made of two cascaded inverters are inserted between the pre-skewed delay line and the multiplexer because the input capacitance of the TG multiplexer varies with its select word, as seen in Figure 14. If buffers were not added, the per-stage-delay of the pre-skewed delay line would vary each time the multiplexer select word changes. Figure 15 shows with the presence of the buffers, the impact of the varying input capacitance of the downstream TG multiplexer modulated by its select word vanishes. In order for the preskewed delay line to provide the delay that corresponds to D 8 D 7 D 6 D 5 , only one bit of TG select word is set to 1. A decoder that maps D 8 D 7 D 6 D 5 to a 16-bit multiplexer select word that has one 1 and fifteen 0s is needed. The truth table of such a decoder is shown in Table 1. The TGs of the multiplexer are arranged in such a way that not only the edges corresponding to D 8 D 7 D 6 D 5 are selected and conveyed to the time interpolator, the capacitance seen at each input node of the multiplexer is independent of multiplexer select word. Since the capacitance at the output nodes of the multiplexer is excessively large arising from the large number of TGs connected to it, a pair of buffers is employed at the outputs of the multiplexer to set the slope of the input of the downstream time interpolation to the desired value. Note that the isolation buffers inserted between the pre-skewed delay line and the multiplexer do not affect the slope of the input of the time interpolator, subsequently its linearity. A binary-tothermometer converter (BTC) that maps D 4 D 3 D 2 D 1 to a 16bit thermometer code interpolation word is needed. Table 1 gives the truth table of the decoder (Table 2).
To illustrate how the DTC operates, let the input of the DTC be 01000001, as shown in Figure 16. The upper 4 bits of the input, 0100, are mapped to the 16-bit code 0000000000010000. TGs highlighted in Figure 16 are switched on, allowing T 4 and T 5 to be conveyed to the time interpolator. The lower 4 bits of the input, 0001, are mapped to the 16-bit thermometer code

| Maximum slope of the interpolator inputs
The slope of the inputs of the time interpolators needs to be properly set in order to minimise the latency without jeopardising the linearity of the time interpolators. Prior studies showed that the slope of the signals to be interpolated needs to be at least 3 ∼ 5 times the space between the inputs, however, without any analytical support [31][32][33]. Here, we derive the analytical relation between the slope of the signals to be interpolated and the space between them with the constraints of the minimum latency. To simplify analysis, we assume that the transistors of the interpolator operate in saturation throughout 0 ∼ V DD . In Figure 17a, for time between A and C, although x 1 varies with time linearly, x 2 remains at 0. Similarly, for the time between D and B, x 2 varies with time linearly, whereas x 1 remains at V DD . In both cases, y exhibits a high degree of non-linearity. In Figure 17b, for time between A and B, both x 1 and x 2 vary with time linearly and y has a linear relation with x 1 and x 2 . In Figure 17c, for the time between A and B, although x 1 and x 2 vary with time linearly and y has a linear relation with x 1 and x 2 , the slope of the signals to be interpolated is unnecessarily low, resulting in excessive latency. Figure 17b thus gives the maximum slope of the inputs at which the latency of the interpolator is minimised without linearity degradation. The maximum slope of x 1 and x 2 , denoted by S max , is therefore given by S max = V DD /(2T in ). The rise time of the inputs, denoted by τ rise , is the amount of time for the inputs to rise from 10%V DD to 90% of V DD V. Since The preceding approach, although simple, conveys a valuable insight on how the slope of the input affects the linearity of the interpolator. In what follows we present a more rigorous analysis. Using pinch-off condition, one can show that the NMOS and PMOS transistors of the interpolator will operate in saturation if V Tn < v in < v o + V Tn and v o −| V Tp | < v in < V DD −|V Tp |, respectively, where V Tn and V Tp are the threshold voltage of NMOS and PMOS transistors, respectively. Assume that the NMOS and PMOS transistors of the interpolator are saturated when V Tn < v in < V DD and 0 < v in < V DD −|V Tp |, respectively. In Figure 18a, for the time between A and D, the NMOS transistor of the interpolator whose input is x 2 does not operate in saturation. Similarly for time between C and B, the PMOS transistor of the interpolator whose input is x 1 does not operate in saturation. In both cases, y exhibits a high degree of non-linearity. In Figure 18b, for time between A and B, both NMOS and PMOS transistors of the interpolator operate in saturation. y has a linear relation with x 1 and x 2 . In Figure 18c, for time between A and B, although both NMOS and PMOS transistors of the interpolator operate in saturation and y has a linear relation with x 1 and x 2 , unnecessary latency exists due to the overlying small slope of the inputs. Figure 18b thus gives the minimum latency without sacrificing linearity. The slope of x 1 , denoted by S 1 , and that of x 2 , denoted by S 2 , are given by The rise time of the input τ rise is obtained from (0.9V DD − 0.1V DD )/τ rise = 0.15/T in from which we arrive at τ rise ≈ 5.3T in . The rise time of the inputs of the interpolator needs to be approximately 5 times the time space between the inputs in order to ensure that the transistors of the interpolator operate in saturation. This result agrees with the prior studies [31,32]. Figure 19 plots the dependence of the INL of the 4bit time interpolator investigated earlier on T in /τ. It is seen that INL deteriorates exponentially with the decrease of τ or equivalently the increase of the slope of the inputs of the interpolator.

| Timing error
Device noise gives rise to timing errors in both the pre-skewed delay line and time interpolator. In this section, we provide a mathematical treatment of the timing errors of the DTC. Now, we investigate the timing error in the charging process of an inverter. The results can be readily used for the timing errors of the discharging process.

| Thermal noise-induced timing error
Consider the charging process shown in Figure 20. Prior to the start of the charging process, the NMOS transistor operates in triode and functions as a resistor r on with a thermal noise voltage source v n;r on;p whose power spectral density is given by S v nc;t1 ¼ 4kT r on;p where k is Boltzmann constant, T is temperature, and r on,p is the channel resistance. v n;r on;p generates noise voltage v nc,t1 across the capacitor with its power obtained from After the charging process starts, the PMOS transistor will operate in saturation when v c < |V Tp | and triode when v c > |V Tp |. To simplify analysis, we assume that the PMOS transistor functions as a current source over 0 ≤ v c ≤ V DD /2, an approach used in [34]. The thermal noise and flicker noise of the channel current of the transistor are integrated onto the load capacitor over [0, t*] where t* is threshold-crossing time. Noise integrated onto the capacitor afterwards t* does not contribute to timing errors. The noise voltage of the capacitor due to the thermal noise current i n,t of the transistor, denoted by v nc, t2 , is given by [34].
where w(t) = u(t) − u(t − t*) and u(t) is the unit step function.
The power spectral density (PSD) of v nc,t2 , denoted by S v nc;t2 , is obtained from where S i n;t ¼ 4kT γg m;p , γ ≈ 1, and g m,p is the transconductance of the PMOS transistor. The noise power of v nc,t2 due to the windowed integration of i n,t over [0,t*] is obtained using the Wiener-Khinchin theorem Making use of ∫ ∞ 0 sin 2 x x 2 dx ¼ π 2 , we obtain from (6): The total noise power of the voltage of the capacitor is obtained from: Thermal noise-induced timing error at threshold crossing, denoted by Δτ t , relates to thermal noise voltage v nc,t by the slow rate of the voltage of the capacitor at the thresholdcrossing [35,36]. v nc;t where I is the channel current. Making use of g m;p ¼ we obtain the timing error due to the thermal noise of the channel current

| Flicker noise-induced timing error
Flicker noise of the channel current also contributes to timing errors. Similar to thermal noise, the PSD of flicker noiseinduced capacitor voltage is obtained from where S i n;1=f is the PSD of the flicker noise of the channel current. Noise current whose frequency is lower than 1/T obs where T obs is observation time is indistinguishable from the DC current. The lower frequency bound of the flicker noise f L is set to 1/T obs , which is a few Hertz typically. Following the approach in [37], we assume S i n;1=f = 0 in [0, f L ]. Since the PSD of flicker noise referred to the gate of the transistor is given by where K f,p is a process-dependent constant for PMOS transistors, C ox is gate capacitance per unit area, W and L are the width and length of the transistor, respectively, we have The noise power of capacitor voltage due to the windowed integration of i n,1/f is obtained from the Wiener-Khinchin theorem Similar to timing errors induced by the thermal noise, the power of the flicker noise-induced timing errors is obtained from Let x = πt*f. We have x L = πt*f L . Equation (15) becomes: where x min = πt*f L . The integration in (16) can be performed using integration by parts and the result is given by where is cosine integral and Γ ≈ 0.577 is Euler-Mascheronic constant. Since f L is small, sinðx L Þ x L ≈ 1 follows. As a result, Equation (16) is therefore simplified to It is seen from (20) that flicker noise induced timing error is directly proportional to t * 2 . Increasing the channel current shortens the charging process, hence lowers both Δ 2 τ t and Δ 2 τ 1=f . The total timing error due to thermal noise and flicker noise is therefore given by To estimate noise-induced timing error, we use the parameters used in [37] for a quick estimation:  duration of the discharging process is t* = 500 ps, and f L = 10 Hz. We have ffi ffi ffi ffi ffi ffi ffi ffi ffi Δ 2 τ t q ≈ 0.21 ps and ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi Δ 2 τ 2 1=f q ≈ 0.44 ps. Figure 21 (top) plots the rising edge of the output of the static inverter with transient noise included. The impact of thermal and flicker noise of the channel current is a timing error of 0.13 ps approximately. Noise-induced timing error is rather small. Figure 21(bottom) plots the output of v o1 . It is seen that the timing error of v o1 is 0.41 ps whereas that of v o2 is 0.13 ps. Timing error accumulation is evident.

| Timing error of pre-skewed delay line
The load capacitor of an inverter in a pre-skewed delay line with one pre-skewed inverter is charged by both the preskewed inverter and the primary inverter. The duration of the former is longer while that of the latter is shorter, as seen in Figure 2. Let the charging current of the pre-skewed inverter and primary inverter be I pre and I pri , respectively. Furthermore, let the charging duration of the pre-skewed inverter and primary inverter be t * pre and t * pri , respectively. The timing error due to the thermal noise and flicker noise of the pre-skewed and primary inverters is obtained from (10) and (20) The timing error of jth stage of the pre-skewed delay line, denoted by Δ 2 τ j , is obtained by summing up (22) and (23) and taking into account two primary inverters and two pre-skewed inverters per delay stage: Since the timing error of each stage of the pre-skewed delay line accumulates, the worst-case timing error of a N-stage pre-skewed delay line, denoted by Δ 2 τ P , occurring at the output of the last stage of the delay line, is given by: If Δ 2 τ j ¼ Δ 2 τ, for j = 1, 2, …, N, Equation (25) can be simplified to: This result is the same as that given in [36,38].

| Timing error of interpolator
For a M-bit digital time interpolation, a total of 2M inverters drive the same output node. Since the total number of the inverters that undergo a charging process is M, the timing error of the time interpolator, denoted by Δτ 2 I , is obtained from 5.2.5 | Timing error of digital-to-time converter The DTC consists of the pre-skewed delay line, the buffers between the pre-skewed delay line and the multiplexer, the multiplexer, the buffers between the multiplexer and the time interpolator, and the time interpolator. Only the timing error of the pre-skewed delay line and that of the time interpolator are important because the timing error of the 4-bit pre-skewed delay line DTC is 32 times that of an inverter and that of the 4bit time interpolator DTC is 16 times that of an inverter. The timing error of the DTC is therefore obtained from Figure 22 shows the layout of the DTC. No effort was made to minimise the silicon area of the DTC. The primary and preskewed inverters of the pre-skewed delay line are placed in two parallel rows so as to simplify routing between them. The buffers between the pre-skewed delay line and multiplexer are placed in parallel with the delay line. The transmission gates of the multiplexer are arranged in such a way that two long horizontal interconnects of equal length are used to route the output of the multiplexer to the buffers placed at the right of the multiplexer. In order to make sure all TGs are matched, interconnects from the buffers between the pre-skewed delay line and the multiplexer are extended over the input nodes of the TGs. The layout of the time interpolator is arranged in such a way with one set of inverters placed in one row and the other set of the inverter placed in another row parallel to the first one.

| SIMULATION RESULTS
The preceding 8-bit DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. The per-stage delay of the pre-skewed delay line with buffers is 58 ps. The longest delay of the pre-skewed delay line occurring when D 8 D 7 D 6 D 5 = 1111 is therefore given by 58 �16 = 928 ps, leading to the conversion range of the DTC: 3.6 ps~928 ps. The delay of the multiplexer with its output buffers included is 587 ps. The longest delay of the time interpolator is 206 ps, occurring when D 4 D 3 D 2 D 1 = 1111. The worst-case conversion time of the DTC is therefore obtained from: 928 + 587 + 206 = 1721 ps, yielding the minimum conversion rate: 1/1721 ps = 580 MS/s. Figure 23 plots the DNL and INL of the pre-skewed delay line. The selection word of the pre-skewed delay line is the buffered output of an ideal analogue-to-digital converter (ADC). It is seen that the DNL and INL of the pre-skewed delay line are negligible small, revealing its excellent linearity. Figure 24 plots the DNL and INL measured at the output of the multiplexer. The selection word of the multiplexer is generated in a similar way as that of the pre-skewed delay line. It is seen that the DNL of the multiplexer is rather small. The INL of the multiplexer is less than 0.3 LSB. Figure 25 plots the DNL and INL of the time interpolator whose interpolation word is generated in a similar way as that of the pre-skewed delay line. It is seen that both DNL and INL of the time interpolator are small. To test the DTC, the input of the DTC is generated using a Verilog-A coded ADC with a properly chosen ramping voltage input such that the output of the ADC varies from -13 00,000,000 to 11,111,111. The generated digital output is buffered before being applied to the DTC. Figure 26 plots the DNL and INL of the DTC (post-layout with R + C extraction). It is seen that the DTC exhibits good DNL and INL. Figure 27 plots the DNL and INL of the DTC (post-layout with R + C + CC extraction) with the inclusion of the impact of coupling capacitors between interconnects and devices. It is seen that the DTC exhibits a good DNL but a deteriorating INL. Further investigation into the cause of the deteriorating INL reveals that when the selection word of the multiplexer changes, there is a consistent slight shift of the thresholdcrossing point of the inputs and output of the multiplexer, possibly caused by the asymmetry of the interconnects, the charge injection of the TGs, the consistent voltage shift along the two long interconnects connecting the output of the TGs and the input of the output buffers of the TGs, and unequal distance between the output of each TG and the output buffers that are located to the right of the multiplexer. TG-based multiplexer, though convenient in accommodating a large number of inputs, is rather sensitive to the impact of charge injection into the source and drain node of the TGs where the input and output of the multiplexer are connected, respectively. Multiplexers that can accommodate a large number of inputs routed to the gate rather than source/drain of transistors, so as to minimise the effect of charge injection, are being developed.

| CONCLUSIONS
An 8-bit delay line DTC with pre-skewing and digital time interpolation was presented. Pre-skewing that lowers the perstage-delay of delay lines beyond that set by chosen technology was investigated. A cascode tri-state inverter was proposed to improve the isolation between the input and output of interpolation cells so as to improve the linearity of the time interpolator. Design considerations that critically affect the linearity of the DTC were examined in detail. The impact of the slope of the inputs of the time interpolator on the latency and linearity of the interpolator was analysed and the maximum slope of the input of interpolators yielding the minimum latency without sacrificing the linearity was obtained. Device noise-induced timing errors of DTC were investigated and the results were compared with simulation results. The post-layout simulation results show the DTC exhibits a good DNL and INL with R + C extraction and INL deteriorates when coupling capacitors are included in the layout extraction. An in-depth investigation of the cause of the deteriorating INL indicates the chosen TG-based multiplexer, though convenient in accommodating a large number of inputs, is sensitive to the impact of the charge injected to the source and drain of the TGs, which are the input and output of the multiplexer, respectively. The proposed DTC consumes only 383 μW power with the maximum conversion rate of 580 MS/s.