CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance

National Natural Science Foundation of China, Grant/Award Number: 61601050; BUPT Excellent Ph.D. Students Foundation, Grant/Award Number: CX2020302 Abstract A pole‐converging X‐band low‐noise amplifier (LNA) using 130 nm CMOS technology is proposed. An on‐chip pole‐converging capacitor CPC is added between the gate and drain node of the common‐gate (CG) stage. The capacitor CPC combines with a noise‐ reducing inductor L1 to converge poles into the desired band, which results in a pole‐ converging effect and wideband performance. The proposed modified broadband simultaneous noise and input‐matching technique is adopted in triple‐cascode configuration to realize good input matching and a low noise figure (NF). Measurement results exhibit a flat maximum power gain of 17.6 dB from 8 to 12 GHz and a reverse isolation over 60 dB within the desired bandwidth along with an NF ranging from 1.5 to 3.6 dB. The LNA core dissipates 17 mW from 2.4 V supply, and the chip size occupies 1.1 � 0.9 mm including all pads. The simulated and measured results show good agreement from 8 to 12 GHz.

network as shown in Figure 1 to simultaneously extend bandwidth and reduce NF. Furthermore, the triple-cascode configuration can utilize higher supply voltage to tolerate higher input signals than with conventional cascode LNAs.
The rest of this paper is organized as follows. Section 2 analyses the modified broadband simultaneous noise and input-matching (MBSNIM) technique to reduce noise with a good input-matching network and calculates the NF explicitly. Further, the noise-reduction technique based on conventional cascode configuration is discussed. In Section 3, we present a bandwidth extension technique by introducing a new pole in the desired band with a pole-converging network. In Section 4, MBSNIM and bandwidth extension techniques are applied in the X-band LNA, and measured results are compared with simulated results. The conclusions follow in Section 5.

| INPUT-MATCHING AND NOISE ANALYSIS OF TRIPLE-CASCODE CONFIGURATION
The proposed triple-cascode LNA architecture is shown in Figure 1. Transistors M 1 and M 2 are used as common-source (CS) and common-gate (CG) amplifiers, respectively, connected in cascode conventional configuration. In this architecture, a MBSNIM network is designed by utilizing an inductive source degeneration technique and a small additional capacitance C GD . To simultaneously extend the bandwidth of conventional cascode LNA and reduce the noise contribution of CG stage, inductor L 1 is introduced and placed between two CG stages, as shown in Figure 1. A pole-converging C PC is added between the gate and source node of M 2 , and this capacitance combined with L 1 can form a new pole near the peak-gain frequency that results in flat and wideband gain response. To achieve high linearity and tolerate stronger input signals, we use a triple-cascode configuration with high supply voltage that can relieve the voltage stress on M 1 , M 2 , and M 3 . Table 1 summarizes the component values used in the design.

| Input-stage analysis
To deliver maximum power from the antenna to the LNA, input matching is required at the input port of the LNA. Considering the input matching and noise performance, two configurations can be employed in LNAs, the CS and CG configurations. The CG configuration [12][13][14][15] is known for its characteristic of wideband input matching, but it suffers from low gain and poor noise performance. A degenerative inductor can be used in the CS configuration to provide real input impedance without sacrificing noise performance. The CS configuration is usually used in narrowband applications, and a negative feedback technique [16] can be utilized to extend the bandwidth of the input-matching network. However, the negative feedback technique will degrade noise performance compared with the conventional simultaneous noise and input matching (SNIM) technique. On the other hand, the conventional SNIM technique suffers from narrowband input-matching performance because of its simple input-matching network. For X-band applications, we propose a MBSNIM technique utilizing parasitic capacitance C gd or augmenting an additional small capacitance C GD in parallel with the CS configuration to achieve low-noise and enhanced wideband input-matching performance. ABCDparameters and Thevenin noise parameters transformed from Norton noise parameters are utilized to derive the noise performance for an inductively degenerated LNA [17]. After complicated algebraic derivations, three modified key noise parameters in the inductor-degenerated CS configuration, the transformed noise conductance G n , uncorrelated noise resistance R u , and correlated noise impedance Z c can be expressed as [17] where R n is the noise resistance, G u is the uncorrelated noise conductance, and Y c is the correlated noise admittance, respectively. The parameters δ and γ are constants describing gate-induced noise current and channel noise current, which have different values in long-channel and short-channel devices. c is the correlation coefficient between the channel noise current and gate-induced noise current. According to the noise parameters in Thevenin format [18,19], the optimal noise impedance can be expressed as Z opt ðωÞ ¼ R opt ðωÞ þ jX opt ðωÞ ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi According to Figure 2, the tedious algebraic derivation for noise parameters can turn to the equations according to noise transformation matrices in the series feedback and cascade configuration in [17,20]. The calculation process is briefly described in the Appendix.
According to Figure 2, s 0 and s in the Appendix represent the scattering parameters of the two-port network. Then, three key noise parameters in the inductordegenerated CS configuration, the transformed noise conductance G n , uncorrelated noise resistance R u , and correlated noise impedance Z c can be calculated with the noise transformation matrix. By adding an additional capacitance C opt , as shown in Figure 1, between the gate and source node of the transistor M 1 , the optimal noise impedance seen from the gate node of the CS stage can be expressed as Z opt ðωÞ¼ α ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffiffi where We propose an insightful vector analysis to simplify the tedious calculation of noise parameters. The noise source I nd can be transferred as the input noise source V ndi , I ndi . The two input noise sources V ndi , I ndi are correlated, so for simplicity they are modelled as two collinear vectors. The induced gate noise I ng �! is decomposed into the correlated noise source I ngc �! and uncorrelated noise source I ngu �! . The vector I ngc �! is collinear with vector I ndi �! , and the uncorrelated noise source vector I ngu �! is perpendicular to vector I ndi �! . The 2-D vector operation to combine the three partially correlated noise sources is shown in Figure 3. According to the 2-D vector analysis, the new noise parameters can be derived as the new noise sources I nnew and V ndi with I ng , I nd . The following equation can be derived: c ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi I nnew ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi I nnew ��! ¼ ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi To achieve good noise performance and good input matching, the optimal noise impedance should be equal to the conjugate impedance seen from the gate node [18]. Thus, we have the following equations: By choosing the proper transistor size, the LNA can simultaneously achieve good input matching and good noise performance. On the other hand, by adding a parallel CAO ET AL. capacitance between the gate and source node of transistor M 1 , we can choose a smaller transistor to obtain the desired optimal noise impedance at the operating frequency. Thus, the power can be reduced with a relatively small transistor size. This technique is named power-constrained SNIM [21]. We design the LNA based on the MBSNIM technique. The input impedance seen from the gate node can be expressed as Z L in Equation (6) represents the load seen from the drain node of CS stage. Generally, it can be modelled as a load impedance when neglecting the parasitic capacitance for simplicity. By inserting an inductance between the drain node of transistor M 1 and source node of transistor M 2 , it can be expressed as R L + jX L . According to Equation (6), the generalized derivation of −10 dB bandwidth for input matching can turn to the following equations from our previous work [22]: ω x,H and ω x,L can be solved by turning to the equations listed in (8)- (11). Based on the MBSNIM technique, the LNA can theoretically extend the input-matching bandwidth by about 40% compared with the SNIM technique and good noise performance. According to the above discussion, the additional capacitor C opt , C GD will decrease the optimal noise impedance according to Equation (3), which results in deceased deviation between the optimal noise impedance and conjugate of the input impedance. On the other hand, by augmenting the capacitor C opt , C GD , the imaginary part of the input impedance will shift to the inductive region slightly. The input-matching condition requires a smaller inductance to achieve input matching. Consequently, the deceased inductor with smaller parasitic resistance will to some extent improve noise performance. The MBSNIM process is conceptually sketched in Figure 4. Figure 4a illustrates the locus of input impedance and optimal noise impedance with increased capacitance of C opt , C GD in the range between 20 and 100 fF. By choosing the proper inductor and capacitor, the optimum of source reflection coefficient S opt and input reflection coefficient S 11 can be brought closer together nearer to the centre of the Smith Chart as shown in Figure 4b, which results in a SNIM condition. We design the circuit following the indication of MBSNIM technique and simulate the circuit iteratively by a trade-off between input matching, noise performance, and gain performance at the operating frequency. F I G U R E 2 Transformation of the two inner noise sources into two outer noise sources. (a) Input-referred noise voltage and current of A α in series-series feedback configuration; (b) Inputreferred noise voltage and current of A 1 in seriesseries feedback configuration; (c) Inner inputreferred noise voltage and current in cascade configuration; (d) Outer input-referred noise voltage and current in cascade configuration F I G U R E 3 Vector diagram to analyse noise parameters for conventional transistor equivalent model

| Noise figure calculation
To calculate the NF of the proposed triple-cascode LNA, we simply derive the NF of the generalized cascode configuration as shown in Figure 5, provided that the CG stage makes a small contribution to overall noise performance. The NF is calculated to be the ratio of the output noise power to the output noise power contributed by the signal source as shown in (12), where i o,ns is the mean-squared output noise current of the source terminal, i o,nd and i o,ng represent the mean-squared output noise current caused by the channel noise source and gate-induced noise source, respectively. ð10Þ F I G U R E 4 Simulated locus of the input impedance and the optimal noise impedance with increased capacitance of C opt , C GD in the range between 20 and 100 fF; (b) Conceptual modified broadband simultaneous noise and input-matching results where k B is the Boltzmann constant, T is the absolute temperature, g d0 is the conductance of the transistor M 1 when the voltage between the drain and source node equals to zero, and Δf is the bandwidth, respectively [19]: To calculate the NF, we can solve the transfer functions of different noise sources to the output noise current independently by turning to small-signal equivalent circuit analysis as shown in Figure 5. The proposed generalized CS circuit model considering C GD and three different noise sources is shown in Figure 5a. The smallsignal equivalent circuit for calculation of i 2 o;ns is shown in Figure 5b, and the output noise current caused by source terminal can be expressed by Equation (13) [21]. The output correlated gate noise currents can be expressed as Equation (17). As shown in Figure 5d, the output meansquared channel noise current can be calculated as Equation (18). Based on the listed equations, the NF can be finally expressed as Equation (19). i o,nRg,R1 represents the output noise current caused by the parasitic resistance R 1 of inductor L g and gate resistance R g of transistor M 1 .

| Noise-reduction technique
As shown in Figure 5, the above analysis derives the NF of the CS stage neglecting the noise contribution of the subsequent CG stage in a conventional cascode LNA. As the operating frequency increases, the NF can be further degraded by parasitic capacitance [23,24], as shown in Figure 6. For simplicity, we analyse the conventional cascode configuration and consider the noise contribution of the CG stage. The small-signal equivalent circuit of conventional cascode LNA is shown in Figure 6b. The noise sources in the CS stage are modelled as equivalent input-referred voltage and current noise sources. The output current caused by the source terminal and channel noise source can be calculated based on the small-signal equivalent circuit shown in Figure 6b. Dnos1¼ The NF of the cascode LNA [23] considering the parasitic capacitance can then be simply expressed as As frequency increases, the parasitic capacitance will degrade the noise performance. To reduce the noise contribution of the CG stage, an inductor is augmented between M 1 and M 2 , and the impedance seen from the source node of transistor can be written as assuming the output resistance of the CS is infinite. Then, the noise contributed by V n2 [24] at the output port can be expressed as where Z x can be re-expressed as By combining Equations (25) and (26), it can be easily found that Z x will approach infinity when the inductor resonates with the capacitances, and thus, the noise contribution of CG stage in output noise will be eliminated. The inductor [24] can be calculated as F I G U R E 6 (a) Circuit for calculation of noise figure of cascode configuration; (b) Equivalent circuit for calculation of noise figure of cascode configuration CAO ET AL.
In practice, we should consider the output impedance of the CS stage. Then the impedance Z x can be calculated by utilizing Thevenin's theorem and Kirchhoff's law, and we have According to Equation (28), the finite impedance will limit noise reduction to some degree. However, the additional inductor can still be utilized to reduce noise. Moreover, the additional inductor can extend the bandwidth by converging poles to the desired band to compensate for the fast roll-off of the gain, which will be derived explicitly in Section 3. In ADS, we simulate two simple conventional cascode LNAs operating at 10 and 24 GHz with an idealized circuit model ignoring the body effect and channel length modulation. The simulated results validate that the additional inductor L 1 can effectively reduce the noise contribution of the CG stage. Simultaneously, we simulate the proposed triple-cascode LNA in 130 nm CMOS process with a noise-reduction technique, and the noise contribution summary is listed in Table 2. The NF is found to be reduced by introducing the proper inductor L 1 . Simulated noise contributions by individual components of the proposed LNA are shown in Figure 7.

| Comparison of load effects between conventional common-source, cascode, and triple-cascode stages
The input impedance for the input-matching condition is discussed explicitly in Section 2. In fact, the load, which determines the resonant frequency, will change the input impedance with the existence of the capacitance C gd . According to simulation, it can be found that the resonant load condition will lead to negative impedance at operating frequency. By adding the CG stage as shown in a conventional cascode or triple-cascode configuration, the load condition seen from the drain node of the CS stage can be effectively reduced. To clarify how the CG stage affects the impedance seen by the drain node of the CS stage, we derive the input admittance in a generalized CG configuration as shown in Figure 8 [25]. According to the calculation in Equation (29) and the simulation, the impedance seen from the drain node of the CS stage can be effectively reduced. According to the simulated results in Figure 9, by introducing the triple-cascode configuration, the input impedance of the triple-cascode configuration with resonant load termination is nearly equal to the input impedance of an ideal CS stage with short load termination: T A B L E 2 Noise contribution summary of the proposed low-noise amplifier Noise source contribution Without L 1 @9 GHz With L 1 @9 GHz Without L 1 @10 GHz With L 1 @10 GHz

| Linearity of triple-cascode configuration
One difficulty that modern wireless communication and radar systems encounter is the strong signal due to high dynamic range. This imposes a high linearity requirement for the systems and LNAs. Moreover, the scaling down of CMOS technology leads to low breakdown voltage that limits output voltage swing. Transistor stacking is a promising way to achieve high output voltage swing with high linearity. Transistors M 1 , M 2, , and M 3 are stacked one by one, and the voltage at the drain node of each transistor gradually increases. The voltage of the drain node is shown in Figure 10. However, the voltage swing between the drain and source of each transistor is less than the breakdown voltage.

| BANDWIDTH EXTENSION TECHNIQUE
We know that an inductor between the CS and CG stage can reduce the NF. Furthermore, two inductors can be utilized to reduce the NF. However, to save the chip area, we intentionally place one inductor between the drain node of M 2 and the source node of M 3 . By adopting this method and with careful selection of inductance L 1 , we can effectively extend the bandwidth over that of the conventional cascode configuration. The simplified small-signal equivalent circuit of the proposed LNA core is shown in Figure 11. We can calculate the voltage gain with the following equations: According to Equation (32), the first gain peaking at low frequency is dominated by Z L , and the second gain peaking at high frequency is dominated by the pole of V out V B . When the denominator is set to 0, L res can be calculated as We can re-express the inductor L res as According to Equation (34), it can be found that the imaginary part is much less than the real part of the inductor. Hence, we can simply select a proper value of L 1 according to the second peaking frequency. According to the geometric evaluation, the frequency response equals the product of the zero vectors divided by the product of the pole vectors in s-plane. On the other hand, according to simulation, a set of poles and zeros appears nearly at the same position in s-plane, which results in poles and zeros in the vicinity having little contribution to frequency response. For simplicity, as shown in Figure 12a, we mainly focus on the poles in the desired band. According to simulation, when the inductor L 1 has a low value, there is no newly introduced pole in the transfer function. As L 1 increases from a low value to 500 pH, the new pole introduced by L 1 and C Total occurs at a high frequency outside the desired band. The newly introduced key pole 2, as shown in Figure 12a, plays a nondominant role in gain peaking. As L 1 increases from 500 to 1000 pH, the non-dominant key pole 2 is pushed towards key pole 1 and becomes dominant. Namely, the newly introduced key pole 2 enters the region of the desired band. The direction of the arrow shown in Figure 12 describes the locus of the pole when L 1 increases from 0 to 1 nH. By pushing peaks 1 and 2 towards each other or by changing the locus of the two key poles, the bandwidth of the triple-cascode LNA can be extended. To further investigate the role of the proposed pole-converging capacitance, Figure 12 presents the zoomed locus of poles with and without pole-converging capacitance. By adding the poleconverging capacitance, the key pole set p 2 will shift closer to the imaginary axis, which results in enhanced magnitudefrequency response at the high-frequency region. The locus of p 1 with pole-converging capacitance will bend to the imaginary axis as L 1 increases, which results in the second gain peaking at the low-frequency region. Figure 13 shows the simulated S 21 with pole-converging capacitance. Figure 13b illustrates the contour of S 21 as L 1 increases from 500 to 1000 pH. The pole-zero analysis and simulated S 21 with different inductor L 1 verify that the proposed technique can effectively extend the bandwidth.

| MEASUREMENT RESULTS
The proposed LNA is implemented in the GLOBAL-FOUNDRIES 0.13 μm CMOS process. The fabricated LNA is shown in Figure 14, and the die area of the whole chip is 1.1 � 0.9 mm 2 . The simulated and measured S-parameters are shown in Figure 15. The S-parameters are measured with Agilent PNA N5247 A with short-open-load-through calibration. The measured voltage gain achieves a maximum of 17.6 dB and remains a good flatness over the desired X-band. As can be seen in Figure 15a, the measured input and output reflection coefficients S 11 and S 22 are below −10 dB across the entire X-band. Figure 15b presents the measured and simulated NF and reverse isolation. The noise source for the measurement is 16,603 FB with 12-19 dB excess noise ratio. The measured NF is less than 3.6 dB over a bandwidth of 4 GHz, and the minimum NF within a 3 dB bandwidth is 1.5 dB at 8 GHz. Measured reverse isolation is better than 60 dB. The noise discrepancy between measurement and simulation results may be caused by transistor noise modelling and imperfect AC grounding at the power supply terminals of each transistor as well as imperfect ground due to bonding wires. Figure 12c shows the input third intercept point (IIP3) of the LNA at 10 GHz. A two-tone test was carried out at a midband frequency of 10 GHz with equal-amplitude 10.005 and 9.995 GHz signals. The measurement indicates an input-referred 1 dB compression point of −16 dBm. The IIP3 at different frequency with 5 MHz offset is shown in Figure 12d.   The triple-cascode LNA provides good gain flatness and low NF with comparable power consumption. In comparison, this LNA presents an improved tradeoff between power gain, NF, and bandwidth compared with conventional cascode low-noise amplifiers. As shown in Table 3, the proposed LNA implemented with 130 nm CMOS technology shows a good figure of merit (FOM) among LNAs fabricated with different processes.

| CONCLUSION
This paper demonstrated a low-noise and high gain X-band LNA with triple-cascode configuration in 130 nm CMOS process. The proposed LNA achieves 17.6 dB of maximum voltage gain, 1.5 dB of minimum NF, and power consumption of 17 mW from a 2.4-V supply voltage. The chip size of the LNA is 1 mm 2 including all the testing pads and the buffer.  The results show good agreement with measured data over the entire frequency range of interest. The proposed triple-cascode LNA has the advantages of good noise performance and good gain flatness across 8-12 GHz. Moreover, the triple-cascode configuration allows the LNA to obtain a higher OP 1dB , 3 dBm at 9 GHz, than that of a conventional cascode amplifier.