A new coplanar design of a 4 ‐ bit ripple carry adder based on quantum ‐ dot cellular automata technology

Quantum ‐ dot cellular automata (QCA) is one of the best methods to implement digital circuits at nanoscale. It has excellent potential with high density, fast switching speed, and low energy consumption. Researchers have emphasized reducing the number of gates, the delay, and the cell count in QCA technology. In addition, a ripple carry adder (RCA) is a circuit in which each full adder's carry ‐ out is the connection for the next full adder's carry ‐ in. These types of adders are quite simple and easily expandable to any desired size. However, they are relatively slow because carries may broadcast across the entire adder. Therefore, an RCA design on a nanoscale QCA is proposed to diminish the cell number, improve complexity, and decrease latency. The QCADesigner simulation tool is used to verify the correctness of the suggested circuit. The comparison results for the design indicate an approximately 49.14% improvement in cell number and 14.29% advantage in area for the state ‐ of ‐ the ‐ art 4 ‐ bit RCA designs with QCA technology. In addition, the obtained results specify the effectiveness of the offered design.


| INTRODUCTION
Over the last few years, the complementary metal oxide semiconductor (CMOS) has been the prevailing technology in the implementation of circuits [1,2]. It is extensively used in many chips such as microprocessors [3] and microcontrollers [4] because it provides for many powerful features. With the development of CMOS technology and the growing frequency of productivity at the nanoscale [5], some issues such as short channel effects and leakage energy consumption have brought significant limitations to maintaining scalability according to Moore's law [6]. These shortcomings limit the future functionality of CMOS technology [7,8].
The quantum-dot cellular automata (QCA) paradigm is an alternative CMOS technology that can develop high-speed, scalable, lower-cost, and denser structures at nanoscale [9][10][11]. Electron positions in the quantum cells play a vital role in defining the logic state in this technology [12,13]. In QCA, the voltage levels are used for binary calculation, while the QCA uses a free-electron place in the cell to evaluate logic [14][15][16][17][18]. Hence, the QCA cell's role in this technology is very important and used for logical computing, connectivity, and data transmission [19,20]. On the other hand, because a full adder is used for mathematical functions and logical operations, it is very noticeable in designing digital circuits [21][22][23][24]. In verylarge-scale integration design and QCA technology, the adder stands as an essential building block and often constitutes part of the critical path [25]. The ripple carry adder (RCA) is the simplest form of adder [21,26,27]. RCAs are quite expandable and straightforward for any desired size. However, they are relatively slow because carries may propagate across the entire adder [28][29][30].
A new design of QCA-based RCA is proposed here to improve on the features of previous designs. The QCADesigner tool is used to simulate the developed circuit [31]. The key objectives of the suggested design are � decreasing the number of cells of QCA-based RCA; � decreasing the amount of space consumed in QCA-based RCA; � reducing the complexity and latency of QCA-based RCA.
proposed design. Finally, Section 5 discusses future trends and concludes the paper.

| RELATED WORK
Several important and effective proposals to design RCA based on QCA have been presented thus far. Those designs are reviewed in this section.
Balali and Rezai [32] have suggested a new QCA-based structure for the full adder to design a high-speed, effective, and robust 4-bit RCA in QCA. These designs have been simulated using QCADesigner to test their correctness. The simulation outcomes have shown significant improvements in circuit speed and latency. Based on the results, the number of cells and circuit delay of the designed coplanar 4-bit RCA are decreased amongst the single-layer plans. The suggested 4-bit RCA has a low complexity and high-speed design. It uses 209 cells in an area of 0.3 μm 2 and latency of 1.25 clock cycles.
In addition, Rashidi and Rezai [33] have designed an efficient, one-layer, one-bit full adder architecture. The suggested architecture is suitable for creating other types of QCA-based adders such as RCA. A 4-bit QCA-based RCA architecture has been developed based on a one-bit QCA-based full adder. The QCADesigner has been used to simulate the offered QCAbased adder architectures. The simulation outcomes have shown that the suggested QCA-based architectures compared with previous modified QCA-based architectures provide improvements in delay, effective area, and layout complexity. The RCA uses 175 cells in an area of 0.14 μm 2 and 1 clock cycle of latency.
Coplanar QCA crossover architectures for designing a QCA-based RCA and full adders have been proposed by Abedi et al. [15]. Their main aim was to decrease the area consumption and number of cells. They have investigated the influence of these improvements on QCA-based adders. The proposed designs for QCA-based full adders and RCA have been tested and assessed for correctness using QCADesigner. The conventional evaluation method and a QCA-specific cost function also have been used to perform a comparison against previous methods. They have shown a 23% cell count and 48% area reduction over existing QCA-based full adder designs. In addition, the proposed RCA uses 262 cells in an area of 0.208 μm 2 and latency of 1.75 clock cycles.
Furthermore, Mohammadi et al. [34] have designed an optimized full adder to improve area, complexity, and delay. The designed adder was also used to create three different RCAs, and acceptable results have been achieved. In the new RCA designs, researchers have used a new formulation of a full adder. The obtained results using QCADesigner simulation have confirmed that the presented circuit can be used as a high-performance design in QCA because of its useful function. For designing 4-bit RCA using a new optimized full adder, 237 QCA cells in an area of 0.24 μm 2 have been used. Also, the latency of the proposed RCA is 1.5 clock cycles [34].
Chan et al. [35] have proposed a new design of 4-bit RCA. The article presents an insight into simple QCA-based digital logic design, especially RCA, using specific QCA techniques. The 5-input majority gate is used to perform this circuit, which can reduce the latency theoretically. The QCADesigner has been used to confirm the designed structures. The suggested RCA uses 1246 cells, resulting in an area of 2.5 μm 2 , and latency of 3.25 clock cycles [35].
Moreover, Balali et al. [36] have proposed a three-input XOR gate structure based on cell interaction and half distance that designs high-speed and low complexity QCA-based one-bit full adder. Then a new 4-bit QCA-based RCA is suggested using the designed three-input XOR gate. The results have indicated the robustness and efficiency of the suggested designs. The proposed RCA in one layer uses 269 cells in 0.37 μm 2 and 3.5 cycles latency.
A robust QCA-based full adder based on a useful fiveinput majority gate has been proposed by Hashemi and Navi [37]. It has benefited from a robust crossover scheme compared with similar designs. In addition, it is considered to be strong in complexity, delay, and area. Because of this component's effective design, it is used to design RCAs at diverse scales. The suggested design simulation was performed using both engines of the QCADesigner. The obtained results have indicated the robustness and efficiency of the offered designs. The proposed RCA uses 442 cells in 1 μm 2 and a latency of 2 clock cycles.
Finally, Senthilnathan and Kumaravel [38] have proposed the QCA-based RCA design based on power and structural investigation. The energy consumption has been observed for different kink energy by adding average leakage and switching energy dissipation that was estimated using the QCAPro. In addition, the functional outputs are verified using the QCADesigner tool. The entire design for the new proposed RCA in QCA technology occupies a 0.95 μm 2 area with 745 QCA cells. A single bit adder has 124 cells with a 0.10 μm 2 area. These results help optimize performance and reduce area and power, especially for designing high-speed digital systems.

| PROPOSED DESIGN
This section presents an efficient and new architecture for a 4bit QCA-based RCA using a 1-bit QCA-based full adder as a basic module. A used 1-bit full adder has been developed by Seyed-Sajad Ahmadpour [39]. Figure 1 displays the used 1-bit QCA full adder block diagram, and Figure 2 illustrates the QCA-based layout of the full adder with a three-input XOR and three-input majority gates [40]. The main block in this design is a three-input XOR gate. It is simulated based on the cellular interaction using 10 cells in two clock phases [9,41,42]. The designed full adder by three-input XOR gate has 20 cells in a single layer and uses 0.75 clock cycles to produce outputs [9,42] with a 0.016 μm 2 area. It uses conventional QCA-based cells in one layer. A, B, and Cin denote input cells, while Cout and SUM are output cells.
As stated earlier, full adder and RCA circuits are fundamental units in digital arithmetic and logic circuits. The RCA layout is simple, allowing fast design time; however, it is relatively slow because each full adder has to wait for the calculated carry bit from the previous one. We can reduce the delay in RCAs by decreasing the delay of full adders. Figure 3 shows the structure of the proposed QCA-based 4-bit RCA architecture. Moreover, Figure 4 indicates the proposed 4-bit QCA-based RCA in which the four full adders are used as its structured unit. In addition, we used a coplanar crossing to design a new RCA circuit. The coplanar crossing is one of the most exciting features of QCA because it allows for monolayered circuits. Coplanar crossing allows the physical intersection of QCA wires [43]. This circuit is designed in a single layer, and all inputs and outputs are located in one layer. This layer has nine inputs (A0-A3, B0-B3, Cin) and five outputs (S0-S3, Cout). In this scheme, the outputs are not surrounded by other cells; therefore, they can be read simply. In other words, this design does not require a wire to transmit the output signal. Thus, the outputs can be fed to the input of another QCA-based circuit easily.

| SIMULATION RESULTS
This section specifies initial simulation tools and parameters. Then, the simulation results are described.

| Simulation tool
The QCADesigner, version 2.0.3, is used for placement, testing, and simulation of the 4-bit QCA-based RCA circuit. The 'coherence vector' and 'bistable approximation' engines are supported by this tool. Here, both engines are utilized, and afterwards, they have attained identical outcomes [44].

| Simulation parameters
Simulation parameters are set as their default values in QCA-Designer tool. Each QCA cell size is 18 x 18 nm with 5 nm diameter dots. Table 1 shows the QCADesigner parameters required for simulation of the QCA-based circuits.

| Accuracy analysis
The simulation outcomes of the 4-bit QCA-based RCA circuit are illustrated in Figure 5. We tested all possible samples but only reported some of them due to the large number of entries. The simulation results for testing the samples of A0, A1, A2, A3, B0, B1, B2, B3, and Cin based on Table 2 are shown in Figure 5. The output of S0 by applying inputs A0, B0, and Cin after 0.5 clock cycles is marked with the black rectangle in Figure 5. Moreover, the S1 output based on A1 and B1 inputs is produced after 1.5 clock cycles and is indicated with an orange rectangle in Figure 5. S2 output by employing inputs A2 and B2 is produced after 2.5 clock cycles and is illustrated by a yellow rectangle in Figure 5. Eventually, the output of S3 using inputs A3 and B3 after 3.5 clock cycles and Cout by providing inputs A3 and B3 after 3.75 clock cycles are produced and marked with a black rectangle in Figure 5. The results have confirmed that the suggested QCA-based 4-bit RCA runs completely and provides suitable proficiency. Figure 5 specifies the robust polarization of the output cell for QCA-based 4-bit F I G U R E 1 Logical diagram of quantum-dot cellular automata-based full adder in [39] F I G U R E 2 Layout of designed full adder by Seyed-Sajad Ahmadpour [39] F I G U R E 3 Schematic for 4-bit ripple carry adder F I G U R E 4 Layout of quantum-dot cellular automata-based 4-bit coplanar ripple carry adder SEYEDI ET AL.

| Comparisons and cost functions
The measurement outcomes are described in Table 3. The proposed design is better in terms of complexity, power consumption, and cell count than the previously obtained results. The design possesses approximately 49.14% betterment in cell number and 14.29% advantage in the area during adjustment to the best-presented QCA-based 4-bit RCA designs.
Furthermore, to measure the complexity of the designs, we employed the QCA cost function, which is expressed as follows [47]: In this function, M is the number of majority gates, I is the number of inverters, C is the number of crossovers, and T is the circuit delay [47]. In addition, k, l, p are the weights for the majority gate, crossover, and delay, respectively. In the evaluation, some values are considered for k, l, p to show the effect on cost from their possible combinations. Table 4 compares RCA design costs.

| CONCLUSION AND FUTURE RESEARCH DIRECTIONS
QCA is a growing and new technology that has an essential place in nanotechnology and has been studied for several years. Because of the benefits of QCA, namely, high switching speed, low power consumption, and increased device density, it could be an appropriate alternative for CMOSbased circuits. It is also possible to create a logical circuit based on multiple full adders to add n-bit numbers. In RCA, Cin is connected to the Cout of the previous adder. Because of the RCA's importance in logical circuits, a new coplanar design of a 4-bit RCA to decrease the complexity, energy consumption, number of cells, and area has been proposed in this article. We used both simulation engines of QCADesigner software version 2.0.3 to simulate the recommended designs. The simulation results using these simulator engines show that the new 4-bit RCA design has an approximately 49.14% advantage in cell number and 14.29% advantage in area over the investigated 4-bit RCA. In addition, the proposed RCA layout contains notably more latency and layer ability than that of previous layouts. The effective structures offered can be used in the future to design n-bit RCA and high-performance QCA circuits at nanoscale. Consequently, the proposed idea can be a fundamental element in the design of high-speed circuits and other types of adders such as full subtractor and ripple borrow subtractor. In addition, some techniques such as coplanar crossing, multilayer crossing, and logical crossing can be used to connect the outputs or inputs of the proposed designs to other QCA-based circuits.