Reliable SRAM using NAND ‐ NOR Gate in beyond ‐ CMOS QCA technology

The rise in complementary metal ‐ oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond ‐ CMOS technologies to stay in race with Moore’s law. Quantum ‐ dot cellular automata (QCA) is considered to be a prominent paradigm among the emerging beyond ‐ CMOS technologies. Since QCA is an emerging technology with no proper layout tools, layout generation from hardware description language (HDL) can be done by implementing circuits using the NAND ‐ NOR logic. In QCA, the NAND ‐ NOR logic is realised by combining a majority gate and an inverter or by using some dedicated structures. The Radius of Effect (RoE) is a critical factor that depends on the permittivity of the material used and it has an influence on the columbic interaction, polarisation and kink energy. Lower Radius of Effect values will have an impact on the performance of the circuit. In this work, a cost ‐ efficient NAND ‐ NOR gate using Single Rotated Cell (SRC) inverter is proposed which can operate with lower Radius of Effect. Using the proposed gate, multiplexer, decoder, and innovative memory cell are implemented. In order to demonstrate the ability to implement larger circuits using NAND ‐ NOR logic and the proposed blocks, a is implemented. QCADesigner is used for the simulation and vali-dation of the proposed designs.


| INTRODUCTION
Scaling of transistors has helped to increase the packaging densities of the devices. However, the scaling is limited by various factors such as physical dimensions, material and thermal effects. This has motivated the researchers to find alternatives beyond-complementary metal-oxide semiconductor (CMOS) . Among the emerging alternatives, quantum-dot cellular automata (QCA) is a transistor-less design paradigm that employs cells with electrons to implement logic functions. Its operation using the columbic repulsion between electrons has ignited the interest and hope to build circuits with low power, smaller area and extremely faster operation due to repulsion based information transfer [1,2]. The idea of QCA has attracted enormous interest from researchers which has resulted in a diverse range of QCA circuits using AND, NOT and OR logic. In general, the digital circuits are implemented using NAND-NOR logic in CMOS circuits. In CMOS, layouts are easily generated from hardware description language (HDL) by realising the circuits using universal logic gates. In QCA, circuits are implemented using AND-OR logic. The QCA layout generation tools are in their infancy stage and are complicated [3,4]. Therefore, in order to reduce its complexity, NAND-NOR logic-based layout generation can be deployed in QCA. However, in QCA, very few realisations are available in the literature to perform NAND-NOR operation. The operation of QCA circuits depends upon the columbic repulsion between the neighbouring cells. The range up to which a cell can interact depends upon its radius of effect (RoE) value [5,6]. The variations in parameters of the material such as temperature, porosity and grain size can affect the RoE value. Higher RoE values will not affect the performance of the circuit. But smaller RoE values will degrade the performance of the circuit. Hence, the circuits must be efficient to operate even with smaller RoE.

| Our contribution
The major contributions of this work are as follows.
i. A reliable NAND-NOR Gate (NNG) which can function at smaller RoE values is designed using a single rotated cell (SRC) inverter. ii. A Novel cost function is proposed to calculate the effectiveness of QCA gates. iii. In order to validate the NNG, logical blocks such as decoder, multiplexer, and memory cell are implemented using NAND-NOR logic. iv. The proposed designs are combined together to implement an SRAM. Implementation and verification are done using QCADesigner [7].
The remainder of the paper is organized as follows. Section 2 gives a short overview of QCA elements. Section 3 provides the working of SRC inverter. Section 4 discusses about the proposed NNG. Section 5 analyses the proposed gate on different metrics and proposes a new cost function for QCA gates. Section 6 presents the proposed blocks and SRAM implementation. Section 7 compares the proposed designs with other designs and finally the article ends with conclusion.

| QCA cell
Each QCA cell consists of two electrons that can tunnel only between the four quantum dots present in it. The electrons occupy the quantum dots in one of the two possible diagonal positions due to repulsion. Based on the dots orientation, the cells are categorised as normal and rotated cells. A rotated cell will have the quantum dots at 45°orientation difference compared to a normal cell. Based upon the diagonal occupation, the cells are encoded as logic '0' and logic '1'. The encoding of normal cells, and rotated cells with binary logic are presented in Figure 1(a) and (b), respectively.

| QCA wire
A QCA wire is constructed by organised placement of cells in an array. A cell in a normal wire will have identical polarisation as its neighbouring cell on both sides, whereas, a rotated cell in a rotated wire will have non-identical polarisation of its neighbouring cells on both ends. A normal QCA wire transmission is presented in Figure 2(a). A rotated wire transmission is presented in Figure 2(b).

| Radius of effect
RoE is the radius of the circular region with its centre at the centre of the cell. Depending on RoE, the influence of the cell will vary as presented in Figure 3. If the RoE value is small, the cell will have an impact on cells which are very close to it.

| Kink energy
Kink energy (E k i;j ) describes the columbic interaction between the cells and it drops inversely with the fifth power of cell to cell distance [8]. The electrostatic interaction (E k i;j ) between the dots in the cells i and j is given by (1).
where, ε 0 and ε r represent the permittivity of free space and the material system, respectively. |r i − r j | represents the distance between the dots in cell i and j. It is summed over all i and j. E k i;j is calculated by finding the electrostatic energy difference between the cells when they have non-identical polarisation and identical polarisation. The electrostatic energy depends largely on the value of |r i − r j |. Hence, the kink energy will drop as the distance increases between the cells and it depends largely on RoE.

| Majority gate
A majority gate consists of odd number of input cells and one output cell. A three-input majority gate is presented in Figure 4 (a). The logic of the output cell is determined by the majority of the logic among the three inputs. The majority gate can be realised as an AND, and OR gate, as presented in Figure 4(b) and (c), respectively.

| Inverter
Placing two normal cells diagonally will make the cells to align with opposite logic in a simple inverter as presented in Figure 5(a). A double path inverter is obtained by combing two simple inverters as presented in Figure 5(b). The applied input is transferred to two wires and brought back together at a cell that is placed at a diagonal position at the other end of the two wires. In general, a simple inverter is used with extra cells as presented in Figure 5(c) to improve output polarisation.

| QCA clocking
In QCA, the cells are connected to four clock zones. Each clock zone is provided with a separate clock signal by using four clock signals (clock 0, 1, 2, 3) which have a phase difference of ninety degrees with its successive zone clocks. Each clock zone cell passes through four states of operation during information transmission, namely relax, switch, hold and release [8]. No two zones will be in an identical state, at any point of time. In the schematic representation of the QCA circuits in QCADesigner, the clock zones are represented as shown in Figure 6.

| QCA crossover
The crossovers are techniques used to cross two wires. They are implemented by multilayer approach, rotated cell coplanar approach, multiphase clocking scheme, ternary cell approach, logical crossing and clock zone based coplanar approach. In the proposed designs, clock zone based crossover is employed as it is robust among all other types. In this approach, the phase difference between the two crossing wires is 180 degrees. The even numbered clock zones can cross each other and similarly, odd numbered clock zones can cross each other [9,10].

| SRC INVERTER
In general, simple inverter is preferred over double path inverter for its robustness and fewer cell count. However, in the double path inverter, the output will not be offset from the incoming wire [3] but it occupies more area compared to simple inverter. Here, an SRC with displacement is used as an inverter. Inversion is achieved by the columbic repulsion between the electrons present in the rotated cell in the middle and normal cells on either side of the rotated cell. The rotated cell is placed with a slight displacement either upwards or downwards. The rotated cell must be placed with its left and right side quantum dots aligned in the same line as that of the top or bottom row quantum dots of its neighbouring normal cells as presented in Figure 7. Table 1 compares the SRC inverter with other conventional inverters.
Coherence vector simulation is used for the calculation of output polarisation. Each cell is considered to be a two state system. The coherence vector (λ) is a vector representation of the density matrix (ρ) of the cell, projected onto the basis spanned by the identity and Pauli spin matrices σ x , σ y and σ z [11]. The z component of the coherence vector represents the cell polarisation (P i ). It is calculated by multiplying σ z with the trace of the density matrix as given by (2). The steady state coherence vector ( λ ! ss ) is given by (3).
where, the energy environment of the cell is represented by Γ ! and the temperature ratio is represented by Δ.
where, j represents the cells under the RoE region. From (2), it is clear that P i depends on the coherence vector and from ( (3)) and (4), it is clear that the steady state coherence vector depends upon the kink energy, RoE and polarisation of the adjacent cells (P j ). Since Kink energy depends upon the location of cells, it is clear that polarisation is depending mainly on two factors, namely, RoE and cell location.
The SRC inverter has the advantage of both the simple and double path inverter. It has fewer cells and smaller area similar to simple inverter and the output will not be offset from the incoming wire similar to double path inverter. The simple and double path inverters have their output cell in diagonal position with respect to the preceding cell.
Hence, they have low output polarisation. To achieve higher output polarisation, additional cells must be added to increase the out polarisation as presented in Figure 5 (c). In SRC inverter, the output cell is placed almost in the same line as the preceding cell. Hence, they have higher output polarisation and do not require any additional cells to be placed after the output cell to increase the polarisation. From Table 1, it is clear that the SRC inverter has the least area among all the designs.

| PROPOSED NAND/NOR GATE
The conventional NAND-NOR gate is designed by using a AND-OR gate (majority gate) along with any of the inverter design. Only few dedicated architectures for NAND-NOR gate have been proposed already in the literature [12][13][14][15]. In [12], an NAND-NOR-Inverter (NNI) gate is proposed which functions similar to a majority gate. NAND-NOR operation is realised by applying inverted inputs to the majority gate. It is realised by using two inverters along with a displaced cell. In [13], NAND-NOR function is realised by using a multi-function FNZ gate. The design in [13] has three cells to be placed with a displacement. In [14], NAND-NOR function is realised by using a gate implemented using multilayer approach. In general, designs implemented using multilayer approach have smaller area but they are complex compared to coplanar designs. The design in [15] has fewer cells, but interfacing it with other cells is difficult since the NAND-NOR selection cell is implemented by using a rotated cell. Hence, the interfacing wires need to be displaced to connect with the NAND-NOR cell and it increases the complexity of the implementation. In the existing coplanar approaches [12,13]  implementing NAND-NOR function, either the number of inverters or the displaced cells will be more. Hence, they have a higher probability to become faulty during fabrication [4]. In order to reduce the number of displaced cells and complexity of NAND-NOR gates, a NNG is proposed using the SRC inverter. The proposed NNG works similar to the conventional majority gate. Instead of using conventional inverters discussed in Section 2, the NNG used in this study utilises the SRC inverter as shown in Figure 8(a). It will function as NAND and NOR gate by setting the NAND-NOR cell to logic '0' and '1', respectively. The schematic representation of the NNG and the results of its simulation are presented in Figure 8(b) and (c), respectively.

| RoE reliability analysis
As discussed in Section 3, the output polarisation of QCA circuits depends on RoE and location of cells. The RoE value depends upon the permittivity of the material. Circuits with smaller RoE values may malfunction, even if there is a minor displacement defect. Permittivity of the material depends upon various parameters such as, temperature, grain size, porosity, thickness and thermal treatment, and changes in these values will affect the RoE. As discussed under Section 2, increase in RoE will not affect the circuit performance to a great extent. But reduction in RoE value will affect the reliability and performance of the circuit. Hence, the circuits must be reliable even when the RoE value becomes smaller due to any parameter variations. Table 2 compares the proposed structure with the existing designs based upon the smallest RoE up to which the gates produce fault-free outputs. The RoE analysis is done for the proposed and existing designs, by considering QCA cells with height and width of 18 nm and dot diameter of 5 nm.
The proposed design provides output without any error, and its output is reliable with RoE up to 21 nm. In [12], a gate is designed with one cell lesser than the proposed design. However, the proposed design occupies the same area and it operates with almost half of its least permissible RoE value. This is achieved because of the close placement of cells compared to the design in [12]. The design in [13] operates with a very low RoE. However, it requires three cells to be placed accurately with a small displacement, but the proposed design requires only one cell with displacement. In [14], a multilayer approach is used to get a reduced area. But, multilayer designs are more complex to implement compared to coplanar designs [10]. The proposed design operates with the least RoE value compared to all other designs.

| Displacement tolerance analysis
In the NNG structure, the SRC displacement plays a major role in achieving the inversion. The location of SRC determines the output polarisation. Hence, care must be taken to place the cell at the exact location. Placing cells accurately at nm levels in exact locations is extremely difficult [6]. Cell displacement will affect the polarisation and the cell can be displaced only within a small range of location without affecting the desired output. A detailed analysis is made with the proposed design and the displacement tolerance (d ) of the SRC is calculated for different RoE values as shown in Table 3. The table also shows the maximum output polarisation value (P o ) for different RoE and the displacement tolerance range of SRC, when the output polarisation value is larger than 0.9.
From Table 3, it is evident that the proposed structure functions with output polarisation larger than 0.9, when SRC is displaced anywhere between 3.3 to 6.4 nm, even with an RoE value of 21 nm. Hence, the wide range of displacement tolerance will help to reduce the impact of misplacement defect, if any occurs during the fabrication.

| Cost analysis
Cost function for QCA circuits is proposed in [16]. The cost function in [16] is given as, where M is the majority gate count, I is the inverter count, C is the crossover count, T is the circuit delay, and k, l, p are the exponential weightings for the above terms, respectively.
In [16], a constant weighting of 1 is assigned to the number of inverters. But for analysing NAND-NOR gate, the number of inverters and displaced cells have greater importance compared to crossovers and majority gate. Hence, (5) is modified as, where, D and R represent the number of displaced cells and rotated cells, respectively. n, m and q are the weightings for number of inverters, number of displaced cells, and number of rotated cells, respectively. The parameters k, l, p are given weightings of 1. n, m and q are given a weighting of 2 to prioritise the impact of inverters, displaced cells and rotated cells. using (6). From Table 4, it is clear that the proposed design is cost-efficient compared to the existing designs.

| SRAM USING NNG
To corroborate the proposed NNG, a 16*16 bit SRAM is implemented using the proposed NNG. To implement SRAM, multiplexer, decoder and memory cells are designed using the proposed NNG.
To design an n to 2 n multiplexer, a 2 to 1 multiplexer is proposed as presented in Figure 9. The proposed multiplexer is extended to implement a 16 to 1 multiplexer as presented in Figure 10 and the results of its simulation are presented in Figure 11. Similarly, a 2 to 4 decoder is implemented as presented in Figure 12. The proposed decoder is extended and a 4 to 16 decoder is implemented as presented in Figure 13 and the results of its simulation are presented in Figure 14. In order to implement a memory cell with better data integrity and also for its implementation with row and column decoder, an innovative architecture is proposed using multiplexers as presented in Figure 15 and realised in Figure 16. Table 5 presents the proposed memory cell operation. The proposed design is implemented by including the row and column enable signals to the architecture in [18]. In addition to that, the proposed architecture is designed for implementation using NAND-NOR logic. The proposed memory cell will be enabled only if the row (Row_En) and column enable (Col_En) signals are enabled. Even if any one of the row or column enable signals is disabled, no read or write operation can be performed in the memory cell. If the row and column signals are enabled, then the last stored data in the memory cell can be read. The proposed memory cell with enabled row and column can be used to realise higher order memory cell array. Figure 17 presents how the memory cells are connected to implement a 1*4 array. Using the proposed blocks, a 16*16 SRAM is implemented using both row and column decoder as presented in Figure 18. The SRAM has around 140,000 cells with an area of 195 µm 2 (17156 nm x 11360 nm) and a delay of 60 clock cycles.

| PERFORMANCE COMPARISON
The proposed designs are compared in Table 6. Several multiplexer and decoder designs are available in the literature. However, efficient higher order designs are implemented only in [18]. The proposed designs are efficient even after implementing using NAND-NOR logic and perform better compared to [18].
The memory cell designs in [17] have better data integrity compared to other existing designs in the literature. The proposed design has the same data integrity compared to [17]. Compared to [17], the proposed design has the row and column enable lines to make the memory cell suitable for higher order memory cell implementation without adding any additional cells. The design in [17] has fewer cells, area and delay due to the efficient multiplexer used in it [19]. The proposed memory cell has additional circuitry (row and column enable) and it is implemented further by using the NAND-NOR logic compared to [17]. Hence, the proposed design has increased cell count, area and delay compared to [17]. However, the design in [17] requires extra cells for interfacing, whereas the proposed memory cell requires no extra interfacing cells and it can be placed as a block as shown in Figure 17. In addition to that, the multiplexer in [19] can operate with RoE only up to 22 nm but the proposed NNG can operate up to 21 nm. The proposed SRAM is more reliable due to its implementation using reliable NNG. F I G U R E 1 4 Proposed 4 to 16 decoder simulation results QCA circuit layout generation from HDL can be expedited by implementing circuits using NAND-NOR logic. Here, an innovative reliable NNG is proposed which can operate with lower RoE values up to 21 nm. Furthermore, a unique cost function for gates is proposed to validate QCA gates. The reliability of the proposed gate is evaluated using different analyses. Furthermore, to validate the NNG, logical blocks are implemented by NAND-NOR logic. The proposed blocks are extended to implement a 16*16 SRAM. The proposed designs are more reliable to RoE variations due to their implementation using the proposed gate.
The proposed NAND-NOR gate can be effectively used in a layout generation of any efficient QCA circuit from HDL similar to the CMOS layout generation. Integrating a majority logic circuit generator, HDL net list and the proposed gate will help to make a leap in QCA layout generation.