Five-level class-D ampliﬁer employing fourth-order continuous-time sigma-delta modulator

A new closed-loop multi-level Class-D ampliﬁer employing a fourth- order ‘continuous-time sigma-delta modulator’ is proposed and analysed. The proposed ampliﬁer is intrinsically linear and it has ap- proximately the ﬁxed ‘total harmonic distortion plus noise’ against the input frequency. The corresponding circuit is designed and simulated in 180 nm technology (3.3 V), while the post-layout model of the power stage is employed. A total harmonic distortion plus noise of 0.0016%, the quiescent current of 2.6 mA, the maximum efﬁciency of 94%, the average switching frequency of 400 ∼ 500 kHz and an excellent ‘power supply reject ration’ of 120 dB are achieved.


Introduction:
The closed-loop Class-D amplifiers including 'pulse width modulation (PWM)' suffer from inherent non-linearity [1][2][3][4][5], such that unlike linear amplifiers, the higher loop-order cannot reduce the distortion levels [5]. The high-frequency ripples of the switching signal are resampled in the PWM section which makes PWM-residual-aliasing distortion [1,5]. To cancel this error, several solutions including an additive pulse-train in feedback path [1], the combination of 'sigma-delta (SD)' and PWM techniques with a 17-level voltage quantiser and digital time-quantised PWM [2], and a low-pass filter in feedback path [3] are introduced. All these techniques add a challenging calibration circuit [1][2][3] to alleviate the inherent linearity problem of three-level closedloop PWM. Besides, a challenging design of loop-filter is needed to achieve a Power Supply Reject Ratio (PSRR) of better than 100 [3]. The 'phase-shifted carrier-modulated' multi-level Class-D amplifiers offer a calibration-free circuit [4]. However, in these amplifiers, like the threelevel ones, the triangular wave generators and fast static comparators are required, and the total harmonic distortion plus noise (THD + N) increases by the second power of the input frequency.
This paper replaces the PWM-based loop by continuous-time SD modulator (CT-SDM) to guarantee an inherent linear operation, while a five-level (four-leg) power stage is employed to improve the dynamic range in a moderate switching frequency. The proposed combination, for Class-D amplifiers, obeys the classical linear amplifiers design-theory in which the higher loop-gain leads to the lower distortion. Hence, unlike all three-level conventional second-order PWM-based amplifiers, a fourth-order loop-filter is employed here, which suppresses extrinsic non-linearity and improves the PSRR. The static comparators and the triangular wave are replaced by the dynamic comparators and the square wave, respectively.
System-level analysis and design: Figure 1 shows the system-level schematic of the proposed multi-level Class-D amplifier. A CT-SDM is employed in this design, while R-C variations of the fabrication process, can be addressed by sampling frequency adjustment. The error signal of is processed in the loop-filter and then it is sampled and quantised by an (N + 1)-level quantiser at f s . N digital outputs of the quantiser excite N power switches and prepare (N + 1)-level output power signal, v o (t). The output signal is fed back to the loop-filter through an optional attenuator. For a busy (i.e. rapidly and randomly varying) input signal, the two-sided power spectral density of the quantisation noise of an (N + 1)-level quantiser is e 2 q = (V FS /N ) 2 /(12 f s ) [5], where V FS is the full-scale voltage of the quantizer. A high-order multilevel SDM eliminates the correlation between the quantisation error and the input signal [5], such that a linear analysis of the Class-D amplifier with the additive white noise of the quantiser is permitted [5]. As shown in Figure 1, the inner feedback path (gain of k * ) compensates the excess loop delay caused by limited gain-bandwidth of amplifiers, the delay of both quantiser and the power stage. For the sake of simplicity, the effects of delays and compensation path are ignored. The 'noise transfer function (NTF)' of Figure 1 is equal to Corresponding to Figure 1, k 1 = a 3 1 . The local feedback of the first two integrators (through the gain of ξ ) provides a resonator. According to (1), two zeros of NTF are migrated from origin into the band of interest.
The in-band quantisation noise of the modulator can be achieved by multiplying e 2 q and (1), and then integrating over the frequency range of [−BW BW], where, BW is the bandwidth. As f s > > 2BW, the NTF has a low-frequency approximation of NTF In this way, the in-band quantisation noise of Lth-order modulator is equal to where OSR is the oversampling ratio equal to f s /(2BW). The resonator (gain of ξ ) decreases the IBN q by (L − 0.5) 2 for L > 2. k 1 is equal to [5], where λ is the modulation index (|λ| < 1), α ELD is a constant term depending on L, N and the excess loop delay (related to T s ). α ELD = 1.15 for L = 4 and N = 4, which leads to k 1 = 0.044, for λ = 0.8.
The errors of power stage (unbalance rising and falling times, the error of dead time and the clock jitter error) are added in the forward path, where any error is shaped by NTF. The main part of permitted noise power is devoted to thermal noise and only 10∼15% of the noise floor can be occupied by quantisation noise. This means that, for a 16bit Class-D amplifier, the in-band quantisation noise must be less than −108 dBFS∼−106 dBFS (dB related to full scale).
Three system-level parameters of N, OSR and L can be designed to achieve the targeted quantisation noise. The parameter N determines the number of inductors, half-bridges and drivers. Considering practical implementations of Class-D amplifiers [4] a five-level output (N = 4) is assumed in future analysis and design. The switching frequency and so the dynamic power consumption of the power stage is proportional to OSR (f s /2BW) which should be limited. As shown in (2), the higher order of the SDM (L), leads to less in-band quantisation. On the other hand, while the number of quantisation levels is limited (N = 4), the stability considerations force less aggressive noise shaping (lower L) or lower k 1 .
Considering relation (2), using the Schreier toolbox [5], and performing vast system-level simulations, a fourth-order SDM, L = 4, a maximum modulation index of λ = 0.8 (k 1 = 0.044), an OSR of 40 (f s = 1.6 MHz) are selected for an IBN q = −107 dB and V FS = 3.3 V. The coefficients k 2 , k 3 and k 4 are designed for stability consideration by the Schreier toolbox. The system-level parameters are reported in Table 1.

Model parameter
Circuit-level equivalent Circuit-level implementation: Figure 2 illustrates the circuit-level implementation of the proposed amplifier and Table 2 translates the systemlevel parameters of Figure 1 to the circuit-level parameters of Figure 2. The first integrator of Figure 2 is the main source of the amplifier's noise. The overall in-band thermal noise of the whole amplifier is given by where K = 1.36 × 10 −23 is Boltzmann's constant, T is the environment temperature in Kelvin and R 1 is the input resistor of the first integrator. The coefficient 4 accounts for four resistors in the signal and feedback paths of Figure 2. The coefficient 1.05 models the noise of 'operational transconductance amplifier (OTA)' as 5% of the noise of 4R 1 . The coefficient 1.1 models the thermal noise of the subsequent integrators as 10% of the first integrator. As noted before IBN th = 0.85NF. For the 16-bit resolution, the amplifier's noise floor is NF = λ 2 V 2 FS /(12 × 2 2×B ) = 1.35 × 10 −10 and using (3), R 1 is equal to For λ = 0.8 and B = 16, (4) gives R 1 ≈ 68 kΩ. Five per cent of the noise floor is devoted to the clock jitter noise and the power-stage errors. Considering Tables 1 and 2, R 1 gives the other circuit-level parameters ( Table 3).
The output low-pass filter of Figure 2 is designed for 4Ω single-ended (8Ω differential) load with −1 dB bandwidth of 20 kHz and −30 dB cut-off frequency of 200 kHz. The feedforward paths of Figure 1 (k 2 , k 3 and k 4 ) are realised in Figure 2 by injecting the output signal of first, second and third integrators to the fourth integrator through C F1 , C F2 and C F3 , respectively. The capacitive-coupling eliminates the last adder of Figure 1. To implement the local feedback path, ξ , of Figure 1, the resistive feedback is required. Due to the very small value of ξ (e.g. 0.0048), the feedback resistor would be in megaohms. In Figure 2, the capacitive local feedback, including C B1 and three first integrators, offers C B1 = 667 fF.
The power stage contains four half-bridges. Two upper half-bridge and two lower ones supply the negative and the positive sides of the  [6] load, respectively. Each half-bridge carries half current of the power stage. The outputs of two upper/lower comparators are digitally multiplexed between two upper/lower half-bridges every M sampling period (e.g. M = 8), to avoid any potential current circulation between inductors.
The output signal of ith half-bridge, v oi , is fed backed through a resistor to the first integrator. While one side is active, the other side is OFF and generates a zero-output voltage. Therefore, the feedback signal injects unbalance common-mode voltage to the differential inputs of both first and last integrators. To alleviate this problem, all half-bridges outputs are inverted and fed backed to input ports of the first and last integrators. The combination of these four signals does not include the input-signal content and just balance the common-mode voltage of differential inputs. Furthermore, this technique enhances the PSRR of the whole amplifier. According to Figure 2, all the feedback paths of the first integrator are added passively and then injected into the first integrator through R B1 , while R B2 = 2R 1 /10, R B3 = 4R 1 /10 and R B1 = 4.5R 1 /10. Also, the output signals of half-bridges and their inverted versions are feed-backed through a capacitor set to the last integrator (k * of Figure 1).
Although one or two OTAs can implement the fourth-order loopfilter, using four OTAs, a more robust design against circuit nonidealities is formed. A 'chain of integrators with weighted feedforward summation (CIFF)' is used to reduce the voltage swing of three first OTAs [5]. In this way, the first three OTAs process only the quantisation noise.
The last-integrator benefits from the third-order shaping of three first integrators. The main-path gain, k 1 , is distributed among three first integrators, k 1 = a 3 1 , to reduces the capacitive load of the first OTA. The voltage swings of the three first integrators are designed for moderate values satisfied by a one-stage folded-cascode OTA of Figure 3(a). According to Table 3 and Figure 2, the three first OTAs have capacitor loads, C L , of C I1 + C F3 = 29.67 pF, C I2 + C F2 = 10 pF and C I3 + C F1 + C B1 = 10.25 pF, respectively. The system-level simulations show that the first OTA requires a ω t = 2π × 8f s and three other OTAs need a ω t = 2π × 2f s . The first OTA is designed with a current budget of I 0 = 772 μA, while the second and third OTAs are linearly scaled. Considering Figure 3(a), for three first OTAs, the gainbandwidth is equal to ω t ≈ g mp1 /C L , where g mp1 is the transconductance of M p1 . Usually, the current budget of folded-cascode OTA, I 0 , is equally divided between its four legs [6]. The size of the input transistors is (W/L) p = g 2 mp1 /(2μ p C ox I 0 /4) = 2ω 2 t C 2 L /(μ p C ox I 0 ). The overdrive voltages, V od , of M n1-4 and M p3-6 are determined by the output voltage swing, and their size is (W/L) n/p = 2I 0 /(3μ n/p C ox V 2 od ). The last OTA requires 0.8 × V FS maximum voltage-swing implemented by two-stage Miller-compensated OTA (Figure 3(b)). This OTA is designed with a current budget of I 1 = 93 μA for a 1.04 pF load. For symmetric slew rate, C C is selected equal to C L and the current budget of OTA is shared corresponding to Figure 3(b) [6]. The gainbandwidth is ω t = g mp1 /C C and the dimension of the input transistors is (W/L) p = g 2 mp1 /(2μ p C ox I 0 /6) = 3ω 2 t C 2 L /(μ p C ox I 0 ). The dimension of M n1,2 is μ n /μ p times smaller than M p1,2 . For a given voltage swing, the V od of the second stage is determined and the sizes of M n3,4 and M p3,4 is (W/L) n/p = 2I 0 /(3μ n/p C ox V 2 od ). Four dynamic comparators quantise the output signal of the loopfilter, V out4 . According to Figure 2, the dynamic comparators are excited by a square-wave sampling clock at the frequency of f CLK = 1.6 MHz. According to Figure 4(a), the dynamic comparator includes a preamplifier, a latch and an Set-Reset (SR)-latch. The SR-latch is designed for the minimum dimensions. The latch time is [5], where C P is the parasitic capacitor, g mp4 and g mp5 are the transconductance of M p4 and M p5 , and V o ((k + 1/2)T s ) and V o ((k + 1)T s ) are the initial and final voltages of latch in the kth sampling period. The final voltage of latch is V FS and the minimum input voltage of comparators, in five-level quantiser, is (V FS /4)/2, amplified by the preamplifier gain of g mp1 /g mn1 . Considering the reset time of T s /2, C P /(g mp4 + g mn5 ) × ln(8g mn1 /g mp1 ) < T s /2 is achieved for the latch time. The dimensions of M n5, 6 and M p4,5 are a trade-off between the maximum values of g mp4 + g mn5 and minimum value of C P , achieved by simulation. M n1-4 need a large L, and a minimum W, while M p1,2 should have minimum L and a reasonable W. Both PMOS and NMOS transistors of each half-bridge, respectively, have a channel width of 28 and 7.2 mm and a channel length of 300 and 350 nm, resulting in an ON-resistance of 180 mΩ.
There are two half-bridge on each side of the load and the whole power stage has an area of 0.287 mm 2 . The power driver of each halfbridge excites the NMOS and the PMOS transistors individually by a chain of inverters, tapered by a one-third coefficient (Figure 4(b)). Compared to the NMOS transistor, the PMOS transistor has larger dimensions driven by a larger inverter. According to Figure 4(b), to prevent shoot-through current in the half-bridges, a bi-stable circuit generates the dead time between the operation of the PMOS and the NMOS transistors.
Simulation results and discussion of results: The amplifier of Figure 2 is designed and simulated in 180 nm technology, while parameters of Table 3 and the schematics of Figures 3 and 4 are used. The high-voltage (3.3 V) NMOS and PMOS transistors are employed, respectively. To achieve more precise results, the post-layout model of the power stage is used. Figure 5 illustrates the THD + N (%) of the proposed Class-D amplifier versus the input power. A minimum THD + N of 0.0016% corresponding to 245.4 mW output power (λ = 0.6) and a THD + N of 0.0032% corresponding to the output power of 403.5 mW (λ = 0.77) are achieved, while no linearisation technique is employed. Figure 6(a) illustrates the THD + N (%) of the proposed amplifier versus the input frequency, f in , which shows an approximately constant value. In contrast, in conventional PWM amplifiers the THD growths by f in 2 [4]. The power supply rejection is tested by applying a 200 mV peak-topeak disturbance voltage on the supply and a −60 dBFS input signal. For different disturbance frequencies, 100 Hz∼17.97 kHz, the disturbance tone is under the noise floor, and PSRR is better than 120 dB.
The simulation results (with the post-layout model of the power stage) show a power efficiency of 94% at P out = 403.5 mW (λ = 0.77) and THD + N (%) = 0.0032%. As stated before, depending on the polarity of V out4 , two of four half-bridges are OFF. In the active section, on average only one of two half-bridges changes its previous state at the sampling moment. Figure 6(b) shows the average switching frequency versus the output power which is 400∼500 kHz, while f s = 1.6 MHz. Figure 7 illustrates the output 'power spectral density (PSD)' of the proposed amplifier for two input frequency of 1.5625 and 6.25 kHz, and P out = 245 mW (corresponding to minimum THD + N). For 1.5625 kHz input, before saturation of the last OTA, the PSD of the amplifier is distortion free, while for 6.25 kHz input the third harmonic is 104.4 dB lower than the main tone. Also, the amplifier has approximately the same THD + N for both frequencies. Table 4 compares the simulation results of this paper with the state-of-the-art results.

Conclusion:
A new version of multi-level Class-D amplifiers with a CT-SDM is proposed for BTLs as a suitable alternative for PWMbased closed-loop Class-D amplifiers. Unlike PWM-based amplifiers, the THD of the proposed amplifier is approximately fixed in the whole bandwidth of the amplifier. The proposed amplifier tends to linear amplifiers such that no linearisation technique is required. However, compared to conventional amplifiers, the proposed amplifier has a higher quantisation noise, reduced by higher loop-order and higher sampling frequency. Both higher order and higher sampling frequency propel the amplifier to the linear category more tightly. The switching frequency of this amplifier is one-fourth times of its sampling frequency comparable to the switching frequency of PWM-based amplifiers. The simulation results show a 2.6 mA quiescent current, 0.0016% minimum THD + N and efficiency of 94%, for an 8Ω BTL, while the post-layout model of power stage is used.

© 2021 The Authors. Electronics Letters published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. Received: 27 October 2020 Accepted: 17 November 2020 doi: 10.1049/ell2.12004