Bias stress instability in multilayered MoTe 2 ﬁeld effect transistors under DC and pulse-mode operation

Here, bias stress instability on multilayered MoTe 2 ﬁeld effect tran- sistors (m-MoTe 2 FETs) with encapsulation of hydrophobic polymers (cyclic transparent optical polymer) is systematically investigated under DC and pulse mode operation. During DC mode stress, the threshold voltage shift ( (cid:2) V th ) under positive bias stress is at least three times larger than that of negative stress due to high hole barrier ( ∼ 0.57 eV), compared with electron barrier ( ∼ 0.18 eV). However, (cid:2) V th in positive pulse mode stress is signiﬁcantly reduced with decrease of a duty cycle, as compared with that of negative stress. With isolation from external gas ambient effects such as H 2 O and O 2 , shallow electron traps in multilayered MoTe 2 ﬁeld effect transistors are identiﬁed as one of strong candidates to cause bias polarity dependency on (cid:2) V th in pulse mode. Moreover, recovery time for traps, involved during positive bias stress, is six times faster than that of negative stress, substantiating that shallow electron traps and their fast detrapping are one of key origins. In practice, optimisation of pulse mode operation via bipolar switching can be potentially utilised for minimisation of device instability during the operation of multilayered MoTe 2 ﬁeld effect transistors devices and their circuits.

✉ Email: shjin@inu.ac.kr Here, bias stress instability on multilayered MoTe 2 field effect transistors (m-MoTe 2 FETs) with encapsulation of hydrophobic polymers (cyclic transparent optical polymer) is systematically investigated under DC and pulse mode operation. During DC mode stress, the threshold voltage shift ( V th ) under positive bias stress is at least three times larger than that of negative stress due to high hole barrier (∼0.57 eV), compared with electron barrier (∼0.18 eV). However, V th in positive pulse mode stress is significantly reduced with decrease of a duty cycle, as compared with that of negative stress. With isolation from external gas ambient effects such as H 2 O and O 2 , shallow electron traps in multilayered MoTe 2 field effect transistors are identified as one of strong candidates to cause bias polarity dependency on V th in pulse mode. Moreover, recovery time for traps, involved during positive bias stress, is six times faster than that of negative stress, substantiating that shallow electron traps and their fast detrapping are one of key origins. In practice, optimisation of pulse mode operation via bipolar switching can be potentially utilised for minimisation of device instability during the operation of multilayered MoTe 2 field effect transistors devices and their circuits.
Introduction: In a recent past, transition metal dichalcogenides (TMDCs) have been actively employed towards next generation device research beyond Si technology owing to their thinness of twodimensional nature, number of layers dependent sizable bandgaps, novel optical/mechanical properties, and others [1][2][3][4]. Among a variety of TMDCs, multilayered molybdenum ditelluride (m-MoTe 2 ) has been attractively considered as one of versatile candidates because of their low energy bandgap (∼0.9 eV) properties, leading to preferable n (or p)type switching, which is mandatory for the reconfigurable device operation [5]. Moreover, among a variety of applications, future display backplanes [6] and internet of things (IoT) sensors based on MoTe 2 field effect transistors (FETs) could be one of the envisioned promising candidates due to easy tunability toward n(or p)-type FETs, excellent gas sensitivity associated with large volume-to-surface ratio, and insensitivity to photoresponse under light illumination [7][8][9]. In this sense, significant research activities have been investigated towards the improvement of electrical properties and their feasibility confirmation on newly proposed applications, such as sensors and memory devices, and others [10,11]. However, for realisation of the aforementioned application, aspects on device instability for m-MoTe 2 FETs during the electrical operation should be thoroughly investigated, but interestingly, such kind of research activities have been limitedly executed, as compared to one of the representative multilayered MoS 2 (m-MoS 2 ) FETs [12][13][14]. In particular, understanding of bias stress instability (BSI) behaviours under DC (or/and AC) mode operation and their comparison are highly demanding for the circuit level application because the better understanding on the origins of device instability in m-MoTe 2 FETs can secure the device reliability by either optimisation of material properties or development of novel operation scheme associated with duty cycle, amplitude, bias polarity, and others.
In this letter, we investigated BSI of m-MoTe 2 FETs after encapsulation with hydrophobic polymer (cyclic transparent optical polymer; CY-TOP), which has been reported to have the effectiveness to secure external gas effects in air [15,16]. Moreover, bias polarity, electric field, and FETs, albeit independently designed, pulse mode stresses in variation of frame time were also applied to identify origin of device instability under AC mode operation. Thereafter, the newly proposed suppression method was rationally validated, leading to elucidation on origin of device instability, and moreover, annihilation of device instability was practically addressed by adoption of practical compensation mode operation via bipolar switching scheme during gate bias operation.
Device fabrication and structure: Figure 1a illustrates a schematic cartoon for trapping process of charge carriers in MoTe 2 channel and their possible sources: (i) interface traps between MoTe 2 and SiO 2 , (ii) bulk traps in SiO 2 , and (iii) surface traps due to O 2 (or H 2 O). From these sources, surface traps were excluded by encapsulation of CYTOP. Figure 1b depicts device structure of fabricated m-MoTe 2 FETs with thermally grown gate oxide dielectric (∼20 nm), implemented on a heavily doped phosphorous Si substrates (ρ ∼ 0.005 ohm·cm) as a common back gate. For device fabrication, m-MoTe 2 was mechanically exfoliated from bulk MoTe 2 crystals (HQ graphene), and transferred onto SiO 2 substrates by using poly dimethylsiloxane (PDMS) elastomer, followed by furnace annealing in a mixed gas (∼Ar/H 2 ) ambient at 300°C for 1 h to retrieve clean surface of m-MoTe 2 via removal of organic contaminants, possibly contaminated during the transfer process [16]. By atomic force microscopy, thickness of MoTe 2 flake is measured as 10 nm, approximately corresponding to 15 layers. Thereafter, source/drain contact formation between selected flakes of m-MoTe 2 and Au was yielded via thermal evaporation of Au (∼30 nm) over photolithographically patterned region, and immediately lifted-off in acetone. In this work, all devices have the same physical dimension of W/L ( = 30/10) μm, respectively. After initial evaluation of I-V characteristics of m-MoTe 2 FETs, hydrophobic CYTOP was encapsulated to minimise external gas effects such as O 2 and H 2 O in air, leading to decoupling with origins of device instability either from external gases (e.g. O 2 , H 2 O) or internal device instability of m-MoTe 2 , respectively. In this study, all protocols for the fabrication and encapsulation of m-MoTe 2 were adopted from the same method in the previous reports [9,15].
Results and discussions: For evaluation of electrical performance of m-MoTe 2 FETs, transfer characteristics (I DS -V GS ) at V DS = − 0.1 V and output characteristics (I DS -V DS ) were measured. As shown in Figure 1c, transfer curves before (or after) CYTOP encapsulation show typically observed p-type behaviours. In addition, Figure 1d shows good saturation behaviours and Ohmic contact properties around a low drain bias regime which represents appropriate device operation. Detailed electrical properties of fabricated MoTe 2 FETs at V DS = −0.1 V are summarised in Table 1. For the evaluation of electrical parameters, V th was calculated as the value of x-axis intercept of linear extrapolation of the I DS -V GS curve at its maximum first derivative point [17] and μ eff was  , V hys was extracted as the difference in V th between forwardly swept and reversely swept transfer characteristics, and contact resistance (R c ) was extracted by using Y-function method [18,19]. Overall, with CYTOP encapsulation, decent electrical performance can be secured, which might be attributed to reduction of charge scattering associated with oxygen and OH − groups on the surface of MoTe 2 surface in air [12,16]. After evaluation of electrical properties, transfer characteristics and evolution of V th under various conditions of DC stress were measured to figure out V th behaviour depending on bias polarity (i.e. + or −), E-field strength (1-2 MV/cm), and effective stress time (1800 s). Figure 2a shows E-field strength effects on device instability from 1.0 to 2.0 MV/cm. As electric field strength was increased, V th increased accordingly. In addition, as shown in Figure 2b, the time dependence of V th for the positive bias stress (PBS) and negative bias stress (NBS) show excellent agreement with the stretched-exponential relationship, which is known to be involved in the charge trapping mechanism in various TFTs such a-Si [20] and a-IGZO TFTs [21]. The stretched-exponential equation of V th is defined as where V tho is the V th at infinite time, τ = τ 0 exp(E τ /kT) denotes the characteristic trapping time of carriers where the thermal activation energy is given by E a = E τ β. β is the stretched-exponential exponent and E τ is the average effective energy barrier that electrons in the MoTe 2 need to overcome before they can enter the insulator, and τ 0 is the thermal prefactor for emission over the barrier. The fact that V th is nicely fitted with Equation (1) can be attributed to the emission of trapped charges towards deep states in the bulk dielectric for longer stress time (t > τ). However, V th under positive stress is larger than negative stress in the same E-field strength range as shown in Figure 2b, implying that different electron and hole trapping behaviours are governed by bias polarity. To have a better understanding on bias polarity dependency, we have investigated device instability under pulse mode operation. Figure 3a shows an illustration to describe waveforms during DC and pulse mode operation. DC mode stress causes a continuous voltage stress, whereas pulse mode stress with an off period leads to a chance of detrapping for trapped charge carriers. With an independent DC and pulse stress, transfer characteristics and their V th shift were evaluated in Figure 3b,c. Under pulse mode stress with a duty cycle ranging from 0.1 to 0.7, V th was reduced, as compared to DC stress. Moreover, a duty cycle dependency on V th for both PBS and NBS is noticeably observed. Even though effective stress time is the same, lower duty cycle condition yields the larger off-period to detrap, leading to less V th . Interestingly, as compared to NBS, V th of PBS is dramatically suppressed under pulse stress with any duty cycle. For the elucidation on the behind mechanism to cause duty cycle dependency, a normalised threshold voltage shift (i.e. V th(duty cycles) / V th(DC) (%)) is illustrated in Figure 3d. Compared to the gradual decrease in V th under NBS depending on duty cycles, the normalised V th behaviour under PBS shows sharp reduction by 20% under 0.7P duty cycle.
For further confirmation on key parameter of pulse stress, we extracted V th depending on frame time of pulse corresponding from 1 MHz to 1 Hz in Figure 4a. With a fixed bias stress voltage (2 MV/cm) for 900 s, V th under PBS shows clear frame time (pulse frequency) dependency for all range from 1 MHz to 1 Hz. On the other hand, NBS reveals insensitive shift behaviour according to frame time, as compared to that of PBS. These results suggest that electron trapping under PBS has fast recovery characteristics during off-period of the pulse. To understand the differences in bias polarity and frame time dependency on PBS and NBS, energy-band diagram models are suggested in Figure 4b. Under PBS, electrons can be trapped to interface traps or bulk traps in SiO 2 . However, for the case of NBS, hole trapping towards bulk trap in SiO 2 is expected to be difficult, because barrier height between MoTe 2 valence band and SiO 2 defect band is larger (0.57 eV) than that of MoTe 2 conduction and SiO 2 defect band (0.18 eV) [22,23], leading to less hole trapping. Thus, V th under DC stress is relatively strong in PBS, compared to NBS. In addition, the recovery characteristics after bias stress were examined to consider the detrapping process. As shown in Figure 4c, after PBS and NBS for 1800 s, immediate recovery monitoring was conducted without any bias stress. Figure 4d displays the V th under bipolar stress is perfectly suppressed. To confirm the duty cycle condition of bipolar stress (i.e. bias polarity ratio) for suppression of V th , device instability under various frame time was investigated. Interestingly, as shown in Figure 5b, duty cycle condition for perfect V th suppression is different, according to a frame time. As frame time increase (i.e. frequency of pulse decrease), ratio of high level (+4) was reduced. This behaviour can be speculated from result of Figure 4a, where PBS shows clear frame time dependency for V th shift. As a result, even for bipolar stress, PBS strongly affects for V th than NBS as frame time decrease. Therefore, to have a balance, portion of high level (i.e. positive voltage) in bipolar pulse should be diminished for zero V th . Additionally, even with different bias voltage strength (i.e. ± 4.5, +3 and −5 V), V th could be successfully suppressed with optimised duty cycle depending on frame time. These results substantiate that bipolar stress mode could be effectively adopted, as compared with simple unipolar pulse stress with off-period for a practical application.
Conclusion: BSI in MoTe 2 FETs was investigated under DC and pulse mode stress. After encapsulation of the MoTe 2 FETs using CYTOP, charge trapping effects in air were intentionally decoupled with isolation of external effects related with oxygen (or/and moisture) as one of possible sources of the device instability. More severe V th for DC PBS, as compared to DC NBS, is possibly attributed to different barrier heights between MoTe 2 and SiO 2 layer for conduction and valence band, which is experimentally substantiated by pulse frequency dependent test and time constant evaluation of recovery. Under pulse mode stress, PBS (or NBS) shows dramatic (or gradual) reduction of V th shift. Furthermore, the frame time dependency on PBS in pulse mode was more clearly exhibited, compared with that of NBS. The BSI of MoTe 2 FETs in pulse mode operation can be effectively controlled via bipolar stress with optimised duty cycle.