Millimetre‐wave high–low IMPATT source development: First on‐chip experimental verification

This paper reports design and development of high–low type Si/SiCbased Impact Ionisation Avalanche Transit Time device and its on-chip characterisation. The design has been performed with indigenously developed strain engineered non-linear self-consistent large-signal simulator. On-chip hetero-structure SiC Impact Ionisation Avalanche Transit Time at 94 GHz has been successfully fabricated and on-chip DC testing (forward and reverse) results are reported for the first time. The device breaks down at 185 V (simulated result: 188 V) and breakdown current is ∼12.5 mA. If the diode chip is mounted properly with W-band waveguide, it is expected to generate ∼2 W of Radio Frequency (RF) power at W-band window frequency (∼94 GHz). The experimental verification of newly developed in-house strain-corrected mixed quantum tunnelling drift diffusion simulator is done successfully.

Introduction: Millimeter-wave frequency range of EM spectrum has immense application possibilities in the field of security sector for non-invasive imaging and improvised explosive device detection [1][2][3]. Amongst all two terminal millimetre-wave devices, Impact Ionisation Avalanche Transit Time (IMPATT) diodes have already proven their efficiency as high-power source in millimetre-/sub-millimetre-wave region [4][5][6]. Throughout the last decade, IMPATT diodes and oscillators have been steadily gaining significance in the field of high-power RF generation. However, most of the available IMPATT oscillators are fabricated with conventional Si or GaAs. But both Si and GaAs have intrinsic limitation of material parameters [7]. The capacity to deliver high power for an IMPATT oscillator depends on carrier saturation velocity, mobility, impact ionisation rate and breakdown electric field. Researchers are therefore searching for suitable semiconductor materials that exhibit such favourable material properties, for developing high-power, highfrequency IMPATT devices. Wide-band gap SiC and its hetero-structures are quite promising for high-frequency applications owing to superior material parameters, that is, 2× carrier saturation velocity, 5× mobility and 10× breakdown electric field than conventional Si [8]. Therefore, the current research has chosen SiC as a base material for the development of IMPATT oscillator chip [9,10].
Design of the device has been done through an indigenously developed strain-corrected mixed quantum tunnelling drift diffusion (Sc-MQTDD) simulator. The simulation has taken into account the effects of parasitic series resistance, quantum effects, junction temperature enhancement effects, lattice phonon interaction effects, generationrecombination of charge carriers, field-and temperature-dependent carrier saturation velocity, mobility and ionisation rates and both substrateand process-induced strains. Recent research has shown that the impact of process-induced strain on device characteristics is extremely significant [11][12][13][14][15][16]. Therefore, the previously used in-house simulator [17,18] has been modified by incorporating strain effects and the validity of the same has already been established [6]. The non-linear DC and large-signal properties of the device under test (DUT) are obtained for W-band operation. The fabrication of the device has been started with a high-resistivity Si substrate (1 × 10 26 m -3 concentrations). The epilayer of SiC (n-type on substrate, 3.5 × 10 23 m -3 doping) has been developed through metal organic chemical vapour deposition technique. A buffer layer of n + (6 × 10 23 m -3 ) was grown in between the substrate and nepilayer. The detailed of grown high-low structure is shown in Figure 1a. To the best of authors' knowledge, this is the first report on high-low IMPATT development and verification of the in-house simulator. Theoretical model: This paper designs and analyses the 2D vertical and asymmetrically doped Si/SiC-ATT (p ++ -n − n + -n ++ doping profile) device. Schematic representation of the designed diode is shown in Figure 1a. Throughout the current paper, in-plane means xy-plane and outof-plane implies z-direction. Physical properties of Si/SiC material along the symmetric axis of the device are obtained from published literature [8]. At each instant of time the physical properties such as electric field, electron and hole current components, recombination current are obtained by solving the non-linear field and carrier transport equations, that is, Poisson's equation and combined current continuity equations for various large-signal modulation factors at the edges of active region, subject to satisfaction of appropriate modified boundary conditions [19]. The authors have considered the effect of introducing an n-bump layer of appropriate doping concentration in between the substrate and epi-layer. The space-and time-dependent transport equations are described elsewhere [20,21]. The carrier generation rates due to avalanche multiplication and band to band tunnelling of electrons and holes are considered in the present model. The newly proposed Sc-MQTDD simulator is based on the solution of Schrodinger equation: where 2 (kx,y ) 2 2m * x,y and 2 2m * z ∂ 2 ∂z 2 are the in-plane and out-of-plane components, respectively.
where G QM is the Bohm quantum potential and is given as follows for electrons/holes: c n/p denotes electron/hole density: Subsequently, the continuity equation is written as where G An/p (z, t ) and G Tn/p (z, t ) are the avalanche and tunnelling generation rates, respectively. The details have been explained elsewhere [6]. In Equations (2), RB (z) is the potential due to reverse bias, for which the Poisson equation is as follows, with symbols having their usual meanings: and Deformation is the strain-induced deformation potential: where ε x,y, z is the induced strain due to doping, lattice and thermal mismatch. d i , C ii and C ij are relevant deformation and elastic constants, i, j ∈ x, y, z. Finally, the current density equation is written as The coupled Schrodinger-Poisson equations along with the current density and continuity equations have been solved simultaneously. Details of the approach that has been used for such purpose have been explained elsewhere [6]. Finally, the conductance and susceptance for the ATT diode are expressed as follows: where r ATT (ω) and x ATT (ω) are the resistance and reactance, respectively. The Poisson and current continuity equations are solved at each space-steps for each phase of time cycle ranging from T = 0 to 2π for different modulation index. At present, the authors have considered 50% modulation above the breakdown voltage. Through this double iterative, self-consistent, voltage exited model/technique quasi-2D space-time analysis of the DUT has been done. The present extensive model/simulation takes into account the mobile space-charge effect, carrier diffusion effect, charge carrier generation-recombination effects in the central region and involves double iteration over the magnitude and location of field maximum for obtaining electric field and current density profiles. The modified boundary conditions for electric field (E(x,t)) and normalised current density (P(x,t)), in Sc-MQTDD model are described elsewhere [20,21]. The large-signal impedance and admittance plots are obtained through the in-house simulator as described earlier [21].
Experimental procedure: A suitable 3C-SiC epilayer has been grown on Si(1 0 0) 1-10 Ω cm, substrates with 100 mm diameter. A heteroepitaxial Si/3C-SiC layers are grown by mixing together a C-based precursor with an Si-based gas chemical vapour deposition (CVD) reactor. This is done at a high temperature (>1250°C), and this requires controlling high temperature. It is to some extent difficult to control two separate precursors; Si and C and the use of a separate precursor could results in little departure from stoichiometry which in turn could lead to point defects, and will affect the device characteristics significantly. However, the rapid thermal processing CVD technique could be used as an alternative to conventional CVD, for the growth of SiC epilayers on to Si substrates at a growth temperature as low as 800°C. A single gas precursor, 'methylsilane; (SiCH 3 H 3 , with an Si:C ratio of 1:1 is used for SiC deposition. Boron is used to obtain p-type 3C-SiC, while phosphorus is used as an n-type dopant in 3C-SiC. The dopants are accomplished by introducing diborane and phosphine precursors. PIRANHA cleaning method is adopted for substrate cleaning. This is followed by dipping of substrates in dilute HF for 30 s, followed by rinsing in DI water before they are transferred to the deposition chamber (pressure ∼104 Torr).
As a result of large lattice mismatch (20%) along with the large difference in the thermal expansion coefficient (8%), coherent interface between 3C-SiC and cubic Si materials is hard to establish. A significant

Fig. 3 Comparison of experimental and simulation results
percentage of mismatches can be minimised through the formation of a dislocation network. However, the mismatch could introduce an additional strain in the system during the cooling process just after growth. All of these defects and strain could generate high-leakage currents in the p-n junction. Therefore, carbonisation of Si is done to improve the quality of SiC/Si interfaces before subsequent epitaxial growth. The use of germanium (Ge) in between the substrate and epilayer is expected to improve the surface morphology. Thus, to improve the crystal quality and to reduce the high-leakage currents, the experiment is carried out with the growth of 3C-SiC p-n junctions on a Ge-modified Si (1 0 0) substrate. Trapped charges are found to generate at the interface of substrate and epilayer. Oxidation process is done to rectify the issue. The defects at the semiconductor interface produced leakage current during reveres bias operation. Thermal oxidation has been done at the height of the first state of mesa. Low-resistance ohmic contacts are formed using E-beam evaporation techniques and photo-lithography, and mesa etching, following standard techniques, are performed sequentially to obtain on-chip diode dots. This is followed by on-chip I-V characterisations.

Results and discussions:
The schematic diagram of the fabricated device is shown in Figure 1a. Figure 1b shows the mesa diode with 50 μm diameter. The on-chip device is shown in Figure 1c. The reverse and forward characteristics are shown in Figure 2a and b, respectively. The simulated device is found to break down at 188 V. The large-signal simulation study depicts the variation of peak electric E(x) field profile with different phase angel for T = 0-2π . The RF power output from the simulated device is ∼10 W for a 3 × 3 array of diodes at a peak operating frequency of 94.3 GHz. Further experimental results show that the device breaks down at 185 V, close to the simulated data with the corresponding breakdown current ∼ 12.5 mA. Incorporation of Ge layer reduces the surface roughness significantly and thus the leakage current reduces. This in turn has increased the output power. If the diode chip is mounted properly with W-band waveguide and is expected to generate ∼2 W of RF power from a single diode at W-band window frequency (∼94.0 GHz). Variation of breakdown voltage and efficiency with the DC operating current density, under experimental and simulation conditions, are plotted in Figure 3. It is interesting to observe that within the range of operating current density (15 × 10 7 A/m 2 to 25 × 10 7 A/m 2 ), the agreement between theory and experiment is quite satisfactory. However, further increment of DC-operating current density results in the degradation of breakdown voltage in experimental observation. This is due to the fact that excessive junction temperature/joule heating in turn increases the parasitic effects and that degrades the overall device performance. Moreover, increasing bias current density increases the device efficiency up to 25 × 10 7 A/m 2 . It starts degrading with further increase in bias current density. The efficiency graph shows a tendency of saturation within the current density range of 20 × 10 7 A/m 2 to 30 × 10 7 A/m 2 . This may be explained in terms of enhancing undepleted epilayer with increasing current density as a result of mobile space-charge effect. This leads to the decrease in the voltage across avalanche region and the subsequent saturation of efficiency level.
Conclusion: For the first time, Si/SiC high-low type IMPATT source is developed and on-chip characterisation is reported. The potential of heterostructure IMPATT source at W-band frequency in terms of high power generation is reported. The experimental validation of the newly proposed Sc-MQTDD simulator is established.