Ultra-low power voltage reference with 40 μ A maximum load current for passive sensor systems

An ultra-low power, low temperature coefﬁcient voltage reference gen- erator used for nanowatt-level passive sensor systems is presented. The voltage reference conﬁguration, based on a voltage reference generat- ing circuit embedded in the feedback loop, realises an average reference voltage ( V REF ) of 837.2 mV and 40 μ A maximum load current. The temperature coefﬁcient of V REF is compensated by a saturated diode-connected the positive channel Metal Oxide Semiconductor (PMOS) and a proportional to absolute temperature current. For supply voltages ranging from 0.86 to 3 V, this proposed voltage reference simu- lated in 55 nm a Complementary Metal Oxide Semiconductor (CMOS) process consumes an average current of 10 nA at room temperature and achieves a minimum temperature coefﬁcient of 8.1 ppm/°C from − 40°C to 125°C. The mean line sensitivity is 0.17%/V and the coefﬁ- cient of variation is 2.1%. ,


Introduction:
Recently, many wireless sensor systems are often equipped with nanowatt energy harvester to realise passive design. With serious energy constraints, reliable and ultra-low power voltage references have attracted extensive research efforts [1][2][3][4][5]. Among the prior arts, these reference generators achieve the low power designs and provide the low temperature coefficient (TC) V REF , while these traditional reference generators need extra power management circuit to supply sensor systems. This letter proposes an ultra-low power voltage reference based on its negative feedback mechanism to generate a temperaturecompensated V REF , while it has a simple structure and realises the 40 μA maximum load current. The results simulated in 55 nm CMOS process show that this voltage reference achieves an average V REF of 837.2 mV with a minimum TC of 8.1 ppm/°C, while its total current dissipation is just 10 nA.
Circuit Description: The circuit of the proposed voltage reference is illustrated in Figure 1. This circuit has three parts: a start-up circuit, a proportional to absolute temperature (PTAT) current source and a voltage reference core. The start-up circuit is designed as a precautionary measure to ensure bias in the desired state.
The PTAT current source is a well-known beta multiplier current source configuration formed by M1-M4 and R1. With higher than 100 mV of the drain-to-source voltage (V DS ), the I-V characteristics of M1-M4 operating in sub-threshold region is given by [1,2] as where μ is the carrier mobility, C ox is the gate oxide capacitance per unit area, W and L are the channel width and length, respectively, m is the sub-threshold slope parameter, typically having a value of 1. is the gate-to-source voltage, V th is the threshold voltage of a MOSFET and V T is the thermal voltage. From Figure 1, there exist body effects in M3 and M6. The expression of V th is given by [3] as where V th0 is the threshold voltage with zero body bias, γ is the body effect constant, V SB is the source-to-bulk voltage of a MOSFET and F is the Fermi potential. Setting the size of M1 and M2 to be the same, while the aspect ratio of M3 and M4 as N 1 :1, the current going through R1 (I o ) can be obtained from expressions (1) and (2) as With the reduction in the reference current value, the size of R1 increases. The value of R1 is 21.4 M and I o ≈ 0.94 nA in this letter, while R1 is about 10 M and the reference current is 3.6 nA in [1].
For the voltage reference core composed of M8, M9, MP, M6 and R2, it can be regarded as a common source amplifier with M9 as input cascaded with a common gate amplifier with M6 as input. M5 is biased by the I o . M6 works in sub-threshold region. Setting the aspect ratio of M7 and M8 is 1:1 and the aspect ratio of M4 and M5 is 1:1, while the aspect ratio of M5 and M6 is 1:N 2 , V1 (in Figure 1) and the current going through R2 (I R2 ) can be obtained as With the aspect ratio of W P and L P much less than 1, MP is designed to be in the saturated region providing a temperature-compensated reference voltage higher than its threshold voltage at room temperature. From Figure 1, the current flowing through the MP is I d , expressed as Therefore, the voltage V REF can be illustrated as Substituting V T = K B T /q (K B is the Boltzmann constant, T is the absolute temperature and q is the charge of an electron), μ p = k μ T −β (k μ and β are the constant, β ≈ 1.4) and |V thP | = |V th_REF | − ηT (V thP is the threshold voltage of MP, V th_REF is the threshold voltage of MP at a reference temperature and η is the constant) into expression (7), V REF can be expressed as where the expressions of the parameters k, k 1 and k 2 are as follows: As observed, V REF in expression (8) has a specific value at a certain temperature with the parameters of the proposed voltage reference designed. Moreover, the value of V REF is not affected by the load current while the proposed voltage reference is in the desired state.
Ignoring the effects of temperature characteristics of R1 and R2 and taking a derivative with respect to temperature in expression (8), there is the following relation as   Table 1, are the most critical design parameters for the performance of the proposed voltage reference.
Considering the stability of the voltage reference core, the small signal model diagram of feedback loop is depicted in Figure 2.
The expression of the low-frequency open loop gain (K Loop ), dominant pole (p 1 ), non-dominant pole (p 2 ), zero pole (z 1 ) and output pole (p 3 ) are obtained as where g m6 , g m9 are the transconductances of M6 and M9, respectively, C A is the equivalent capacitance of point A. The expression of p 1 is 1/((r o6 //r o8 ) × (g m9 (r o9 //RL)Cc + C A )) C A is far less than  Figure 1), C MP is the equivalent source-drain capacitance of MP, r o9 is the small signal output impedance of M9, C L and R L are the equivalent capacitance and resistance of load, C C is a Miller compensation capacitor. C C splits the poles at the output node and at the output of point A, making the last one the dominant pole of the loop to reach stability. p 2 is much larger than the unit gain bandwidth of loop and p 3 is close to z 1 with the increase in load current.
Simulation Results: The performance of the proposed voltage reference has been determined in 55 nm CMOS process. The temperature characteristic of resistance is considered in the simulation of temperature coefficient. Figure 3 depicts the temperature characteristic curves of V REF at different supply voltages. For supply voltages ranging from 0.86 to 3 V, this voltage reference achieves an minimum TC of 8.1 ppm/°C from −40°C to 125°C and a 0.17%/V mean line sensitivity, while the load current is 0. The TC of voltage reference under different load currents is shown in Figure 4. This proposed voltage reference realises a TC less than 20 ppm/°C under the load currents ranging from 1 nA to 10 μA and achieves a TC between 20 ppm/°C and 35 ppm/°C under the load currents ranging from 10 to 40 μA. Figure 5 depicts the stability response simulation of voltage reference under the load currents ranging from 1 nA to 40 μA. The loop can provide a minimum 48 dB gain and a minimum phase margin about 64.2 o .
The simulation result of power-up is shown in Figure 6. The supply voltage is set at 1.2 V and the load current is set at 10 nA. The PTAT current source and the voltage reference core reach the desired state at 5.77 ms while the power on time of supply voltage is 2 ms.
The process variation and device mismatch of all devices except the resistors of proposed voltage reference are simulated by Monte Carlo. Figure 7 shows the Monte Carlo simulation results from 1000 samples. The coefficient of variation (=σ /μ, where μ and σ are the mean value  Table 1 shows the parameters in this voltage reference. Table 2 summarises the characteristics of the proposed voltage reference in comparison with prior arts. It can be noted that the proposed reference has the lowest TC, the maximum supply voltage range compared to [1,4,5] and consumes less power compared to [1,5]. Meanwhile, this proposed volt-