A 190.3-dBc/Hz FoM 16-GHz rotary travelling-wave oscillator with reliable direction control

This letter presents a rotary travelling-wave oscillator (RTWO) with re- liable direction control in a standard 130 nm complementary metal– oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16-stages customised transmission line segments are designed and simulated on electromagnetic tools. The PN is investigated through modelling the RTWO as multiple standing-wave oscillators. The proposed oscillator achieves 11.2% tuning range, 190.3 dBc/Hz ﬁgure-of-merit (FoM) at 1 MHz offset and 192.3 dBc/Hz FoM at 10 MHz offset with 5.8-mW power consumption from 16-GHz carrier.

Introduction: Voltage-controlled oscillators, dominating the noise and power consumption, are the core of phase-locked loop (PLL). Ring oscillators suffer from poor phase noise (PN) and less energy efficient compared to LC oscillators [1] due to the unavoidable noise injection in each stage and charging and discharging process in every clock cycle. Wavebased oscillators recently have gained interest because of its superior PN performance. Rotary travelling-wave oscillators (RTWO) utilising TL to form a Möbius loop naturally provide multiphases with high-resolution rail-to-rail outputs, enabling RTWO to be an excellent potential candidate for beam-forming itegrated-circuits (ICs) in 5G modem applications [2]. The RTWO was first presented by Wood [3], where RTWO arrays were utilised in a large chip to generate gigahertz clock. The authors in [4] demonstrated a 15 GHz RTWO in a 0.18 μm process with PN of -112 dBc/Hz at 1 MHz offset. Another design achieved 15 GHz with 182 dBc/Hz FoM in 90 nm CMOS [5]. A more recent work from Shehata et. al. [6] demonstrated a low flicker noise corner RTWO in a 22 nm fully-depleted-silicon-on-Insulator (FDSOI) technology. Multiphase square-like outputs suggest that RTWO can be employed in an all-digital PLL (ADPLL) to replace the power-hungry component, timeto-digital converter and digitally controlled oscillator (DCO). The deployment of RTWO in ADPLL was discussed in [7] in which a variable look-up table was created to adapt to the undetermined direction of the rotary wave. The authors in [8] proposed a phase-offset technique to force the direction of the wave while the reliability of the direction control scheme was not proved, the same as [9]. Motivated by the need for a power efficient and a reliable direction control RTWO, this letter presents a process-voltage-temperature (PVT) resilience direction control with tunable power consumption while maintaining low PN, achieving 190.3 dBc/Hz FoM.
Circuit topology: The proposed RTWO shown in Figure 1 is composed of a differential TL with a cross-connection to form a Möbius loop, requiring no termination and no matching. Consequently, the limitations on the load impedance mismatch and signal bandwidth are greatly alleviated. Unlike LC oscillator, the signal generated from RTWO not only keeps the fundamental harmonic but also maintains the odd harmonic components. Similar to the basic RTWO, gain stages are implemented by complementary latches, to compensate the loss of the resonator, sharpening the transition of the signal while keeping symmetric waveform to further decrease 1/f noise up-conversion degrading the close-in PN. To achieve multiple phases, low PN and low flicker noise corner frequency, the TL is divided into N segments (N = 16). PN is primarily dominated by the differential TL stages [10]. On the other hand, the increased num- The gated pair is tuned through binary-weighted switches. Junction varactors are inserted at every TL segment to widen tuning range. Attributed to the symmetric structure, the rotary wave can propagate to both clockwise (CW) and counterclockwise (CCW) direction. In the proposed design, static inverter-based buffers are intentionally inserted between each TL bank, formed by four consecutive TL segments, to introduce delay such that the travelling wave propagation is intervened by the in-balanced termination impedance of the TL during start-up. The delay is set sufficiently large to overcome PVT variations, thus ensuring robust propagation direction control.

ModeLling of RTWO:
Coplanar TLs can be modelled as lumped LC ladder assuming no loss from the TL. Considering differential inductance and capacitance per unit length, L 0 and C 0 , the phase velocity of the rotary wave is given by v p = 1 √ L0C0 , leading to the free-running frequency where N is the number of segment of the TL. The factor of 2 accounts for two complete waves travelling around the loop to form one cycle. It is noticed that the total differential inductance and capacitance are NL diff and NC diff , respectively [11].
Circuit design: To maximise the quality factor (Q) of the resonator, the top metal with a thickness of 4 μm is used to design the Möbius loop. Negligible sheet resistance benefits the energy stored in the TL. The cross-connections are implemented in metal 7 with 3 μm thickness. To keep inner and outer loops symmetry, metal 7 is also used in corners. The loop is designed and simulated based on electromagnetic tools. A 3-D view is presented in Figure 2(a). The simulated Q-factor and inductance at 16 GHz are shown in Figure 2(b). Several design iterations are required to adjust and optimise TLs spacing and width. Each four adjacent TL segments are conformed as a TL bank, including two gain stages and four tuning capacitor stages. Direction and power control signals are applied to the TL banks. Figure 3 shows two TL segments. The length for all transistors herein is selected to be the minimum length. The gain stages control rotation directions and adjust power consumption. The direction control bit 'dir' with an enable signal 'en', determine the direction of the travelling wave during the start-up. In each of direction control module, either the CW control or the CCW control is delayed by approximately 1 ns through a set of inverters. Combined with 4-bits power control signals, the direction control signal sequentially sets n-channel/p-channel mos transistor (NMOS/PMOS) switches of the cross-coupled pairs 'ON/OFF' such that the NMOS/PMOS pairs are powered ON/OFF under the direction control signals and 4-bits power control signals. Once the RTWO is oscillating, direction control bits hold the value until the next start-up, and power consumption is determined by the power control signals. Maximum power consumption of the oscillation suggests all four bits are '1' while the minimum power setting still maintains the oscillation. Note that randomly setting delay time may cause the failure of direction control. The delay cell must be properly sized providing 1 ns delay for two gain stages in each of TL bank to be turned on. Monte Carlo results proved a varying delay window affecting the success rate of the direction control. The minimum delay window at 15.1 GHz is 600 ps, while it changes to 200 ps at 16.9 GHz. It is confirmed that 1 ns delay is sufficient to ensure the direction control. The tuning is realised by deploying implanted junction varactor. In comparison with the NMOS varactor, junction varactor offers twofold Q-factor, benefiting the PN performance.
Phase noise: Similar to [11], linear time-invariant system and cyclostationary property are adopted to analyse RTWO noise. To simplify analysis and provide a more intuitive understanding of noise behaviour, an inverter latch is treated as two differential pairs. The noises are categorised into two sources: (i) Thermally induced resonator noise due to the loss of TL, and (ii) thermally induced differential pair noise.
Noise in the RTWO is analysed through the noise in standing-wave oscillator (SWO). The SWO is first viewed as a λ/4 TL. Modelling LC ladder as λ/4 TL, the input impedance Z(f 0 + f) of λ/4 can be expressed as − jZ 0 2 π f0 f , where Z 0 = √ L/C. The loss of the resonator is denoted by R p . Assuming half noise from R p contributes to the PN, for example, i 2 n = 1 2 4kT /R p , where k is Boltzmann constant and T is absolute temperature. The expression of PN due to thermal noise of resonator at the offset frequency f in the SWO is the same as the cross-coupled LC oscillator: where Q = π 2 R p /8Lω 0 , and V 0 = 4/π I D R p attributed to the differential property. I D is the summation of drain currents with V GS = V DD , and The noise current injected from differential pairs becomes strongest at which the drain voltage of two NMOS transistors are the same. This results in two strongest noise injection period, that is in every cycle of the clock. In the presence of this periodical noise injection, the thermally induced noise from the differential pair is cyclostationary. Its spectral density is scaled by a ratio of total injection time and the time period The total injection time is 4t in one cycle, T 0 , if each side of the noise conduction time at the zero-crossing point is denoted by t, which is given by t = √ 2Vod V0 1 2π T 0 , where V od is the overdrive voltage when the differential pair is in equilibrium. Since the current noise of the differential pair is given by i 2 n = 4kT γ g m , where g m = ID Vod , γ is the noise coefficient. Assuming g m, N = g m, P = 1/2g m , the total noise current is In analogous to Equation (1), PN due to the differential pair is derived as Underestimating t due to approximating transition smoothly will not affect the PN estimation as injected noise strength is overestimated. Equations (1) and (3) yield the total PN given by Equation (4) is the total PN in a λ/4 SWO. The RTWO is modelled as a superposition of multiple λ/2 SWOs [11]. It is necessary to modify the Q-factor in λ/4 SWO by replacing L with L/4, resulting in Q' = π 2 R p /2Lω 0 . The amplitude of RTWO is also reduced by a factor of 2, giving rise to total noise as where V 0 ' = 2/π I D R p .
Simulation results: The proposed RTWO was implemented in a standard 0.13 μm CMOS process from a 1.2 V supply. The S-parameter file of the TL segments was extracted in EM tools. The simulated tuning range is from 15.1 to 16.9 GHz. At 1 MHz offset, the maximum power consumption is 5.8 mW with FoM of 190.3 dBc/Hz; the minimum power consumption is 3 mW with FoM of 185.5 dBc/Hz. The PN at 1 MHz offset increases by 7 dB due to the small signal swing at the minimum power setting. Figure 4(a) shows the simulated PNs from 16 GHz carrier with 5.8 mW setting under five corners. The temperature for 'ss', 'ff', 'tt', 'fs' and 'sf' process corners were set as 120, 0, 27, 0 and 120 degrees, respectively. Figure 4(  To verify the direction control, two signals, for example, 157.5 and 168.75 degrees (Figure 1), were measured by the phase difference. For the CW and CCW wave propagation, the ideal phase difference is 11.15 and −11.15 degrees, respectively. Monte Carlo simulation, including the process spreading and device mismatch, is shown in Figure 6, demonstrating the robust direction control. The majority is falling into one σ .
Conclusion: An RTWO with reliable direction and power-saving control is proposed. The oscillator is operating at 16 GHz with 11.2% tuning range, drawing power from 5.8 to 3 mW. Table 1