Dynamic characteristics after bias stress of GaN HEMTs with ﬁeld plate on free-standing GaN substrate

This paper investigates the electron trapping behaviour after bias stress in GaN high-electron-mobility transistors (HEMTs) fabricated on GaN substrate. On-resistance ( R ON ) and electron-trap-induced thresh- old voltage shift ( (cid:2) V th ) of GaN HEMTs on GaN substrate are determined by gate quiescent bias ( V gq ) and independent of drain quiescent bias( V dq ).ThisresultindicatesthatthecurrentcollapseofGaNHEMTs is mainly attributed to the electron injection in barrier layer under gate region. Moreover, time constants of electron emission are dependent on the V gq . At least two time constants ( τ 1 and τ 2 ) are found to exist in the HEMTs after being switched from an off-state ( V gq ≤ − 30 V, V dq = 0 V) to an open channel condition. The τ 1 and τ 2 continue to increase with increasing | V gq |. It is speculated that the presence of multi-trap energy states in barrier layer results in the quiescent bias-dependence of time constants.

✉ Email: qiangma2007@gmail.com This paper investigates the electron trapping behaviour after bias stress in GaN high-electron-mobility transistors (HEMTs) fabricated on GaN substrate. On-resistance (R ON ) and electron-trap-induced threshold voltage shift ( V th ) of GaN HEMTs on GaN substrate are determined by gate quiescent bias (V gq ) and independent of drain quiescent bias (V dq ). This result indicates that the current collapse of GaN HEMTs is mainly attributed to the electron injection in barrier layer under gate region. Moreover, time constants of electron emission are dependent on the V gq . At least two time constants (τ 1 and τ 2 ) are found to exist in the HEMTs after being switched from an off-state (V gq ≤ −30 V, V dq = 0 V) to an open channel condition. The τ 1 and τ 2 continue to increase with increasing |V gq |. It is speculated that the presence of multi-trap energy states in barrier layer results in the quiescent bias-dependence of time constants.
Introduction: GaN high-electron-mobility transistors (HEMTs) on freestanding GaN substrate, associated with high critical electric field and large charge densities, have been expected to be used in the field of high-frequency and high-power applications [1]. Until now, different kind of substrates, such as silicon, silicon carbide (SiC), and sapphire, have been used to fabricate GaN HEMTs [2][3][4]. However, because of the crystal lattice mismatch and difference in thermal expansion coefficient between GaN and these substrates, lattice defects are easily introduced into the buffer layer during the process of epitaxial growth. The dislocation can extend to the entire thickness of the epitaxial layer and lead to the formation of trap states, which captures electrons under a biasing condition.
Free-standing GaN substrate is considered a promising substrate candidate to limit the formation of lattice defects. The first AlGaN/GaN HEMTs on bulk GaN substrate was fabricated by Khan et al. in 2000 [5]. Since then, many efforts have been devoted to develop GaN HEMTs on GaN substrate with high performance, such as an output power density of 9.4 W mm −1 at 10 GHz, a cut-off frequency f T of 165 GHz and a high breakdown voltage [6][7][8]. However, the performance and reliability of the GaN HEMTs are always limited by the electron trapping and emission behaviour. A high gate-drain quiescent bias or RF operation can lead to electron trapping in trap states under gate or in gate-drain access region. This results in an increase in on-resistance (R ON ) and a current collapse.
A high-quality homo-epitaxial layer on GaN substrate can possibly suppress electron capture in deep levels of GaN buffer layer [9]. A passivation layer on GaN HEMTs can reduce electron trapping in surface states. However, electron injection in AlGaN barrier layer under gate or gate insulator also causes a severe current collapse and V th instability in GaN HEMTs fabricated on GaN substrate. The V th instability can induce a gate degradation and influence the device reliability. Therefore, investigating electron-trapping-induced degradation of GaN HEMTs on GaN substrate is useful for its practical applications.
In this paper, GaN HEMTs with a field plate (FP) on GaN substrate was evaluated to investigate its current collapse, V th , and transient response of I d in an on-state condition after biasing stress. Degradation mechanisms of GaN HEMTs was analysed according to the changes of transient I d and time constant.
Device fabrication: A structure of a GaN HEMTs on a GaN substrate is shown in Figure 1. An AlGaN/GaN hetero-structure fabricated in this study was grown on a GaN substrate. The pre-treatment of GaN substrates was a thermal cleaning in the growth chamber. Al-content of the barrier is 0.22. The dislocation density of GaN epilayer is less than 5E6/cm 2 . Mo/Al/Mo/Au ohmic electrodes for source and drain were deposited by the electron beam evaporation, followed by rapid thermal annealing at 850°C for 5 min in N 2 ambient. Thereafter, samples were passivated by using a 60 nm thick SiN, deposited by plasma-enhanced chemical vapour deposition. A gate window was opened by dry etching of SiN film, followed by Schottky gate and FP formation with Ni/Au. A gate length (L g ), a source to gate distance (L sg ), a gate to drain distance (L gd ) and a length of FP (L FP ) were fixed to 0.8, 1.0, 2.0 and 1.0 μm, respectively. The gate width is 100 μm. Here, we defined L FP as over hanged length of the gate electrode towards the drain electrode over the SiN film.
Device characterisation: To understand the current collapse mechanism of GaN HEMTs with 1.0-μm-long FP on GaN substrate, gate and drain lag measurements were carried out at room temperature. Quiescent bias points of (V dq , V gq ) = (0 V, −10 to −20 V) were set for gate lag measurement. And (V dq , V gq ) = (10-40 V, −10 V) were set for drain lag measurement. The pulse width was 10 ms and the duty cycle was 10%. Figure 2a shows that the pulse I d -V ds characteristics of GaN HEMTs are determined by different quiescent bias (V gq ). In the case of V gq ≤ −10V, GaN HEMTs on GaN substrate is tough against the gate quiescent bias. A drop of the I d increases with decreasing V gq from −10 to −20 V and there is no change in the knee voltage. This means that the gate lag effect is obvious in GaN HEMTs on GaN substrate. Figure 2b displays that the pulse I d -V ds curve has a slight change as the V dq increases from 10 V to 40 V. As well known, the gate lag effect is related to the electron trapping in the deep level of barrier layer under gate. And the drain lag effect is attributed to electron injection into deep-level traps in the buffer or substrate layer. Therefore, based on the changes of the pulse I d -V ds characteristics in Figure 2, it is considered that the current collapse in GaN HEMTs on GaN substrate is mainly attributed to the electron injection in AlGaN barrier layer. It is to be noted that the stress V gq = −20 V is hardly applied between gate and source of HEMTs in their usual operation. Because for high V gq , a current leakage will cause a serious current collapse. This phenomenon has been observed in GaN HEMTs on sapphire substrate [10]. Figure 3 shows the influence of V gq and V dq on I d -V gs characteristics of GaN HEMTs with 1.0-μm-length FP on GaN substrate. The change in the V th at an off-state is similar to the current collapse. The V th increases with the increasing |V gq |, and is independent of the V dq . The result provides an evidence of the presence of electron injection in barrier layer under gate region. Moreover, I d -V gs characteristics of the GaN HEMTs in our work is stable in the case of V gq = −10 V. The injected electrons possibly originate from a gate leakage at an off-state. Figure 4 shows the gate leakage current (I gleak ) in GaN HEMTs on GaN substrate as a function of the V gq . The I gleak rises from 1.9 × 10 -1 μA/mm to      Figure 3a, it is speculated that a gate leakage injection into the trap states located below the gate leads to a reduction of two-dimensional electron gas (2DEG) density and a shiftof the V th . Transient I d response of GaN HEMTs 1.0-μm-length FP on GaN substrate was measured at different V gq , in order to study the characteristics of trap energy states in barrier layer. As shown in Figure 5a, transient I d in early time (≤ 10 -3 sec.) decreases with the increasing |V gq |. As the time prolongs, transient I d starts to exponentially recover and reaches an equilibrium value, which is almost identical to the dc I d . The recovery of the transient I d is delayed with the increase of |V gq |. The results indicate that high gate quiescent bias causes a strong increase in the trapping effects of the electron. Time constants of electron emission were extracted with an exponential fitting of the I d -t curves in Figure 5a by using the following equation [11]:  Figure 5b shows the time constants as a function of the V gq . As V gq ≥ −20 V, a unique time constant (τ 1 ) is extracted from the curve of transient I d . In the case of V gq ≤ −30 V, at least two time constants (τ 1 and τ 2 ) are required for suitable experimental results. Both τ 1 and τ 2 increase with a decreasing V gq from −10 V to −40 V. Figure 6 shows the transient I d response of the GaN HEMTs on GaN substrate with different filling time ranging from 0.1 to 10 s. V dq and V gq were set at 0 V and −30 V, respectively. The inset exhibits the relationship between the extracted time constants and the filling duration time. The results indicate that the transient I d and the time constants are independent of the filling time.

Fig. 2 The dc and pulsed I d -V ds characteristics of GaN high-electronmobility transistors (HEMTs) with 1.0-μm-length field plate (FP) on GaN substrate under: (a) various quiescent bias (V gq ) conditions and V dq = 0 V; (b) various independent of drain quiescent bias (V dq ) conditions and
Several mechanisms of electron trapping in GaN HEMTs at an offstate were mentioned in the literature. One is the electron injection into gate insulator or the barrier layer, which results in an increase in R on and a shift of V th [2,12]. Another is electron trapping in passivation layer or buffer layer in the gate-drain access region, which induces current collapse without obvious V th [13]. According to the V th of the HEMTs on GaN substrate in Figure 3, it is considered that the τ 1 and τ 2 originate from the trap states mainly distributing in the barrier layer. A change in the V gq from −10 V to −40 V leads to an enhancement of electric field strength under gate of GaN HEMTs. After being accelerated by the strong electric field, electrons obtain high kinetic energy to fill in the deep levels of the barrier layer. In case of the electron injection into multi-trap energy levels, multiple time constants are possibly extracted and increased with quiescent bias [14].
Conclusion: Electron behaviour of GaN HEMTs on GaN substrate was investigated. Based on the gate lag effects, the current collapse and the V th in GaN HEMTs are mainly determined by the electron injection in the barrier layer under gate. Moreover, the time constants of electron emission increase with increasing |V gq |. As the V gq is less than -30 V, at least two time constants are found to exist in the GaN HEMTs.