A compact broadband ESD protection circuit using multi-layer helical inductor

Here,abroadbandelectrostaticdischarge(ESD)protectioncircuitusingarea-efﬁcientmulti-layerhelicalinductorsispresented.Theproposedconceptwasveriﬁedina0.18 μ m 1P6M CMOS process, and the circuit area is only 54 × 63 μ m 2 . The measurement results show that a bandwidth of around 30 GHz is achieved, and the impedance matching is kept under –20 dB up to 40 GHz. The measured TLP and VF-TLP currents reach 2.19 and 5.80 A, respectively, which indicates a good ESD robustness.

Circuit description: Figure 1 shows the schematic diagram of the proposed circuit. The 3D structure of the multi-layer helical inductor is also shown in the figure. There is only one turn in each metal layer, which leads to a high quality factor due to the lack of the proximity effects between the parallel metal paths in the same metal layer [11]. As a T-coil, the helical inductor has three ports including Port A at the top layer, Port B at the bottom layer and Port X at the middle point along the path from Port A to Port B. Port A is tied to the input port of the circuit, and Port B is tied to the termination resistor R T in order to lower the impact of the inductor-to-substrate parasitics on the input port. Port X is connected to the internal core circuit. The inductor and C B work as low impedance paths for low and high frequencies, respectively, which helps to produce a broadband impedance matching.
The diodes are distributed among Port A, Port B and Port X. The parasitic junction capacitances of the diodes and the input capacitance of the internal core circuit have significant impacts on the frequency characteristics of the circuit. But, if designed properly, the transfer func-Core circuit to be protected Multi-layer Helical Inductor   Test chip: We verified the proposed concept by using a 0.18 μm 1P6M CMOS process. D P and D N are implemented with P+/N-well and N+/Psub diodes, respectively. The total width of diode D P (D N ) is 60 μm, and distributes at Port A, Port B and Port X as listed in Table 1. An nmos transistor M 0 with a size of W/L = 80 μm/0.18 μm is employed to emulate the core circuit to be protected as shown in Figure 2 [12]. An additional version of the test circuit implementing the conventional dual-diode circuit was also fabricated. The total width of the diodes and the size of M 0 are the same as above. With proper voltage bias, M 0 equivalents to a loading capacitance of 167 fF, and the parasitic capacitances of D P and D N are 36 and 40 fF, respectively. The multi-layer helical inductor uses 5 metal layers, from M2 to M6. The inner diameter and the path width are 25 and 5 μm, respectively. The total inductance of the inductor is about 1 nH, and the coupling coefficient k between the upper and the lower half of the inductor is about 0.7. In consideration of the parasitic capacitance between the stacked metal layers, we remove C B for the final version of the test circuit, which simplifies the circuit and reduces the area. Figure 3 shows the chip micrograph of the test circuits. The total area of the proposed circuit, including the helical inductor, all the diodes and the termination resistor, is 54 × 63 μm 2 .
Frequency characteristics: We use Keysight N5247A and RF probe stations to perform the two-port S parameter measurement. The frequency range is from 10 MHz to 40 GHz. The measured data are then transferred

Fig. 4 Measured reflection coefficient and transfer function
to Z parameters. The impedance matching status of the input port (Port 1) is characterized by the reflection coefficient , which is calculated with Z 11 , as follows: The transfer function V x /I in can be directly obtained from Z 21 . Figure 4 shows the reflection coefficient in decibel. For the conventional dual-diode circuit, it is shown that the matching of the impedance degrades rapidly as the frequency increases, and will be inferior to that of the proposed circuits when the frequency exceeds 3 GHz. While, the reflection coefficients of the proposed circuit maintain less than -20 dB even up to 40 GHz. Figure 4 also shows the relative transfer function, also in decibel. R 0 is the resistance at low frequency, which is 50 for the conventional dual-diode circuit and 57.5 for the proposed circuit. Due to the series resistance of the inductor, the input dc resistance of the proposed circuit is a bit larger than 50 . From the figure, the -3 dB bandwidth for the conventional dual-diode circuit is only 6.9 GHz, while for the proposed circuit, it is shown that the -3 dB bandwidth is around 30 GHz, which is much better than that of the conventional dual-diode circuit.
ESD characteristics: All ESD tests were conducted on an ES620 transmission line pulse (TLP) testing system, using the standard four-wire Kelvin method. A rise time of 1 ns and a pulse width of 100 ns are used as a normal TLP test setting to evaluate the current handling ability of the circuits under human body model (HBM) ESD stress, and a rise time of 0.3 ns and a pulse width of 5 ns are used as a very fast TLP (VF-TLP) test setting to evaluate the under charged device model (CDM) ESD stress. Figures 5 and 6 show the measured TLP and VF-TLP I-V curves, respectively. Both PD and PS results are given. The snapback behaviour in the PS curves attributes to the turning on of the power rail ESD clamp circuit. The secondary breakdown current (It 2 ) of each curve is extracted and listed in Table 1. It is found that D p1 burns down and the metal over it gets fused for the proposed circuit. Though the T-coil circuit actually shows a lower current handling ability than the conventional dual-diode circuit in VF-TLP test, it still provides good ESD robustness.
Compared with the corresponding parameters from [7], it worth noting that the area of the proposed circuit is only 42% as that in [7], which is 85 × 95 μm 2 .
Conclusion: A compact broadband ESD protection circuit using multilayer helical inductor is proposed, which occupies a much smaller chip area compared to the prior art which uses a planar inductor. Meanwhile, it provides ∼30 GHz bandwidth and good ESD robustness, which make it suitable for the design of high speed and broadband circuits.