All-SiC 99.4%-efﬁcient three-phase T-type inverter with DC-side common-mode ﬁlter

This letter presents a hardware demonstrator of an all-SiC three-level T-type (3LTT) inverter with the common-mode (CM) EMI ﬁlter stages placed on the DC input instead of the AC output side, targeting, for example, high-efﬁciency PV applications. The extensive experimental characterization shows that state-of-the-art SiC transistors and a DC-side CM ﬁlter enable an unprecedented peak/full-load efﬁciency of 99.4% (calorimetric measurement) at 12.5 kW and a power density of 2.4 kW/dm 3 (39 W/in 3 ). The demonstrator fulﬁlls CISPR 11 Class A EMI regulations as well as upcoming EMI standards for the frequency range of 9–150 kHz. Compared to other high-efﬁciency converters, which often employ bridge legs with more output voltage levels, the described 3LTT concept thus offers a very favorable trade-off between complexity and performance.

Introduction: Over the past decade, the global photovoltaics (PV) market has rapidly grown with a compound annual growth rate (CAGR) of 34% [1], with PV contributing by far the largest share of added renewables per year [2]. Thus, a worldwide PV generation capacity of about 940 GW has been reached at the end of 2021 [3]. In this context, there is a clear demand for the power electronics, especially the inverters that interface PV installations to the mains, to achieve ever higher conversion efficiencies with limited complexity and hence cost [4][5][6].
Targeting high-efficiency inverter systems, multilevel topologies are promising candidates [7][8][9], as power semiconductors with lower blocking voltage ratings and hence favorable conduction and switching characteristics can be employed. For example, a recently presented 10 kW active-neutral-point-clamped (ANPC) three-phase inverter employing a hybrid Si/GaN semiconductor configuration achieves a peak efficiency of 99.3% (at 5 kW), features a power density of 2.4 kW/dm 3 , and fulfills the CISPR 11 Class A EMI regulations [10]. Similarly, some of the authors have investigated a 12.5 kW all-Si seven-level hybrid ANPC (7LHANPC) inverter in [11], which achieves a peak efficiency of 99.35% (at 10 kW), features a power density of 3.4 kW/dm 3 , and also complies with CISPR 11 Class A.
However, the 7LHANPC approach is relatively complex due to the high transistor count (30 transistors in a three-phase inverter). It is therefore an interesting question whether similar performance can be achieved with reduced complexity. Three-level topologies have been found to offer interesting trade-offs between efficiency and power density [12,13]. In particular, the three-level T-type (3LTT) topology originally proposed in the 1970s for thyristor-based circuits [14][15][16] is of high interest, because a three-phase AC-DC converter system can be realized with only 12 transistors. Even though half of the transistors must block the full DC-link voltage, we demonstrate in this letter that with state-of-the-art SiC transistors and an advantageous arrangement of the common-mode (CM) filter on the DC side [17, p. 36], [6,12,18], very high efficiencies can be achieved. Specifically, the designed 12.5 kW demonstrator features an unprecedented peak efficiency of 99.4% (calorimetrically measured at full load), a power density of 2.4 kW/dm 3 , and fulfills the CISPR 11 Class A standard as well as upcoming EMI limits for the frequency range of 9-150 kHz.
In the following, we thus discuss first the advantages of a (fully passive; in contrast to the active DC-side CM filter discussed in [6]) DC-side CM filter for grid-connected converters, briefly summarize key hardware design aspects, present the complete experimental characterization of the 3LTT demonstrator, and compare the results with those of the mentioned 7LHANPC system [11]. DC-side common-mode EMI filter: Figure 1a shows a typical realization of a three-phase EMI filter with the differential-mode (DM) and CM filter elements on the AC side. Note that the DC-link midpoint is capacitively (via C cm ) connected to the star point formed by the three DM filter capacitors. This internal CM filtering approach has been proposed in the 1990s [19][20][21] for various topologies. Advantageously, relatively large values for C cm can be selected, as the resulting CM current remains inside the converter and does not flow to earth, that is, the value of C cm is not restricted by touch current limits. Further, note that if the modulation employs third-harmonic injection (which advantageously can prevent a 150 Hz current flowing into the DC-link midpoint and hence facilitates a reduction of the DC-link capacitance [12]), the corresponding lowfrequency (LF) CM voltage appears at the DC terminals, that is, across the ground capacitance of the DC-side assembly (e.g. the PV panels). If the parasitic ground capacitances of the DC-side assembly would result in too high LF ground leakage current, which could trip residual current devices (RCDs), no third-harmonic injection should be used; furthermore, the leakage current could even be closed-loop controlled to zero [22].
Whereas in typical grid-connected motor drives an EMI limit applies at the AC input terminals, there are also multi-drive applications where the individual inverters operate from a distributed DC bus. Then, in certain applications, the EMI limits must be fulfilled at the inverter's DC input terminals but not at its AC output terminals; hence, a DC-side placement of CM filters is needed [23]. However, as initially proposed in [17, p. 36] and shown in Figure 1b, the CM inductor can be moved to the DC side also for grid-connected converters (for which the EMI limits apply on the AC side) without changing the system's behavior with respect to the DC and AC terminals. With the modulation index defined as M = √ 2V ac /(V dc /2), the AC-and DC-side power balance yields where V ac and I ac are the rms phase voltage and current, respectively. The ratio of the winding losses of a DC-side CM inductor to those of an AC-side CM inductor becomes CM equivalent circuit (C g represents the ground capacitance of the DC-side circuitry, for example, the PV panels, see Figure 1). Note that the equivalent circuit is simplified considering C cm C dm ; even though L cm L dm would allow a like simplification, the effective CM inductances of the DM inductors are indicated to facilitate the explanation of a potential resonance of L dm1 /3 with C par1 and C Y2 .
where R w,dc and R w,ac denote the respective winding resistances. Finally, considering the same core and the same total copper usage for both types of CM chokes implies R w,dc /R w,ac = 2/3 and for a typical modulation index of M ≈ 0.9. This significant reduction of the low-frequency copper losses by about 60% is augmented by the absence of any significant high-frequency (HF) copper losses: except for the very small CM current, no HF currents flow on the DC side, whereas at least the first-stage CM inductor on the AC side would be exposed to the typically high DM HF ripple currents in the boost inductors [12]. On the other hand, also the DC-side of the switching stage is now subject to a high-frequency CM voltage with respect to ground. Figure 2 shows the full power circuit of the 3LTT demonstrator implementing such a (two-stage) DC-side CM filter and the corresponding CM equivalent circuit. Note that in a practical realization, the presence of parasitic capacitances between the switching stage and ground (C par1 , C par2 ) necessitates the placement of a (small) CM choke L cm3 at the grid terminals (i.e. on the AC side) and of a Y-capacitor C Y2 , because the internal CM filter arrangement does not provide any attenuation for CM currents through these parasitic capacitances [21]. Furthermore, as discussed in [18] for a single-stage DC-side CM filter without using the internal filtering approach (C cm1 and C cm2 ), the parasitic capacitances from the DC bus to ground, C par1 , the Y2 capacitor C Y2 , and the effective CM inductance of the three first-stage DM inductors, L dm1 /3, form a resonant loop (see Figure 2b) that could cause excessive noise emissions at its resonant frequency (in the lower megahertz range with an estimated C par1 ≈ 200 pF). With the selected hardware realization of the DM inductors (see below) using nanocrystalline cores and solid flat-wire windings, however, that resonance is sufficiently damped.
Hardware implementation: A 12.5 kW three-phase 3LTT inverter with the power circuit from Figure 2a has been implemented to demonstrate the high performance that a 3LTT topology with SiC transistors and a DC-side CM filter achieves. The employed design procedure including component modeling has been comprehensively described in [12]. For the sake of conciseness, we do only briefly reiterate key aspects here and Table 1 provides an overview of the components used for the hardware realization.
A relatively moderate switching frequency of 20 kHz is needed to limit the switching losses, whose estimation takes into account the additional capacitive loss contributions found in 3LTT bridge-legs [24]. At these operating frequencies, nanocrystalline core materials (specifically,

Fig. 3 12.5 kW three-phase inverter demonstrator systems realized as (a) all-SiC 3LTT inverter with DC-side CM filter (this work) and, for comparison, (b) as all-Si seven-level hybrid active-neutral-point-clamped/flying-capacitor converter (7LHANPC) [11]. (c) Volume breakdown of the two demonstrator systems. The 3LTT demonstrator's power density is 2.4 kW/dm 3 (39 W/in 3 ) and the 7LHANPC prototype's is 3.4 kW/dm 3 (56 W/in 3 ).
Hitachi Finemet F3CC) are well suited, and solid rectangular wire (i.e. helical) windings can be used instead of Litz wire windings. However, as known from literature such as [25,26], estimating core losses of (gapped) nanocrystalline cores is prone to significant errors, for example, caused by misalignments and resulting magnetic field components that are perpendicular to the nanocrystalline laminations. Therefore, we have employed calorimetric pre-characterization measurements of L dm1 and L cm1 prototype realizations to improve the overall converter loss estimation compared to [12]. As can be seen in Figure 2a, the DC link features a combination of foil capacitors (C dc,F ) and additional electrolytic capacitors (C dc,E ), which would facilitate operation without third-harmonic injection and hence a corresponding 150 Hz current flowing into the DC-link midpoint. The prototype achieves a volumetric power density of 2.4 kW/dm 3 (39 W/in 3 ), see Figure 3a. 1 The 7LHANPC prototype described in [11] and shown in Figure 3b is more compact (3.4 kW/dm 3 or 56 W/in 3 ), mainly because the higher level count facilitates significantly smaller magnetic components. This also explains the lower weight of 4.8 kg (i.e. the gravimetric power density is 2.6 kW/kg) compared to the 3LTT inverter's 11.8 kg (1.1 kW/kg). Figure 4 shows measured key waveforms of the 3LTT demonstrator operating from a 720 V DC voltage supply and with a 10 kW resistive three-phase load. The expected (see Figure 1b) separation of HF and LF CM voltage components is clearly visible; note that sinusoidal thirdharmonic injection with M 3 = √ 2V ac,(3) /(V dc /2) = 0.25 has been used to almost completely mitigate any 150 Hz DC-link midpoint current.
Efficiency measurement: Due to the high expected efficiency levels, the specified accuracy of commercial power analyzers that rely on electrical measurements is at least theoretically not sufficient [11]. Therefore, a high-precision double-wall calorimeter [27] has been used to measure the efficiency characteristics at 720 V DC and 650 V DC shown in Figure 5. At 650 V DC, the 3LTT demonstrator achieves an unprecedented peak/full-load efficiency of 99.4%, and at 720 V DC still 99.3% (at full load). The figure also shows the (calorimetrically) measured efficiency characteristics of the all-Si 7LHANPC demonstrator as given in [11] for comparison purposes. Whereas the peak efficiencies are similar, the 7LHANPC inverter's efficiency curve bends downwards with increasing power, which can be attributed mostly to the comparably high number of semiconductors in the current path (see also Figure 3b) and to the stronger positive temperature coefficient of the Si transistors' onstate resistances, that is, to overall larger ohmic (quadratic) loss components. Interestingly, at 720 V, the 12.5 kW 3LTT inverter achieves a Fig. 5 Calorimetrically measured efficiencies of the 3LTT demonstrator operating with 720 V and 650 V DC input and resistive load, and calculated curve for 720 V DC (as described in [12], but using the L dm1 and L cm1 losses obtained from component-level pre-characterization). For reference, the calorimetric measurement results for the 7LHANPC prototype from [11] are shown, too.

Fig. 6
Conducted EMI noise emission spectrum of the 3LTT demonstrator operating with 720 V DC. The CISPR 11 peak (PK) detector has been used with a 2 kHz step size, 9 kHz resolution bandwidth, and 10 ms measurement time for frequencies >150 kHz, and with a resolution bandwidth of 200 Hz for frequencies <150 kHz. In addition to the CISPR 11 Class A limit, also a proposed limit (IEC TS 62578 Class 2) for the frequency range of 9-150 kHz is indicated. Selected peaks (see markers) have been measured with the quasipeak (QP) detector during a 1 s measurement window. For reference, we also show the measurement results for the 7LHANPC demonstrator from [11].
fitted European Weighted Efficiency of 98.8% and a CEC efficiency of 99.1% but the 7LHANPC inverter shows very similar values of 98.9% and 99.1%, respectively, despite the quite different efficiency characteristics.
Conducted EMI pre-compliance tests: Finally, conducted EMI precompliance tests have been carried out to assess the 3LTT demonstrator's compliance with CISPR 11 Class A as well as proposed limits for the frequency range of 9-150 kHz (IEC TS 62578 Class 2). The measurement setup consists of a Rhode & Schwarz ESH2-Z5 three-phase LISN and a Rhode & Schwarz ESPI3 EMI test receiver. The converter was placed on an appropriately sized, grounded aluminum plate emulating a housing to which C Y2 is connected. The AC-side CM choke L cm3 (see Figure 2a) is realized externally with 3 × 3 turns on a VAC Vitroperm 500F W516-03 core, resulting in a measured CM inductance of 142 µH; as mentioned above, a much smaller realization would be possible without significantly affecting the overall converter volume or losses. Figure 6 shows the measurement results and demonstrates compliance with both limits, including a minimum quasi-peak (QP) margin of 12 dBµV at 160 kHz, that is, the 8th harmonic of the switching frequency. Note the minor bump in the emission spectrum at around 1.7 MHz: this can be attributed to the above-mentioned resonance between C par1 , C Y2 , and L dm1 /3, which is well damped because of the DM inductors' core and winding losses in this frequency range. Thus, the DC-side CM filter provides the expected attenuation and shows the aforementioned advantages compared to the typical AC-side placement.