Selection of capacitance for stable operation of low power DC system with constant power loads

The connection of constant power loads (CPL) in a low power dc system leads to a reduction in the stability margin of the system. Most of the existing techniques increase the stability margin by modifying the controller for CPL or source converter at the cost of deterioration in the performance of converters. Few publications have suggested methods to determine the value of dc-link capacitance required for stable operation of dc microgrid with CPL. These methods do not necessarily give the minimum possible capacitance as a solution. This paper suggests a method to determine the lower bound on the value of capacitor, for stable operation of dc system. A dc system with both linear and CPL loads is considered. Detailed mathematical analysis is used to determine the range of capacitance to ensure the stability of equilibrium point. Further, this paper discusses the effects of variation in linear loads on the selection of capacitor. The procedure of capacitor selection for a low power dc system is included. Using the real-time digital simulator and a digital signal processor, controller hardware-in-loop based validation is carried out for the proposed approach.


FIGURE 1 Schematic of low power dc system
Power drawn by linear and CPL loads vary over time and therefore system should be designed to ensure stable operation for the complete range of linear and nonlinear CPL loads. Some of the stability criteria used to study stability of dc systems with CPL are discussed in [19].
To compensate for the destabilizing effect of CPL, impedance compensation techniques are used [20][21][22][23][24][25][26][27][28][29]. These techniques modify or reshape the equivalent output impedance of source or input impedance of CPL converters to meet the stability criteria. Method to modify source impedance using passive components is discussed in [20]. Though, the method is capable of maintaining stability, it may lead to increased losses due to additional resistive components. This method also increases the cost and size of the system. Therefore, active methods based on the emulation of impedance are more popular in literature. Three techniques for realizing active damping in the source side converter are presented in [21]. The suggested techniques modify the output impedance of voltage source converter which is used to interface ac system to the dc microgrid. Each technique has its advantages and limitations over another in reference to phase margin and voltage sensitivity, which is usually user-specific. The effectiveness of the suggested techniques is validated for a dc microgrid connected to ac system. To enhance the performance of the system, two virtual impedance loops in which one emulates impedance in series with intermediate converter and the other in series with capacitor filter of the intermediate converter are emulated [22]. However, it requires one additional converter called intermediate converter to implement the suggested methods, which may not necessarily be available in generic dc microgrids. Further, the implementation of suggested active damping method requires additional sensors, which increases the cost of the system. Virtual resistance is emulated in series with the source in [23]. This increases damp-ing, but may increase error in power-sharing among different sources and deterioration of voltage regulation. To enhance the current sharing performance and stability margin of dc system, frequency dependent virtual impedance methods are suggested in [24][25][26]. In [24], a first order low pass filter is introduced in droop controller. By adjusting the cut-off frequency of low pass filter in range of oscillations produced by CPL, the instability due to CPL may be compensated. However, the performance of the suggested method deteriorates due to variation in parameters of dc system. The voltage regulation becomes poor at heavy loads. To minimize the effect of variation in system parameters on the active damping method and to improve voltage regulation at heavy loads, a virtual impedance including parallel R-L branch is emulated in [25]. The virtual impedance is designed in such a way that during step variation in load demand, the behaviour of virtual R-L branch enhances the damping of the system. During steady state, the virtual R-L branch offers negligible impedance which improves the voltages regulation of sources. It is observed in [26] that the effect of delay caused due to digital control, sampling and switching operation in current control loop of source converters may deteriorate the bandwidth of current control loop and stability margin of the system may decrease. While evaluating the performance of virtual impedance methods discussed in [24,25], the effect of delay is not considered. The delay may deteriorate the bandwidth of current control loop and stability margin of the system may decrease. To address this issue, a high frequency based virtual impedance based method is suggested in [26]. The suggested method improves band width of current control loop and stability margin of voltage control loop. However, the implementation of suggested virtual impedance method discussed in [26] requires additional current sensors. To keep the performance of the source converter intact, active damping techniques are used to modify input impedance of CPL in [27][28][29]. Similar to electronics loads, the electric motor drives operating in speed regulated mode exhibit constant power behaviour at the input of dc-bus [27,28]. In [27], negative input-resistance compensator is suggested to damp out oscillations in dc-link voltage during load transients in brushless dc motor drive. The controller reduces the value of dc-link capacitance required for stable operation of system. However, a trade off is observed between stability margin and load performance. Improvement in stability margin due to suggested controller is sacrificed at the cost of degradation in torque and speed response of motor drive. To reduce the coupling between the controller and torque and speed response of drive, a decoupled reference voltage-based active stabilization method is suggested in [28]. The suggested controller includes a simple and improved reference-voltage-based compensator (RVC) to compensate the negative impedance instability caused due to permanent magnet synchronous motor drive (PMSM). The simple RVC requires an extra current sensor used to sense dc-link capacitor current. To reduce the cost of system, improved RVC is used which requires sensing of dc-link voltage only. The suggested controller makes the operation of drive insensitive to the variation in dc-link capacitance. However, the effectiveness of the suggested controller is observed only for low speed PMSM drives. The deterioration in load performance of the drive may not be acceptable for certain loads [18,23]. Therefore, to improve the load performance, feedforward control based active damping technique is suggested in [29] which emulates virtual R-C branch at the input of CPL. This method enhances stability margin of the system and damp out oscillations caused due to CPL. However, the stability of the system is affected by the cut off frequency of first order low pass filter used in feedforward controller. The tuning of this filter requires the accurate knowledge of parameters of L-C filter. The methods suggested in [27][28][29] are based on input impedance shaping of CPL. Moreover, as the sources and CPL may be manufactured by different suppliers, practically it may be difficult to modify the controller of each source and CPL to ensure system stability. To resolve this issue, the best way to compensate CPL instability is to connect an external stabilizer in parallel with CPL. In [30], a positive smart resistor is emulated using active stabilization circuit (ASC) which successfully compensate negative impedance instability. The smart resistor reduces the size of dc-link capacitance and enhances fault endurance capability of the system. However, suggested method requires a separate ASC to be connected in parallel with each CPL. The cost of the system increases with increase in number of CPLs in the system. The reduction in dc-link capacitance is achieved at an additional cost of ASC.
To overcome the above-mentioned issues, simple design procedures for dc microgrid, with conventional sources and load controllers, are suggested in [15,[31][32][33][34]. These methods are based on establishing the stability conditions as functions of system parameters. In [31], the stability analysis of dc microgrid is studied using linearized reduced order model. In this study, it is established that droop gain should be less than the inverse of load conductance, to ensure stable operation of dc microgrid. However, the effect of the dc-link capacitor is not considered in the aforementioned study. Other possible methods to improve stability are addition in linear loads and curtailment of CPL [15]. However, these options are not generic and would not be viable for different dc systems. In [32], port Hamiltonian matrix method is used for electrical network connected with CPL and the necessary condition for the existence of equilibrium points is derived. However, the analysis for the stability of equilibrium points is not included. In [33], the condition for the existence of the equilibrium point and its stability for a dc network connected with CPLs is studied using linear matrix inequality (LMI). However, solving LMI for a dc microgrid having a large number of sources is computationally intensive. The approach discussed in [34], evaluates the capacitance value required for the stable operation of dc system. The value is determined based on the assumption that the system should be stable up to the loading, determined by maximum power transfer (Z line = complex conjugate Z load ). However, usually rated power capability of systems is much lower than the maximum power transfer and is limited by thermal and operational capabilities, therefore the solution determined in [34] would ensure stable operation, but is sub-optimal. In this situation, the suggested approach results in a large value of capacitance. Therefore, the capacitance value must be evaluated as per the power demand by CPL. This will result in a reduction in the cost of the system.
To address the aforementioned issues, a design approach is proposed in this manuscript, which determines the lower bound on the values of dc-link capacitance for the stable operation of the dc system with nonlinear CPL. The proposed approach considers the variation in power demanded by linear loads and therefore gives a solution applicable for all range of load variations. Lower bound on capacitance is deduced by evaluating the stable operating region. A minimum value of capacitance is obtained for rated power demanded by CPL. If the rated CPL demand is lower than the maximum load of the system, the proposed technique results in significant reduction in capacitance value. Using the proposed technique, the stepwise procedure for selection of capacitor in perspective of a low power dc system is included. Section 2 deals with the brief review of the problem and formulation of approach for evaluation of the stable region. The criteria for the selection of the minimum value of capacitance and design approach for a low power dc system are discussed in Section 3. Section 4 discusses the simulation results of a test system and its correlation with the analysis. Section 5 includes the controller hardware-in-loop (CHIL) results and Section 6 concludes the paper.

REVIEW OF [34] AND PROBLEM FORMULATION
This section gives a brief overview of the problem formulation. Further, the design approach of [34] and the reason for its conservativeness are discussed. Subsequent sections, utilize this problem formulation and discuss the proposed approach to determine the lower bound on the capacitance. A low power dc system shown in Figure 1 includes multiple sources and loads interfaced to a dc-bus through power electronic converters. Some of the sources (such as solar photovoltaics (PV)) operate under maximum power point tracking (MPPT) mode [35]. For constant atmospheric conditions, solar PV source behaves as a constant power source. In MPPT mode, the PV source injects constant power into the low power dc system for variation in dc-bus voltage [22,34,36]. Sources integrating storage (battery) would usually be controlled by the droop controller and would share the load power proportionally [37]. Figure 2(a) shows the constant power sources and droop controlled sources. The constant power sources can be combined with constant power loads such that the effective load power is the difference between the two values.
The output voltage of droop controlled sources is given by, where, v out j is the converter output voltage, V o j is the nominal voltage, i s j is the source current and d s j is the droop gain of j th source. The CPL is a nonlinear load and is modelled as voltagecontrolled current source [17,23,34]. The current drawn by j th Here, P CPL j represents the power drawn by j th CPL and v bus is the dc-bus voltage. It is assumed that, for each cable. All the droop controlled sources are represented by a Thevenin equivalent circuit, as shown in Figure 2(b). All the CPLs and constant power sources are combined and shown as a single CPL. The differential equations governing source current, i s and dc-link capacitor voltage, v bus are where, Here, P CPS j is the power generated by j th constant power source, R t j is the resistance and L t j is the inductance of j th interconnecting cable, R j is the resistance of j th linear load, P CPL j represents the power drawn by j th CPL and C j represents the dc-link capacitance in parallel with j th CPL connected at dc-bus. The elements P CPL , R and C represent the equivalent values of power demanded by CPL, linear load and dc-link capacitance corresponding to the circuit shown in Fig. 2 The equilibrium points are identified from (3) and (4) by equating di s ∕dt and dv bus ∕dt to zero. The two equilibrium points, e 1 and e 2 are given by [34], where, the value of q is given by the following expression: Here, I * s−1 , I * s−2 , V * bus−1 and V * bus−2 are the values of currents and voltages corresponding to equilibrium points e 1 and e 2 . Value of q must be non-negative for existence of real equilibrium points. This gives us a condition on P CPL , Typically, R (linear load resistance) is much higher than R d (Source Thevenin resistance including droop and cable resistance). Therefore, Since, R d is small, P max1 is usually much higher than the rated power of the system. This condition is usually satisfied in practical systems. Once the existence of equilibrium point(s) is ensured, the stability at the equilibrium points is evaluated as below. Equations (3) and (4) are linearized and represented in the state space form given below: where, V * bus−k is the value of the dc-bus voltage at the equilibrium point e k and ΔP is a small change in the CPL. The system matrix J k (also referred as Jacobian Matrix) evaluated at equilibrium points e 1 and e 2 is given by, (11) where, k = 1, 2. The determinant of J 1 is always negative, which implies that one of the eigenvalues would be negative and other would be positive. Thus, e 1 is an unstable equilibrium point. The determinant of J 2 is simplified to, Since det(J 2 ) is always positive, eigenvalues may be complex conjugate, both negative or both positive. To ensure that the real parts of the eigenvalues are negative, the trace of the matrix J 2 should be negative. Thus, As derived in [34], by substituting the value of V * bus−2 from (7) in (13) and rearranging, the following two cases are possible which guarantee the stability of e 2 .

Case-1:
The stability condition is given by, where, P max1 is defined in (9).

Case-2:
The stability condition is given by,

Existing Approach and Limitation
As discussed in [34], selection of capacitance based on case-2 restricts P CPL < P max2 , for stable operation. On the other hand for capacitance selection based on case-1, P CPL < P max1 , is required. Since P max1 is higher than P max2 , case-1 allows higher available range of P CPL . Therefore, in [34], case-1 is used, which gives the minimum value of capacitance as L d ∕R 2 d . However, for practical systems, the value of P max1 is much more than the rated power of the system. Therefore, case-2 is also a viable option for determining the value of capacitance. This case allows the selection of lower capacitance, required for stable operation of the system. Therefore, unlike [34], this paper focuses on case-2 and discusses the viability of case-2 and its associated challenges in the selection of dc-link capacitance and solutions in subsequent sections.

PROPOSED SELECTION METHOD
This section discusses the proposed approach for determining the value of capacitance for stable operation of the dc system. Section 3.1 discusses the variation in P max2 over the range of linear loads. This would provide the worst-case condition (minimum value of P max2 ). Further, it should be ensured that the operating P CPL should always be less than this worst-case P max2 . This is discussed in Section 3.2. This gives us a lower bound on the capacitance for stable operation of the system. In Section 3.3, steps for the determination of capacitance for a dc system are provided, which includes the relations derived in Sections 3.1 and 3.2.

Determination of P max2 over variation in linear load
Value of P max2 , given in (15), depends on system parameters (R d , L d , C ) and variable (linear load, R). With the operation of the system, as the linear load changes, R ∈ (R min , R max ), value of P max2 , also changes. The minimum value of P max2 , over the range of R is important, as it represents the worst case limit on P CPL , as shown in (15). To find the minimum value of P max2 , This gives a single solution for R, The value of d 2 P max2 ∕dR 2 is negative at R * , which indicates that P max2 achieves the maximum value at R * . Figure 3 shows the variation of P max2 , with R, for different cases. For the case R * < R min , the min{P max2 }, occurs at R = R max , and for case the R * > R max , the min{P max2 }, occurs at R = R min . Hence, the minimum value of P max2 , will occur at the boundary values of R (either at R min or R max ). Therefore, the value of R, at which the minimum value of P max2 occurs is given by, Replacing R with R cr in (15), the minimum values of P max2 is given by,

Evaluation of lower bound on capacitance
For stable operation of system, condition given in (15) must be satisfied for all operating conditions. Therefore, By substituting P max2 from (19) in (20) and rearranging gives, ). Roots of the quadratic equation (C ) are Using the expression for q, from (8) gives, This shows that the value of b 2 1 − 4b 0 , is non-negative and therefore the roots of (C ), are always real. Further, the value of b 1 , is evaluated by using the definition of q as, Since, b 1 , is always negative, at least one of the roots of (C ), would be positive and real. Figure 4 shows the plot of (C ) for sub-case (a), one of the roots (C 1 ) is negative and one positive (C 2 ) and, sub-case (b), both the roots (C 1 and C 2 ) are positive. These cases are further discussed below: Variation of (C ) with respect to variation in C for sub-case (a) and sub-case (b) Sub-case (a) (C 1 <0 and C 2 >0) The product of the roots (b o ) would be negative for this case. Therefore, for sub-case (a), the range of capacitance for stable operation starts from zero value of capacitance. Using the expression for b o , the inequality b o < 0, gives, Usually, the droop resistance R d would be much smaller then resistance of linear load (R cr ). Therefore, using R cr >> R d , the above expression becomes, The physical significance of above result is that if the value of P CPL becomes less than linear load demand (V 2 o ∕R cr ), the range of C would start from negative value, and therefore, the system would be stable even with zero capacitance. However, in realistic sense, the zero value of C means a very small value of C . The capacitance value cannot be zero as the analysis carried out in Section 2 of paper is valid only for non-zero value of dc-link capacitance. To keep the value of voltage ripples within a specified percentage of average value of dc-link voltage, a fixed minimum value of dc-link capacitance is still required [38,39].
If the power demanded by nonlinear CPL load is more than the power demanded by linear load, then both roots would become positive and is discussed in next case.

Sub-case (b) (C 1 > 0 and C 2 >0)
Here the lower bound on capacitance for stable operation is given by, As derived in appendix, the value of C 1 is less than L d ∕R 2 d . This shows that the lower bound for this case would be given by C 1 , which is less than L d ∕R 2 d . In summary, for P CPL less than the power of linear loads, the lower bound on capacitance for stable operation is zero, and in case of high penetration of CPL loads (P CPL > power of linear loads), low bound is given by C 1 , which is less than L d ∕R 2 d (lower bound given in [34]). This section determines the lower bound on capacitance value. Once the range of capacitance for stable operation is known, the viability of proposed approach for a dc system is explored in subsequent sub-section.

Capacitor Selection: System Perspective
This section discusses the selection of dc-link capacitor based on the expressions derived in the previous subsection. Typically, the load requirements are known. Using the composition of sources (solar PV and battery) and their locations would be determined based on available resources and technocommercial analysis. Subsequently, the interconnecting cables would be determined.

Design of interconnecting cable and droop gain
The interconnecting cable is selected based on the desired current carrying capacity and allowable voltage drop across it. As discussed in [40], the required power handling capacity of the cable is determined by, where, is the desired voltage regulation of the system, is the overloading margin, V o is the nominal system voltage, is the specific resistance at 80 • C, S is area of cross section and L is the length of the cable. Depending on the system voltage and power handling capacity, suitable cable is selected. Its parameters (R t , L t ) as specified in cable data sheet supplied by manufacturer, would be used for further design process.
To ensure proportional power sharing among sources, they are controlled using droop controllers. The value of droop gain d s depends on the source power capacity and value of voltage as discussed in [41].

Incorporation of tolerance limits
However, due to manufacturing imperfection and aging effect of capacitor, the capacitance value would be different from its nominal/designed value, which may affect local stability of equilibrium point [42,43]. Tolerance in the value of capacitance, is defined as the permissible relative deviation from its rated value.

FIGURE 5
Block diagram for selecting dc-link capacitance C in low power dc system The tolerance limit ± 1 % and 2 % represent the effect of manufacturing variations and the effect of aging, respectively. Corresponding to 1 % and 2 %, the modified nominal value of capac-itorC new , required for stable operation is, Incorporation of tolerance limits 1 % and 2 % compensates the effect of aging and manufacturing imperfection.
Once the system parameters are known, the design process, as shown in Figure 5 is followed: i Calculate the droop gains of sources using (29). Using droop gains of sources (d s ) and cable parameters (L t , R t ), determine the values of R d and L d using (5). Now the condition given by (9) on CPL power, gives the condition on the existence of equilibrium point e 2 . ii Check if power demand by nonlinear CPL is higher or lower than that of linear loads. If CPL power is lower than as discussed in section IIIC, minimum required capacitance is zero. Otherwise, use (27) to calculate the capacitance values

Other factors affecting dc-link capacitance
The boundary of value of dc-link capacitance, C selected from (27) ensures the stable operation of dc system with CPL. However, use of reduced value of C may lead to certain tech-nical issues in dc system which are discussed in brief in this section. The reduction in the value of dc-link capacitance may increase the magnitude of ripples in dc-link voltage [38,39,44]. Due to reduction in the value of dc-link capacitance, the necessary energy required to open the protective devices is not provided by the dc-link capacitance which may deteriorate the fault detection and fault clearance performance of protection schemes used in dc systems [15]. To resolve above mentioned issues arising due to use of reduced value of dc-link capacitance, a higher value of dc-link capacitance is selected.

Selection of DC-link Capacitance using Detailed Model of DC System
In Section 2, the simplified model of dc system given by (11) is used to select the lower bound on the value of dc-link capacitance. In this model, the sources used in the low power dc system are modelled as ideal sources. However, the actual sources are provided with inner current and voltage controllers in addition to droop controller. The dynamics of these controllers may affect the value of lower bound on the value of dc-link capacitance. In this section, the selection of dc-link capacitance using detailed model of dc system is discussed. Further, the effect of these models on the selection of lower bound of dc-link capacitance is discussed.

Detailed model of dc system
In this subsection, the value of C is evaluated using detailed model of low power dc system discussed in [24]. The low power dc system including sources and loads interconnected through cables is shown in Figure 6. Each source is connected to the dc-bus through bidirectional dc-dc boost converter as shown in Figure 6. The dynamical equations of j th boost converter are where, V b j is the source input voltage, i Ls j is the inductor current and d j is the duty cycle of j th dc-dc boost converter, respectively. The elements, L Ls j and R Ls j are inductance and resistance of input inductor coil and C s j is the value of capacitance connected at the output of boost converter. The control scheme of j th dc-dc boost converter is shown in Figure 7. The linear PI controllers are used to minimize error between the reference and actual quantity in voltage and current control loops. From the control scheme shown in Figure 7 for closed loop dc- where, K pv j and K iv j are proportional and integral gains of PI controller used in voltage control loop and K pc j and K ic j are proportional and integral gains of PI controller used in current control loop of j th dc-dc boost converter. Here, v j is the output of voltage controller, c j is the output of current controller and i ref j is the reference value of inductor current of dc-dc boost converter. Using (34) and (35), the expression for duty cycle, d j is given by, (32), (33), (34), (35) and (36) and simplifying, the small signal model of j th source converter is given by, where, the state vector,

The value of system matrix
A c j of j th converter is given by (38) in which, V o and I Ls j are output voltage and inductor current corresponding to the operating point (V o , I Ls j ) of j th source converter.
Writing (37) for n-sources connected in dc system, where, the state vector, T . Now assuming that, R t 1 ∕L t 1 = R t 2 ∕L t 2 = ⋯ R tn ∕L tn = R t ∕L t , for each cable, the total source current, i s is expressed as According to simplified model discussed in Section 2, all the CPLs and constant power sources are combined and represented as a single CPL. The dynamics of dc-bus voltage are represented in (4). In case of schematic of dc system shown in Figure 6, the differential equations governing dc-bus voltage, v bus is The meaning of symbols used in above relation are defined in Section 2. Linearizing above and writing in matrix form, Δ̇v bus = A bus Δx c + B bus Δv bus (42) where, A bus = ). To check the stability of the dc system, the linearized small signal model of dc system is required. For this purpose, the state equations given by (39) and (42) are converted into standard state space form given below. (43) where, the state vector, Δx = [Δx T c Δv bus ] T and the value of system matrix, A of low power dc system is given by,

Δẋ = AΔx
The small signal model represented by (43) represents the detailed model of dc system including dynamics of source converters and their controllers, interconnecting cables and loads.

Selection of dc-link capacitance
The theoretical value of dc-link capacitance required to ensure stable operation of dc system about the stable equilibrium point is evaluated from eigenvalues root loci plots. For this purpose, the eigenvalues of the dc system are determined using (43). For a given value of P CPL , the value of C is set to zero value. If any of the eigenvalue is in Right Half Plane (RHP), then gradually increase the value of C such that all the eigenvalues come to lie in the Left Hand Plane (LHP) from RHP. This is the minimum value of C required for the given value of P CPL . The same procedure is adopted for other values of P CPL .

STUDY OF A TEST SYSTEM
In this section, the procedure for evaluating dc-link capacitance is used for a test case system. The selection of dc-link

Configuration of Test Model
The test system has two sources connected to the dc-bus using dc-dc boost converters, one CPL and one linear load, as shown in Figure 8. System parameters are given in Table 1 and cable parameters are given in Table 2. The value of droop gain d s of each source is set to 0.15 V/A for the value of voltage regulation  Figure 9 shows the plot of P max1 and P max2 corresponding to R cr = R min = 20 Ω with variation in the values of C . For C = L d ∕R 2 d , the value of P max1 is equal to P max2 . The region located below the P max1 curve is the region of existence of equilibrium point. The region located below the curve P max2 is the region of stability of equilibrium point e 2 . The value of P max1 | R=20Ω is 312 kW. The point of intersection of P max2 and P CPL gives the value of C required for stabilization of dc system. In the simulation study, two cases are considered. In one case, the value of power demanded by CPL, P CPL , is less than the value of rated linear load demand (P R ), as shown in Figure 9(a). In the other case, the power demanded by CPL, is more than the rated linear power, as shown in Figure 9(b). In case-a, the value of linear load demand is P R = 8 kW. The point Q shown in zoomed portion of Figure 9(a), represents the value of P CPL which requires zero value of C for stabilization of dc system. The value of P CPL corresponding to point Q is calculated from (25). The value of P CPLQ for the parameters given in Table 1 is 7.8 kW which is nearly equal to P Rmin = 8 kW. However, the value of P CPL1 is 3 kW. The value of C required for stabilization lies on negative side of C-axis. This can be seen in the zoomed portion of Figure 9(a). This implies that for P CPL < P CPLQ , system would be stable for any positive value of capacitance.

Region of existence and stability of equilibrium points
In case-(b), the rated value of P CPL2 is 90 kW. The P CPL , is more than the rated linear power P R , therefor the minimum capacitance required for stable operation is given by C min = 0.60 mF . As shown in Figure 9(b), the value of P max1 is much higher than the P CPL and P R and therefore, there is no need to restrict capacitance value above L d ∕R 2 d . The proposed technique results in significant reduction in the value of C . The points of intersection of P CPL and P max2 , gives the value of C 1 as shown in Figure 9

Selection of C using simplified model
In this section, the value of C is evaluated for the case, P CPL > P R using simplified model discussed in Sections 3.1, 3.2 and 3.3. Analytically, for the given range of R, the value of C is evaluated using (27). The value of C 1 | R max , is calculated as 0.60 mF whereas C 1 | R min is 0.58 mF. The value, max{0.58 mF, 0.60 mF} = 0.60 mF, is the minimum value of capacitance required for stable operation of the system for all range of linear and CPL loads. This proves the effectiveness of the proposed methodology, which provide lower bound on capacitance for stable operation of the system. Figure 10 shows the variation of P max2 with respect to variation in C 1 for the system parameters given in Table 1. The

FIGURE 9
Effect of variation of C on P max1 and P max2 for case (a) and case (b)

FIGURE 10
Graph of C − P max2 to select C 1 for a given value of constant power load demand P CPL expression for P max2 is given by (15). The point of intersection of P max2 and P CPL gives the value of C required for stabilization of dc system. For a constant load power demand P CPL1 = 90 kW , the minimum value of C 1 is 0.60 mF. The horizontal line (red colour) shows the selected value of C 1 using the approach suggested in [34], which gives the value of C 1 = L d R 2 d = 7.30 mF. From the graph, it is clear that there is significant reduction in the value of C , if the value of P CPL is smaller than P max1 .

Selection of C using Detailed Model
In Section 4.2, the value of dc-link capacitance is selected for the parameters of a low power dc system given in Table 1. The value of C is selected using simplified modeling discussed in Sections 3.1, 3.2 and 3.3. In this subsection, the value of C is evaluated using detailed model discussed in Section 3.4 for the parameters of low power system given in Table 1.
To determine the value of C using detailed model of dc system, root loci plot for dominant eigenvalues given in Figure 11  is determined using (43). The value of constant load power demand is maintained at P CPL = 90 kW and linear load demand, P Rmax = 4 kW. The initial value of C is set to 10 F. The value of C is gradually increased in small steps. It is observed in Figure 11 that with increase in the value of C , eigenvalues starts moving towards the LHP. For a threshold value of C 1 = 0.52 mF, all the dominant eigenvalues migrate from RHP into the LHP. This threshold value of C 1 = 0.52 mF is regarded as the desired value of dc-link capacitance required to ensure the stable operation of dc system about the equilibrium point for P CPL = 90 kW. The same procedure is repeated to determine desired values of C for other values of P CPL using detailed model of dc system.
In the above mentioned case, the value of C 1 is evaluated using detailed model for a dc system having capacity of 100 kW and rated CPL demand P CPL = 90 kW. Adopting the above mentioned procedure, the value of C 1 for other dc systems can be determined. As discussed in section 4.3, the Figure 10 shows the variation of P max2 with respect to variation in C 1 for the system parameters given in Table 1. The point of intersection of P max2 and P CPL gives the desired value of C required for stabilization of dc system using simplified model. Using detailed model, the desired value of C required for a given P CPL is mentioned above. The values of dc-link capacitances required for given values of constant load demands using the two models of dc system are plotted in Figure 12. For a rated constant load power demand P CPL = 90 kW, the minimum value of C 1 required using simplified and detailed models are 0.60 and 0.52 mF, respectively. From Figure 12, it is observed that the values of C 1 determined using simplified and detailed model of dc system are in close agreement. This justifies the use of simplified model to evaluate the desired value of C required to ensure stable operation of dc system for a specified value of rated CPL demand.

FIGURE 12
Graph of C − P CPL to select C 1 using simplified and detailed model

Simulation results
To validate the results in matlab/simulink, the simulation study of the system shown in Figure 8, is carried out. The parameters of the dc system are given in Table 1 of this manuscript.
Depending upon the value of dc-link capacitance C 1 , the following Matlab/Simulink results are included for capacitance value less than and more than its lower bound.

P CPL < P R and C 1 < C min
In this case, the constant load power demand, P CPL is maintained at a value which is less than the power demanded by linear load. The value of P CPL is 3 kW and the value of P Rmax is 4 kW. At t = 1 s, the step variation in linear load demand P R from 4 to 8 kW is applied. The value of dc-link capacitance, C connected at the input of CPL is 20 F. The Figure 13 shows the waveforms of current supplied by source-1, source-2 and dc-bus voltage. From the waveform as shown in Figure 13, the operation of dc system remains stable. From these waveforms, it is clear that a stable operation of dc system is observed even for small value of C , which validates the findings discussed in Section 3.

P CPL > P R and C 1 < C min
In this case, the rated value of P CPL is 90 kW. The minimum value of C 1 required for stabilization dc system is 0.60 mF. The initial value of P CPL demanded by buck converter connected at the dc-bus is 60 kW. The dc-link capacitance having value of C 1 = 0.40 mF is connected at input of buck converter. As the linearized model of the converter is valid for small perturbations in load variations, therefore the constant power demand is gradually increased using variable resistance R L connected at the output of buck converter. Figure 14(a) shows the waveforms

FIGURE 13
Simulation results for sources having equal power ratings. Source currents, dc-bus voltage, power consumed by constant power load (CPL) and power consumed by linear load for P Rmin = 8 kW: (Current: 20 A/div, voltage: 200 V/div, power: 5 kW/div and time-axis: 50 ms/div). Waveforms of currents supplied by source-1 and source-2, dc-bus voltage, power consumed by CPL and power consumed by linear load with C = 20 F of current supplied by source-1 and source-2 interfaced to the dc-bus through dc-dc boost converters, dc-link voltage v bus and power demanded by CPL. The linear load demand is maintained at P R min = 8 kW. A step variation in P CPL from 60 kW to 70 kW is applied at t = 1 s. As shown in Figure 14(a), oscillations appears in i s1 and i s2 , which increase without bounds and the operation of the dc system becomes unstable for C 1 < C min .

P CPL > P R and C 1 > C min
Now the value of C 1 is changed from C 1 = 0.40 mF to C 2 = 0.80 mF. The Figure 14(b) shows the waveforms of currents supplied by source-1, source-2, dc-link voltage v bus and power consumed by CPL. From the responses of i s1 , i s2 , v bus and P CPL , the stable operation of dc system is observed for C 1 > C min .

(P CPL > P R and
Now the operation of dc system is observed with value of C 1 = R d ∕L 2 d . The Figure 15 shows the operation of the dc system with value of C 1 = R d ∕L 2 d = 7.30 mF. The Figure 15 shows the waveforms of current supplied by source-1 and source-2, dclink voltage v bus and power demanded by CPL, P CPL . The linear load demand is maintained at P R min = 8 kW. A step variation in P CPL from 60 to 70 kW is applied at t = 1 s. The operation of dc system remains stable. From Figs. 14(b) and Figs. 15, it is observed that the responses of dc system remains stable even for lower values of C if dc-link capacitance is selected as per the CPL demand rather than selecting C according to the method discussed in [34]. This validates the findings discussed in Section 3.

4.6
Evaluation of C 1 for sources having unequal ratings The approach used to evaluate the value of dc-link voltage is applicable to the system including multiple sources of either equal or unequal ratings as discussed in Section 2. The analysis for the evaluation of value of C remains same. From (5), the unequal values of droop gains of sources modify the average value of droop gain d s which leads to modification in the value of effective droop gain R d of Thevenin's source. From (27), the minimum value of capacitance required for stable the operation is determined.
To validate the results, the simulation study of the low power dc system having two sources of unequal ratings as shown in The Figure 8, is carried out. The rating of source-1 is 70 kW, and that of source-2 is 30 kW. The cables used to connect the sources to the dc-bus are same as the previous case. The droop gain of source-1 is 0.109 V/A and that of source-2 is 0.253 V/A. For these values of droop gains, the value of C evaluated using (27) to stabilize the operation of dc system against P CPL = 60 kW and P CPL = 90 kW are 0.30 and 0.50 mF. The initial value of P CPL demanded by buck converter connected at the dc-bus is 60 kW. The dc-link capacitance having value of C = 0.40 mF is connected at input of buck converter. The Figure 16(a) shows the waveforms of current supplied by source-1, source-2 and dc-link voltage v bus for C = 0.40 mF. The linear load demand is maintained at P Rmin = 8 kW. From the waveforms of the currents i s1 and i s2 , supplied by source-1 and source-2, it is observed that the operation of dc system becomes unstable for a step variation in P CPL from 60 to 70 kW applied at t = 1 s. The Figure 16(b) shows the waveforms of current supplied by source-1, source-2 and dc-bus voltage v bus for C = 0.80 mF. From the waveforms of the currents i s1 and i s2 , stable operation of dc system is observed for the step variation in P CPL from 60 to 70 kW.

CHIL BASED STUDIES AND VALIDATION
This section discusses the CHIL realization using realtime digital simulator (RTDS) and Texas Instruments made TMS320F28335, digital signal processor (DSP). The Figure 17 shows the overall scheme, implemented for this study. The parameters of source converter and CPL are given in Table 1. Each source and CPL is a dc-dc boost and buck converter along  with inner voltage and current controllers as shown in Figure 8. The values of droop gains of boost converter, cable parameters and the dc-link capacitance are identical to those considered in previous section. The giga-transceiver analogue output and giga-transceiver digital input cards are used to interface the DSP (which includes controller for source and load converters) with RTDS (which includes the dc system and converters).
Depending upon the value of dc-link capacitance C 1 , the CHIL results are considered for the following two cases.

5.1
Case-a (P CPL < P R ) In this case, the value of resistive load demand is more than the nonlinear CPL demand. As discussed in Section 3, for this case the stabilized operation of dc system can be achieved, even with very small value of C . For this case, C having small value of 10 F is connected at the input of CPL. The value of P CPL is 3 kW and the value of P Rmax is 4 kW. At t=70 ms, the step variation in linear load demand P R from 4 to 8 kW is applied. The Figure 18 shows the waveforms of current supplied by source-1, source-2 and dc-bus voltage. From the waveform as shown in Figure 18, the operation of dc system remains stable.

Case-b (P CPL > P R )
This case is further subdivided into three cases.

5.2.1
Case-b1 (P CPL > P R and C 1 < C min ) In this case, the CPL demand is maintained more than the linear load demand. The rated value of P CPL is 90 kW. The minimum value of C 1 required for stabilization dc system is 0.60 mF. The initial value of P CPL demanded by buck converter connected at the dc-bus is 60 kW. The dc-link capacitance having value of shows the waveforms of current supplied by source-1, source-2 and dc-link voltage, v bus by maintaining the linear load demand of P Rmax = 4 kW. A step variation in P CPL from 60 to 90 kW is applied at t = 70 ms. As shown in Figure 19(a), the oscillations having large magnitude appear in the responses of i s1 , i s2 and v bus , and the operation of the dc system becomes unstable. Now the linear load demand is changed from P Rmax = 4 kW to P Rmin = 8 kW. The Figure 19(b) shows the waveforms

5.2.2
Case-b2 (P CPL > P R and C 1 > C min ) Figs. 20(a) and 20(b) shows the waveforms of i s1 , i s2 and v bus for P Rmax = 4 kW and P Rmin = 8 kW, respectively. The value of C 1 connected at the input of buck converter is 0.80 mF. A step variation in P CPL from 80 to 90 kW is applied at t = 70 ms. As shown in Figure 20(a), damped oscillations appears in responses of i s1 and i s2 . Due to increase in linear load demand P R from 4 to 8 kW, oscillations are visible in i s1 and i s2 , as shown in Figure 20(b). From the Figs. 20(a) and 20(b), the stable operation of dc system is observed for the value of C 1 = 0.80 mF.

5.2.3
Case-b3 (P CPL > P R and C 1 = , it is clear that the operation of low power dc system is stable even with smaller values of dc-link capacitor selected using proposed approach and does not require large capacitance as discussed in [34].

CONCLUSIONS
In this paper, a novel approach is proposed for the design of a low power dc system interfaced with nonlinear CPLs and resistive loads. The proposed approach helps in selecting the value of dc-link capacitance as per the CPL demand of the system. In the case where the CPL demand is greater than linear load, there exists a lower bound on the value of dc-link capacitance above which the stable operation is guaranteed. If the CPL demand is less than the linear load demand, the stable operation of low power dc system is observed even with very small value of dclink capacitance. From the proposed approach, it is concluded that the stable operation of dc system is possible even with smaller values of dc-link capacitance and does not require large dc-link capacitance as discussed in the literature. The selection of capacitance for a low power dc system is also discussed in this paper. The value of capacitor, determined from the proposed methodology is validated using CHIL based setup. From the results included in Section 5, it is verified that the proposed method results in a significant reduction in the value of capacitance. Since q is non-negative quantity, the inequality (33) is true. Therefore the inequality given by (31) is also true. From above analysis, it is inferred that, C 1 < L d ∕R 2 d holds.