Design and DC fault clearance of modiﬁed hybrid MMC with low proportion of full-bridge submodules

The hybrid modular multilevel converter (MMC) consisting of half bridge submodules (HBSMs) and full bridge submodules (FBSMs) combines the respective advantages of both submodules. In order to further reduce the manufacture cost and power loss, this paper proposed a modiﬁed hybrid MMC with lower proportion of FBSMs than the conventional hybrid MMC. First, three main conditions for successful DC fault clearing of the hybrid MMC are analysed, which are: (1) Blocking AC fault current; (2) suppression of DC fault current; (3) capacitor voltage under threshold value. Then the topology and the DC fault clearing strategy of the proposed modiﬁed hybrid MMC are introduced. Since the installed AC current blocking switches (ACBSs) block the AC current feed during the fault, the number of FBSMs is only limited by third condition. Furthermore, the maximum capacitor voltage after the DC fault is analysed to obtain the minimum required number of FBSMs. Finally, the DC fault responses of the modiﬁed hybrid MMC are compared with the conventional hybrid MMC in a three-terminal MMC-HVDC test system in PSCAD/EMTDC. Simulation results demonstrate the effectiveness and feasibility of the proposed modiﬁed hybrid MMC.


INTRODUCTION
In recent years, with the development of power electronic technology, the modular multilevel converter based high-voltage direct current (MMC-HVDC) system has drawn great attention from both the industry and academia [1][2][3]. Due to the advantages of decoupled control of active and reactive powers, no risk of commutation failure and low harmonics, MMC is expected to be widely used in long distance overhead line transmission as an alternative to the line commutated converter (LCC) [4][5][6]. In addition, MMC is more suitable for multi-terminal HVDC (MTDC) systems than LCC, since the DC power flow can be reversed by changing current direction instead of voltage polarity. Up till now, there have been several multi-terminal MMC-HVDC projects in China, such as the Kunliulong project and the Zhangbei project [7,8].
However, DC fault clearance is still a major challenge for MMC-HVDC systems. Theoretically, there are mainly three methods to clear DC fault in MMC-HVDC systems.
1. Tripping AC circuit breakers (CBs). In most of the early MMC-HVDC projects, due to economic and technical constraints, DC line faults are cleared by tripping ACCB. This method will take a long time to resume the active power transmission from DC line faults, and will cause transient AC voltage drop, which may influence the stability of the connected AC systems [9]. Therefore, this method is mainly applied in the projects that use cable as DC transmission line, such as offshore wind power transmission projects. 2. Using HVDC circuit breakers. After the first announcement of the hybrid HVDC CB by ABB in 2012 [10], with the maturity of technology, using DCCB has gradually become one of the mainstream DC fault handling methods for MMC based MTDC systems. It is also applied in the Zhangbei four-terminal MMC-HVDC project [8]. The main disadvantage of the DCCB is the high manufacture cost, which will increase geometrically with the increase of DC grid complexity.
3. Adopting MMCs with DC fault blocking capability. By replacing the half bridge submodules (HBSMs) with the submodules with DC fault blocking capability such as full bridge submodules (FBSMs) and clamp double submodules (CDSMs), the DC fault can be cleared by blocking MMC [11][12][13][14]. This method is also applied in the Kunliulong threeterminal MMC-HVDC project. The main disadvantage is that all MMC stations need to be blocked during the DC fault, which makes this method not suitable for the largescale DC grid [15].
For the MTDC systems with small number of terminals, adopting MMCs with DC fault blocking capability is an economical and effective method to deal with DC fault [15]. Among these SMs with DC fault blocking capability, FBSMs can output negative voltage to enable MMC to work under a wider range of DC voltage. However, FBSMs will also increase the manufacturing cost and operation loss of MMC-HVDC since it uses twice as much power electronic devices as HBSMs. In order to reduce the cost while retaining the advantages of FBSMs, the hybrid MMC with mixed HBSMs and FBSMs has been proposed [16][17][18][19][20][21]. The modulation and capacitor voltage balancing method of the hybrid MMC are discussed in [16]. In [17,18], the required number of FBSMs in the hybrid MMC is calculated to ensure successful DC fault blocking and capacitor voltage balancing. Ref. [19] studies the precharging process of the hybrid MMC. The transient DC fault ride-through strategies for hybrid MMC without blocking the converter are studied in [19][20][21].
However, there are mainly two deficiencies in the existed research. The first is that in most of the above studies, the minimum proportion of FBSMs required for successful DC fault blocking or DC fault ride-through is greater than 50%. And there are few researches on how to reduce the required number of FBSMs. The second is that when designing the minimum proportion of FBSMs, it is not included in the condition that the maximum capacitor voltage during fault cannot exceed the threshold value during the fault.
To overcome the aforementioned deficiencies, a modified hybrid MMC consisting of mixed HBSMs and FBSMs is proposed in this paper. By installing AC current blocking switches (ACBSs) in stat connection on the AC side, the proposed modified hybrid MMC can effectively clear DC faults using fewer FBSMs than the conventional hybrid MMC. The capacitor voltage of FBSMs after fault is also analysed in two stages: before and after blocking. Then a calculation method for required FBSMs proportion is proposed and the relationship between the FBSMs proportion and DC line length is analysed. It is found that when the DC line is short, the required FBSMs proportion is much less than 50%, while when the DC line length exceeds a certain value, the required FBSMs proportion will be more than 50%, but still less than that of the conventional hybrid MMC.
The outline of this paper is as follows: Section 2 introduces the operation principle and DC fault clearing conditions of the hybrid MMC. Section 3 introduces the topology and DC fault clearing strategy of the proposed modified hybrid MMC. In Section 4, the maximum capacitor voltage during DC fault is Equivalent circuit of arm after blocking estimated by analyzing the equivalent circuit of the modified hybrid MMC before and after blocking. And the minimum required FBSMs proportion is calculated. In Section 5, the fault clearing capability of the modified hybrid MMC is verified in a three-terminal MMC-HVDC test system in PSCAD/EMTDC. The conclusions are given in Section 6. Figure 1(a) shows the basic structure of a three-phase hybrid MMC. The converter consists of six arms, each having a series connection of an arm inductor L 0 and N total submodules, including N HB HBSMS and N FB FBSMs as shown in Figure 1(b). U dc denotes the dc-bus voltage and I dc denotes the dc line current. The arm voltage and the arm current are u rj (r = p, n denotes the upper and lower arms; j = a, b, c denotes the three phases a, b, c) and i rj respectively. u vj denotes the ac-side phase to ground voltage of phase j. i vj denotes the ac-side current.

OPERATION PRINCIPLE AND DC FAULT CLEARING CONDITIONS OF HYBRID MMC
The blocked FBSMs can provide reverse electromotive forces (EMF) regardless of the current direction to block the current flow. The equivalent circuit of arm in different current direction after blocking can be obtained as shown in Figure 2. For first condition, the hybrid MMC is required to provide sufficient reverse EMF in the AC current feed path. Figure 3 shows two typical AC current feed paths after blocking. And the reverse EMF in both paths should be greater than the peak line-to-line AC voltage during the DC fault [17]. The conditions for blocking path 1 and path 2 can be expressed as Equations (1) and (2) respectively.
where, U cn denotes the rated voltage of SM capacitor and U vm denotes the amplitude of u vj . According to Equations (1) and (2), the required number of FBSM can be expressed as: where, m is the ac-side modulation index and can be expressed as: For second condition, according to the direction of the fault current and the equivalent circuit of arms in Figure 2, the DC side circuit of the hybrid MMC after blocking can be obtained as shown in Figure 4(a). R dc and L dc include the resistance and inductance of smoothing reactor and DC line. R 0 represents the equivalent resistance in each arm. The DC side circuit of the blocked hybrid MMC can be further simplified to the equivalent circuit shown in Figure 4(b). Assuming that the DC voltage and fault current is U dcB and I dcB respectively at MMC blocking moment, the operational circuit of the blocked hybrid MMC can be obtained as shown in Figure 4 The Laplace inverse transform of Equation (5) yields: where, dc = arctan ( dc dc ) According to Equation (6), DC-side fault current i dc (t) consists of two components. One is the continuous current of inductor charging the capacitor. Another is the capacitor discharge current in the opposite direction of the fault current. As a result, the DC-side fault current would drop to zero rapidly and remain at zero due to the unidirectional conduction characteristics of the diode. Therefore, the hybrid MMC can always meet the second condition, no matter what the proportion of FBSMs is. Besides, it should be noted from Equation (8) that the time constant will be influenced by the fault circuit inductance L dc and the fault circuit resistance R dc , which change with the length of the DC line from the fault point to the converter station. In addition to the aforementioned two conditions, the hybrid MMC should also ensure that the SM capacitor voltage does not exceed the threshold value set by the protection system after blocking.

MODIFIED HYBRID MMC
According to the analysis in Section II, the proportion of FBSMs in the conventional hybrid MMC is mainly limited by the first condition. According to Equation (3), the proportion of FBSMs should be greater than 43% when m equals 1. However, the proportion required by the second condition is much lower than this value. According to [13], the power loss of the full-bridge MMC in normal operation is 38% more than that of the half-bridge MMC. While the power loss of the hybrid MMC with 40% FBSM is 16% more than that of the half-bridge MMC. Therefore, the power loss of the hybrid MMC is slightly higher than that of the half-bridge MMC and the extra power loss is approximately linear with the proportion of FBSMs. Therefore, in order to reduce the required proportion of FBSMs in hybrid MMC, this paper proposed a modified hybrid MMC, which only need to meet the second condition and third condition for successful DC fault clearance. This section first introduces the structure of the modified hybrid MMC. Then the corresponding DC fault clearance strategy is presented.

Topology of modified hybrid MMC
The structure of the modified hybrid MMC is shown in Figure 5. The arm of the modified hybrid MMC is still composed of N total SMs and an arm inductor in series, while the number of FBSMs N FB is reduced. Different from the structure shown in Figure 1, the intersection of upper arm and lower arm in each phase is connected through three AC Current Blocking Switches (ACBSs) in star connection. These ACBSs always remain open in steady state. After the fault occurs, ACBSs are asked to close immediately to block the AC current. In order to guarantee the operation speed of ACBSs, the thyristors which are durable and economical are employed to compose the ACBSs as shown in Figure 5. Then both of the closing time and disconnecting time of the ACBSs can be within 1 ms. In addition, the ultra-fast disconnector (UFD) is installed on the DC side to isolate the faulty line. When the DC fault occurs, a three-phase short-circuit can be actively applied at the AC-side of hybrid MMC by close all ACBSs after blocking. Then the AC current feed would be blocked at point M according to the equivalent circuit of the modified hybrid MMC after blocking shown in Figure 6. Therefore, the first condition mentioned in Section II would always hold. And the number of FBSMs N FB no longer needs to satisfy Equation (3). The UFD is mainly used to isolate the faulty line immediately after the fault current drops to zero, then the ACBSs can tripped as soon as possible to remove the threephase short circuit.
In addition, compared with the conventional hybrid MMC, energy charged into FBSM capacitors after blocking is also reduced because the energy from the AC system is blocked. So the maximum FBSM capacitor voltage of modified hybrid MMC during DC fault is lower than the conventional one with the same number of FBSM. Therefore, the number of FBSMs in the modified hybrid MMC can be reduced without affect the DC fault clearance capability.

Strategy of DC fault clearance
Take a positive DC line-to-ground fault as an example, the detailed DC fault clearance strategy of the modified hybrid MMC is as follows: 1.
Step 1: The DC line-to-fault occurs at t 0 . With the rapid rise of the fault current, maximum arm currents of six arms exceeds the threshold value (2 times of the rated current of the IGBT) at t 1 . Then the hybrid MMC is blocked immediately. And ACBSs are closed to apply a three-phase short circuit at AC side after the converter is blocked. Since the time delay of converter blocking is very short, both operations can be considered to be applied at t 1 . After that, the AC current into the MMC drops to zero and the fault current only includes the DC-side component expressed in Equation (6). 2.
Step 2: The fault current drops to zero and the open signal is sent to the UFD at t 2 to isolate the faulty line. After a short delay, the UFD fully opens at t 3 . By now, the physical isolation between the converter and the faulty line is realized and it is no longer necessary to block the AC current feed. Then the tripping signal is send to the ACBSs. 3.
Step 3: At t 4 , all ACBSs in the converter are completely tripped and the state of three-phase short-circuit is removed. The DC-fault clearance is completed and the AC system returns to steady state operation at t 5 .
In the whole process of fault clearance shown in Figure 7, a three-phase short-circuit fault is actively applied at AC-side in the period from t 1 to t 4 . In order to ensure that the stability of the AC system will not be affected, it is necessary to estimate the existence time of three-phase short circuit T short .
According to Equation (11), T short consists of three components: the time for fault current to drop to zero T tozero , the time delay for UFD to open T UFD and the time delay for ACBS to open T ACBS . Among them, T UFD is approximately 2 ms according to [22]. T tozero can be eliminated according to Equation (6). Fault current i dc (t) consists of a positive component and a negative component. Obviously, the time for the positive component to drop to zero is larger than T tozero . But it can still be used to make a conservative estimate of T tozero as shown in Equation (12). According to the simulation results in [23] and the estima- tion results based on the parameters of the practical engineering, T tozero is smaller than 10 ms in most cases.
T tozero < dc dc (12) As for T ACBS , it mainly represented the time delay from receiving the tripping signal until the current flowing through ACBSs dropping to zero. Assuming that the AC system frequency is 50 Hz, the maximum value of T ACBS is 10 ms. According to the above calculations, the existence time of three-phase short circuit T short would not exceed 22 ms, which is acceptable for most AC systems. Therefore, the proposed DC fault clearance strategy would not affect the stability of the AC system.
In the case of multi-terminal system, it is necessary to use the selective protection to obtain the fault location. Therefore, in addition to the fault clearing strategy introduced above, the following coordination strategies are also needed.

ANALYSIS OF CAPACITOR VOLTAGE
Different from the conventional hybrid MMC, the minimum number of FBSMs in the modified hybrid MMC is only limited by the capacitor voltage during fault clearance. In order to minimize the device cost, it is necessary to estimate the maximum capacitor voltage during the fault. The analysis of the capacitor voltage is applied on the modified hybrid MMC before and after blocking respectively.

Capacitor voltage before blocking
After the DC fault occurs until the MMC is blocked, the number of inserted SMs in each arm still changes according to the control system. Take the upper arm of phase A as an example, assuming that the capacitor voltage at the moment of fault is u c0,pa , then the capacitor voltage before blocking can be expressed as: S pa (t) denotes the average switching function. Because the time period before blocking is sufficiently short, the expression of S pa (t) remains the same as in steady state: The arm current i pa (t) consists of AC side current and DC side current and can be expressed as: In the calculation, the change rules of the AC side current i va (t) is considered as before the fault. While the expression of the i dc (t) before blocking can be obtained according to [23]: where, I dc is the DC current before the fault occurs, and dc0 = arctan( dc0 dc0 ) According to Equations (13)- (17), the capacitor voltage at the moment of blocking can be expressed as: where, u cst,pa denotes the steady state component and u ctr,pa denotes the transient component of capacitor voltage. According to Equation (22), u cst,pa is same as the expression of the capacitor voltage under steady state [24]. In most MMC projects, the maximum capacitor voltage ripple in steady state is limited to 10% of rated capacitor voltage. Therefore, the following inequality can be obtained: The maximum value of u ctr,pa can be estimated as follows: Substituting Equation (17) into Equation (24), the expression can be obtained as follows: where, Substituting Equations (23) and (25) into Equation (22), the maximum value of u c1,pa can be estimated as follows:

Capacitor voltage after blocking
After the modified hybrid MMC is blocked, the DC-side equivalent circuit is shown in Figure 4. Since the AC current feed is blocked due to ACBSs and the energy consumed by the resistor is negligible, the energy in the DC-side circuit is almost conserved. It can be used to calculate the final value of capacitor voltage after blocking. Assuming that the energy is evenly distributed among the six arms, the final value of capacitor voltage can be calculated as follow: (28) where, u c2,pa denotes the final capacitor voltage, and Substituting Equation (29) into Equation (28), the following relationship can be obtained: (30) where, I vm denotes the amplitude value of the AC-side current in steady state.
According to Equation (30), the final rise of capacitor voltage is mainly related to |i dc (t 1 )|, which is the absolute value of fault current at the moment of blocking. Therefore, it is necessary to calculate the maximum value of fault current before blocking. The arm current can be divided into AC component and DC component, and the expression can be rewrite as: For different arm, the phase angles of AC components differ by 60 • in turn: According to the properties of sine function, the minimum value of sine value of six angles which increase by 60 degrees in turn will always be less than sin(−π/3). Therefore, it can be obtained from Equation (32) that: Because the condition of blocking is that one of the six arm currents exceeds the threshold value |I blk |, the maximum value of |i dc (t 1 )| at the moment of blocking can be expressed as: Substituting Equation (34) into Equation (30), the maximum value of u c2,pa can be obtained. It is also the maximum value of the capacitor voltage which should be limited under the threshold value (1.4× of U cn in this paper) when setting N FB .

Calculation of required FBSM proportion
According to the aforementioned analysis, the minimum required proportion of FBSMs K FB,min in the modified hybrid MMC can be calculated as: It can be seen from Equation (35) that in addition to the MMC parameters, the minimum proportion is also related to the fault circuit inductance and resistance. Therefore, the required proportion of FBSMs will change with the DC line length. And the fault resistance is also included in the fault circuit resistance R dc . According to Equation (35), R dc can only indirectly influence K FB,min by affect u c1,pa . And the change of fault resistance has little effect on u c1,pa . Therefore, the effect of fault resistance on K FB,min is negligible. The detailed calculation steps of K FB,min are as follows: Take the 500 kV/3000 MW MMC station as an example, the 4.5 kV/3kA IGBTs are used in all SMs. The main parameters are listed in Table 1. The rated value and threshold value of capacitor voltage are 2.2 and 3.08 kV respectively. Supposing that the system operates in steady state and DC current I dc is 3 kA before the fault occurs. It is assumed that it takes at least 6 ms from the occurrence of the fault to the blocking of the hybrid converter. Then the relationship between K FB,min and the DC line length can be obtained according to Equation (35) and is depicted in Figure 8.
As can be seen in Figure 8, for the above system, the required proportion of FBSMs can be reduced to less than 50% when  the length of DC line is short than 243 km. In fact, for the conventional hybrid MMC with the same parameters, the required proportion of FBSMs would also exceed 50% when the DC line is longer than 243 km. This is because the main constraint on the FBSMs proportion of conventional hybrid MMC changes from Equations (1) to (3) introduced in Section 2. Furthermore, the modified hybrid MMC can use less FBSMs than the conventional one to keep the maximum capacitor voltage under threshold value, because the energy charged into FBSM capacitors during the fault is reduced by blocking the energy from the AC system. Therefore, the required proportion of FBSMs of the modified hybrid MMC is always lower than that of the conventional one, and this advantage will be more obvious when the DC line is short.
In order to verify above conclusions, a modified hybrid MMC test system is established in PSCAD/EMTDC. The main circuit parameters of the MMC are same as Table 1. The length of DC line is set as 100 km and the number of FBSMs is correspondingly set to 71 (31% of N total ) according to Figure 8. It is assumed that the DC fault occurs at the end of the DC line far away from the MMC station. DC fault occurred in different time is simulated in the test system. Figure 9 shows  the maximum capacitor voltage when the DC fault occurs at different time in a system cycle. According to Figure 9, the maximum capacitor voltage would reach 3.004 kV under some specific fault time, which is still lower than the threshold value 3.08 kV. Therefore, the FBSMs proportion calculated by the above method can ensure that the capacitor voltage during the fault under threshold value.

Test system
In order to verify the effectiveness and feasibility of the modified hybrid MMC, a three-terminal MMC-HVDC system is established in PSCAD/EMTDC. The system structure is shown in Figure 10. In order to test whether the three-phase shortcircuit applied during DC fault will affect the stability of AC system, the four-machine system introduced in [25] is used. MMC-2 station and MMC-3 station are connected to bus 7 and bus 9 of the same four-machine system respectively. The parameters of generators and loads in four-machine system are listed in Table 2. The modified hybrid MMC is used in all MMC stations with the same parameters of Table 1. The number of FBSMs The capacitor voltage balancing strategy introduced in [17] has been used to achieve the voltage balancing among HBSMs and FBSMs.

Simulation results
As a comparison, the fault response characteristics of the test system using the conventional hybrid MMC with 50% FBSMs are also simulated. Supposing that the test system is in steady state at the beginning, a permanent DC line-to-ground fault F-1 is applied at the end of Line-2 near the MMC-2 station at t = 0.2 s. Fault resistance is 0.001 Ω. The simulation results are depicted in Figure 11. In the case of using modified hybrid MMC, the arm current of MMC-1 and MMC-2 exceeds the threshold value 6 kA at As shown in Figure 11, the test system using modified hybrid MMC has almost the same DC fault response characteristic as the one using conventional hybrid MMC. In addition, the wave form of generator phase angle in four-machine system shows that they have the same effect on AC system when dealing with DC fault. Figure 12 depicts the AC current of the modified hybrid MMC during the DC fault. As can be seen, over current caused by the active three-phase short-circuit lasts for about only 20 ms and maximum value will not exceed the over current caused by the three-phase line-to-ground faults on the point of common coupling (PCC). Therefore, it is proved that the threephase short-circuit applied during DC fault will not affect the stability of the system.
The waveforms of average capacitor voltage in each arm of modified hybrid MMC during the fault are depicted in Figure 13. The capacitor voltage in MMC-1 station increases most during the fault. And the maximum value of capacitor voltage in MMC-1 is 3.03 kV, which is still below the threshold value 3.08 kV. The capacitor voltage in MMC-3 is significantly lower than that of other two stations during the fault. This is because MMC-3 station is blocked due to the blocking signal from other station before its arm current exceeds the threshold value.
In order to ensure that the maximum capacitor voltage will not exceed the threshold value under different faults, the faults at several extreme locations are simulated. The selected faults  are at the ends of the Line-1 and Line-2, which are marked by F-2 to F-4 in Figure 10. The maximum capacitor voltage waveforms of each station under these DC faults are depicted in Figure 14. As can be seen in Figure 14, the maximum capacitor voltage is 3.08 kV appearing in the MMC-1 under the fault F-4, which is still below the threshold value. Assume that the IGBTs 5SNA 3000K452300 with 3 kA current rating and 4.5 kV voltage rating are used in all SMs, and the thyristors 5STP 45Y8500 with 8.5 kV voltage rating is employed in ACBSs. The voltage that a single thyristor bears should be 4.25 kV [22]. Each ACBS needs to withstand the maximum phase-to-ground voltage 214 kV on the AC side. Hence, each ACBS consists of 102 thyristors. The comparison of two strategies is shown in Table 3. It can be seen that the number of IGBTs of the modified hybrid MMC is 516 less than that of the conventional hybrid MMC, while 306 additional thyristors are required. Since the price of the thyristor is much lower than that of the IGBTs, the manufacturing cost of the modified hybrid MMC is significantly reduced compared to the conventional one.
According to the above simulation results, the modified hybrid MMC can effectively deal with the DC fault with less FBSMs than the conventional hybrid MMC, which can signif-FIGURE 15 Test system based on the Kunliukong project icantly reduce the manufacturing cost and operation loss of MMC-HVDC systems.

Case study based on practical engineering
In order to make the above conclusions more representative, a simulation model based on the Kunliulong project in monopole operation state is established in PSCAD/EMTDC. The system structure is shown in Figure 15. In the test system, one LCC with twelve impulse unit connection is adopted as the rectifier station. And another two MMC stations are composed with two modified hybrid MMC unit connected in series. The parameters of converter units in each station are listed in Table 4. LCC-1 adopts the constant current control and the reference value of DC current is 5 kA. The MMC-1 station is operated with constant active power control and the reference value is 1500 MW. The MMC-1 station adopts constant DC voltage control with the reference value of 800 kV. The lengths of Line-1 of Line-2 are 932 and 557 km respectively.
Supposing that the test system is in steady state at the beginning, a permanent DC line-to-ground fault is applied at the end of Line-2 near the MMC-1 station at t = 0.1 s. The simulation results are shown in Figure 16. The arm current of MMC-1 exceeds the threshold value 3.75 kA at t = 0.1020 s.
Both MMC units of MMC-1 station are blocked immediately and ACBSs are closed. At t = 0.1040 s, MMC-2 station receives and executes the blocking signal from MMC-1. At t = 0.1052 s, LCC-1 station receives the blocking signal and forces the firing angle to 145 • . At t = 0.1190 s, all DC fault current drops to zero and UFD-3 and UFD-4 are opened. At t = 0.1220 s, ACBSs in MMC-1 and MMC-2 are completely tripped. As can be seen in Figure 16, DC fault has been successfully cleared and the maximum average capacitor voltage in each MMC units is 2.32 kV, which is much lower than the threshold value 2.8 kV. Therefore, the feasibility and effectiveness of the modified hybrid MMC have been further verified.

CONCLUSION
This paper proposed a modified hybrid MMC with lower proportion of FBSM than the conventional hybrid MMC, while the DC fault clearance capability is retained. Three DC fault clearing conditions of the hybrid MMC are first introduced.