Semiconductor loss calculation of DC–DC modular multilevel converter for HVDC interconnections

: DC–DC modular multilevel converter (DC–DC MMC) is an attractive candidate for high-voltage DC (HVDC) interconnections since it can provide the required voltage matching, galvanic isolation and flexible power control abilities. The semiconductor loss of such a DC–DC MMC is a major concern for both system evaluation and parameter design. However, it cannot be measured directly since it is out of the precision range of the high-voltage measuring equipment, and thus, mathematical analysis is considered as a feasible alternative. This paper proposes an accurate off-line loss calculation method for DC–DC MMC modulated by fundamental frequency modulation. Based on the characteristics of the modulation, the switching moments along with the instantaneous voltage and current can be calculated exactly, and the conduction loss and switching loss of each submodule can be expressed in a mathematical way. The calculation results are compared with the simulation results from a comprehensive switched model and show good accuracy performance within a relative error of ± 2% under different operating conditions.


Introduction
The interconnection of two or more high-voltage DC (HVDC) grids is considered as a vital part of the establishment of future smart grids. It can enhance the reliability and effectiveness of the system by providing mutual power support and reducing the system reserve capacity. In this scenario, high-performance DC-DC converter is required.
Compared with traditional multilevel converters such as flying capacitor converter, neutral-point clamped converter or cascaded converter [1][2][3][4], modular multilevel converter (MMC) is a promising candidate due to its low switching frequency, low harmonic content, high level of modularity and simple implementation of redundancy. Many DC-DC topologies have been proposed based on MMC, which can be classified into nonisolated [5][6][7][8] and isolated types [9][10][11][12][13][14][15][16]. Non-isolated DC-DC MMC has the advantage of reduced investment cost and is preferable in high voltage, but common ground applications. However, in cases where galvanic isolation is required, the isolated DC-DC MMC with an interlinked transformer is necessary. Such isolated DC-DC MMCs could have many topology variations, as shown in Fig. 1. The structure of submodules could be half-bridge (HB) or full-bridge; for the primary (or secondary) side, the AClink voltage could be generated with monopolar arrangement structure, or two-or three-arrangement structure according to different HVDC lines and power levels, as shown in Figs. 1a-c.
Different modulation technologies are feasible for such DC-DC MMCs. The quasi-2-level (Q2L) modulation and 2-level (2L) modulation were proposed in [9][10][11][12]14], respectively, where submodules are almost switched synchronously and the AC-link voltage is modulated as trapezoidal or rectangular waveform. With Q2L and 2L modulations, the harmonics of current and voltage will be relatively high and thus leads to more conduction loss. On the other hand, the switching loss can be reduced since zero-voltageswitching is possible. The staircase modulation (or sinusoidal modulation) proposed in [8,[17][18][19] can ease the transformer design since the AC-link voltage is modulated as a sinusoidal-like staircase waveform. However, the switching loss can be more distinct because the soft-switching is difficult to realise. As a tradeoff, the fundamental frequency modulation (FFM) in [20] is proposed, which inherits the merit of staircase modulation but with reduced switching loss. With FFM, the AC-link voltage is modulated as staircase waveform, and the switching frequencies of submodules are fixed at the fundamental frequency. In this paper, the isolated DC-DC MMC with FFM is focused on.
As one of the main operation parameters, the semiconductor loss is a key reference when designing heat dissipating system and selecting the type of devices. For the isolated DC-DC MMC, the total loss mainly consists of two parts: the semiconductor loss and the transformer loss. The transformer loss can be evaluated using simplified resistance model and data provided by the manufacturer [8]. Also, it can be obtained directly with measuring equipment. However, it is not practical to measure the semiconductor loss, since the total loss of semiconductors is usually below several percentages of the rated power, and is out of the precision range of the high-voltage measuring equipment. Therefore, this paper focuses on the calculation of semiconductor losses, and the transformer loss is out of scope. To address this issue, two methods are commonly used for loss calculation. The first approach is to build a comprehensive switched model of the converter using simulation software such as PSCAD/EMTDC and MATLAB/ Simulink [21], and calculate the loss with real-time simulation results. The calculation is highly accurate since the voltage and current can be obtained precisely and the switching and conduction characteristics of the semiconductors can be well described. However, the process is usually complex and time-consuming. Instead, calculating the loss by introducing mathematical analysis is considered as an efficient alternative.
Several techniques have been proposed to calculate the semiconductor loss of MMC for DC-AC conversion. Based on a thermal model, the conduction and switching loss were estimated in [22] by using the simulated current waveforms and specifications of the semiconductor under the premise of a constant junction temperature. Tu and Xu [23] also used simulated waveform of current, and the loss was estimated with junction temperature feedback. Rodrigues et al. [24] used the temperature correction factor to improve the accuracy, and an average strategy was introduced based on an assumption of the switch states. Zhang et al. [25] simplified the switching function into a continuous change rate function, and computational efficiency was further increased by replacing part of the detailed calculation by estimated upper limits. Yang et al. [26] derived a loss model with linear fitting method applied to the relationship between the loss and the current of semiconductors. In the existing literatures, losses are usually estimated by introducing the concept of probability and average. It is because that the switching frequency of the submodules in MMC is uncertain and would be affected by the employed sort-and-selection strategies for voltage balancing control. In this way, the error might be relatively large. Also, when simulated waveforms are used in the mathematical model, the online calculation process could be computationally intensive and time consuming for a large number of submodules.
For the proposed DC-DC MMC, the semiconductor loss calculation can be less complicated. Since the DC-DC MMC consists of two DC-AC MMCs, the existing mathematical methods are still viable. Besides, the reactive power in DC-DC MMC is often controlled to the minimum and the current is easy to be calculated with the transmitted active power. These features facilitate the loss calculation, especially when FFM is applied. With FFM, the switching frequency of each submodule can be fixed at the fundamental frequency, and the associated sort-andselection strategy is performed only once in each fundamental period, so that the switching frequency will not be affected by the voltage-balancing control. With FFM, not only the instantaneous voltage and current, but also the switching moments and state of each submodule can be determined precisely in an analytical way. This makes the loss calculation process not only accurate but also effective since it can be achieved off-line.
According to the aforementioned issues, this paper proposes a semiconductor loss calculation method based on a mathematical model for isolated DC-DC MMC with FFM. The remaining of the paper is organised as follows. In Section 2, the basic structure, modulation method and model of MMC are introduced. In Sections 3 and 4, the semiconductor loss calculation of a submodule and the overall converter are illustrated. The calculation results are compared with a comprehensive switched simulation results in Section 5, and the conclusion is drawn in Section 6.

Topology of the isolated DC-DC MMC
For illustrative purpose, the simplest monopolar arrangement DC-DC MMC shown in Fig. 2 is used as an example in this paper. It is briefly introduced as follows: (i) On the primary and the secondary sides, the monopolar arrangement is used and interlinked by an ideal transformer with turning ratio N t and a leakage inductance L t . The coupled arminductors are with self-inductances L ap , L as and mutual inductances M ap , M as . (ii) The structure of submodules is selected as HB and each arm consists of N submodules. For each submodule, the DC-link capacitor C sm is inserted when the upper switch T 1 is turned on and T 2 is turned off, and is bypassed when T 2 is turned on and T 1 is turned off. (iii) The arm voltages of primary and secondary sides are denoted as v arm_Up , v arm_Lp and v arm_Us , v arm_Ls . v arm are of staircase waveform modulated by FFM. (iv) The capacitor dividers C div_p and C div_s are used to provide the middle points for both sides. They are sufficiently large and their voltages are treated as v div_p = V dc_p /2 and v div_s = V dc_s /2.

Modulation of the isolated DC-DC MMC
The FFM proposed in [15] is used for the isolated DC-DC MMC in this paper. As shown in Fig. 1b, each gating signal is strictly turned on and off only once in a fundamental period T 0 ; and the voltage balancing is achieved by re-matching the gating signals and the submodules at the beginning of each fundamental period. Such a modulation method reduces the switching loss of the submodules. With such a modulation method, the arm voltage can be determined by the modulation indexes m _Up and m _Lp (for the upper and lower arms in primary side), m _Us and m _Ls (for the upper and lower arms in secondary side), which are defined as follows: where ω 1 = 2π/T 0 ; γ is the phase-shift angle between AC-link voltages of the primary and secondary sides. M dp and M ds are limited within [0, 0.5], so that m _Up , m _Lp , m _Us and m _Ls can be normalised within [0, 1]. Also, the exact switching moments of each submodule can be obtained so that the switching loss can be calculated precisely. As shown in Fig. 1b Therefore, the switching moments of the ith submodule, denoted as α r(i) and α f(i) , can be determined α r(i) and α f(i) can be expressed as

Modelling of the isolated DC-DC MMC
To provide the basis of semiconductor loss calculation, the arm currents should be calculated. Several assumptions are made to simplify the model: (i) The specifications of each submodule (including the semiconductors and the capacitor) are identical; (ii) The number of submodules is large and their voltages are well balanced and regarded as equal, so that the harmonic components of the arm voltages are ignored; (iii) For the same reason, the harmonic voltage and current components of AC-link are also ignored and considered as sinusoidal.
Based on these assumptions, the arm current can be expressed as When the DC power P dc is given, the DC current in (6) can be easily calculated as The AC components i t_p and i t_s in (6) can also be obtained by using the AC equivalent circuit of the converter presented in Fig. 3, where the primary and secondary sides are regarded as two voltage sources u p and u s ′, and the power between primary and secondary sides is transmitted through the equivalent inductor L eq . According to Kirchhoff voltage laws, the equivalent circuit can be described as where L eq = (1/2)L ap + (N t 2 /2)L as + L t , U p = k p ⋅ M dp V dc_p and U s ′ = k s M ds N t V dc_s , k p and k s are the correction factors from the modulation indexes M dp,s to the fundamental components of the arm voltages, which are introduced because these fundamental components might deviate from M dp,s V dc_p,s especially when the number of the submodules is relatively low. The method to obtain k p and k s has been given in [20] and thus is not repeated here.
The active power of AC-link can be obtained as Ideally, the active power of the AC-link P ac equals to P dc . Based on (9), it can be seen that when DC power P dc , modulation indexes M dp,s and DC voltage V dc_p,s are given, the phase-shift angle γ can be obtained, and then the AC component of the arm currents i t_p and i t_s can be easily calculated as where γ = arcsin (2ω 1 L eq P dc )/(U p U′ s ) , ϕ ps = (U′ s sin γ)/(U p − U′ s cos γ) and .
Based on the developed analytical models (7) and (10), the current flowing through the submodules at any switching moments can be calculated and can be used for later loss calculation.

Loss analysis of the submodule
The loss of the semiconductors is composed of two parts, the conduction loss and switching loss. Based on the submodule voltage (V dc_p /N p or V dc_s /N s ) and current calculated by the models (6), (7) and (10), both types of losses can be calculated according to the different switch states. In this section, the conduction loss and switching loss are calculated, respectively, by taking the submodules of upper arm on primary side as an example.

Calculation of conduction loss
The switching pattern of the submodules with typical driving signal g (m) is illustrated in Fig. 4. As shown in Fig. 4, the current path depends both on the switch state and the direction of the arm current. When the arm current is positive, it will flow through switch T 2 if the submodule is bypassed as shown in case 1 of Fig. 4, and will flow through diode D 1 and charge the capacitor C sm if the submodule is inserted as shown in case 2. When the arm current is negative, it will flow through switch T 1 and discharge the capacitor C sm if the submodule is inserted, as shown in case 3, and will flow through diode D 2 if the submodule is bypassed, as shown in case 4.
The conduction loss of the semiconductor is resulted from two parts, the conduction resistance and the conduction voltage drop due to the bipolar-device nature of the IGBTs. Taking the certain submodule driven by gate g (m) in Fig. 4 as an example, the calculations are illustrated as follows: In case 1, the arm current will flow through the IGBT T 2 , hence the voltage drop can be expressed as where U T0 and R CE are the threshold voltage and conduction resistance of T 2 , which can be obtained from the manufacturer datasheet.
In one fundamental period, the conduction loss of T 2 can be expressed as where α r(m) presents the turn-on moment of g (m) , which can be calculated by (5), α i2 is one of the zero-crossing points in one fundamental period of the arm current, as marked in Fig. 4, and can be calculated as Substituting (14) and (16) into (15), (15) can be reorganised as P cond_1(m) = U T0 I Tav1 + R CE I Trms1 where I Tav1 and I Trms1 are the average and RMS values of the current flowing through T 2 in one fundamental period, which can be given by In case 2, the arm current will flow through the diode D 1 , hence the voltage drop can be expressed as where U D0 and R D are the threshold voltage and conduction resistance of D 1 . Therefore, the conduction loss can be expressed as P cond_2(m) = 1 where α i1 is another zero-crossing point of the arm current, as marked in Fig. 4, which can be calculated as Therefore, (20) can be further deduced as where I Dav2 and I Drms2 are the average and RMS value of the current flowing through D 1 in one fundamental period, which can be given by Similarly, in case 3 the conduction loss can be calculated as P cond_3(m) = U T0 I Tav3 + R CE I Trms3 where α f(m) presents the turn-off moment of g (m) , which can be calculated by (5). I Tav3 and I Trms3 are the average and RMS values of the current flowing through T 1 in one fundamental period, which can be given by In case 4 where I Dav4 and I Drms4 are the average and RMS value of the current flowing through D 2 in one fundamental period, which can be given by

Calculation of switching loss
The switching loss of the semiconductor consists of the turn-on loss and turn-off loss. The turn-on loss E on of IGBT is resulted from the energy loss caused by the discharging of the capacitor between the emitter and collector. The turn-off losses of IGBT and diode E off and E rec come from the overlap area of voltage and current during the fall time of current. Since the turn-on loss of the diode is far less than turn-off loss, it is ignored in the loss calculation.
Generally, the turn-on and turn-off energy E on and E off of IGBT, the reverse recovery energy E rec of the diode, and the reference voltage and current can be found from the manufacturer datasheet. They can be converted proportionately to adapt the operating condition, as where f 0 = 1/T 0 is the fundamental frequency. U ref_x and I ref_x (x = T, D) are the reference voltage and current, i x (α), u x (α) represent the instantaneous current and voltage of the semiconductor at the switching moment. Different from calculating the conduction loss, the switching loss is calculated based on the instantaneous state of submodules. Considering that inserting or bypassing a submodule involves a dead-time (a short period during which both IGBTs are turned off in case of shoot-through), the switching loss under different conditions are illustrated in Fig. 5.
(i) The arm current is positive: As shown in the top of Fig. 5a, the submodule is initially bypassed, and at the α r(i) moment, it is inserted into the arm so T 2 is first turned off, the current is commutated to D 1 , introducing the turn-off loss of T 2 . Such a loss can be calculated as After that, T 1 is turned on. However, no turn-on loss is caused since the current still flows through diode D 1 . As shown in the bottom of Fig. 5a, when the submodule is initially inserted and needs to be bypassed at the α f(i) moment, turning-off of T 1 will not change the current path. After a small dead-time, T 2 is turned on and D 1 is blocked reversely. Such a situation results in both the turn-on loss of T 2 and turn-off loss of D 1 , which can be expressed as (ii) The arm current is negative: As shown in the top of Fig. 5b, the submodule is initially bypassed and needs to be inserted, so T 2 should be turned off at the α r(i) moment. However, this will not change the current path. After a small dead-time, T 1 is turned on and D 2 is blocked reversely. Such a situation results in both the turn-on loss of T 1 and turn-off loss of D 2 , which can be expressed as As shown in the bottom of Fig. 5b, when the submodule is initially inserted and needs to be bypassed at the α f(i) moment, T 1 is turned off and the arm current is commutated to D 2, introducing the turnoff loss of T 1 , which can be calculated as Since all the possible conditions are discussed, the switching loss of a specific submodule can be calculated by selecting the formula (29)-(32) based on the practical operation condition, i.e. the switching moment, whether the submodule is inserted or bypassed, and the direction and value of the arm current. All of the above information can be obtained using the derived model in Section 2.

Loss calculation of the isolated DC-DC MMC
In Section 3, all possible cases of the submodule operation involved with loss calculation are analysed. In this section, the flowchart of calculation is further designed. Since the upper and lower arm are considered to be symmetrical and there is no discrepancy between the specifications of the submodules, the loss from primary side is first calculated as an example in this section. As can be seen in Fig. 6, the operating parameters, including the rated power P dc , DC voltages V dc_p, s , and the modulation indexes M dp, s are first input. According to (7), (10), (6), (16) and (21), the expressions of arm current and the zero-crossing points can be obtained. For each submodule, its conduction loss and switching loss will be calculated sequentially.
For the ith submodule, the conduction loss is first calculated. According to the analysis, in one fundamental period, four cases may occur representing different conduction state of the semiconductors. As can be seen in Fig. 4, one fundamental period is divided into different time zones z (x) (x≤5) based on both the switching moments of the submodule and the zero-crossing points of arm current. By judging the type of case, the conduction state of the semiconductors can be obtained and the conduction loss can be calculated referring to the method introduced with (14)- (27). After calculating the conduction loss of each time zone, the results are accumulated and stored as P cond_ i , which represents for later calculation.
After that, the switching loss of the ith submodule is calculated. For the switching moments of the submodule α r(i) and α ( f i , the direction of the arm current is used for judgement. If the arm current is positive at α r i , the switching loss can be calculated with (29). Otherwise, it can be calculated with (31). If the arm current is positive at α f i , the switching loss can be calculated with (30). Otherwise it can be calculated with (32). After finishing the calculation, results are accumulated and stored as P switch_ i , which represents for later calculation.
When both the conduction loss and switching loss of the ith submodule are calculated, the same process is applied to the next submodule, and then continues until i > N, so that the losses of all the submodules of the arm are considered. Since the calculation results of the lower arm in primary side are assumed to be the same as the upper arm, the sum of the calculation results of primary side are added up as The calculation of the conduction and switching loss of the secondary side upper P loss_s can also be conducted with the same process, the loss of the converter can be finally deduced P loss = P loss_p + P loss_s (34)

Simulation verification
In order to verify the validity of the proposed calculation method, simulation platform based on a comprehensive switched model of isolated DC-DC MMC with FFM is built in MATLAB/Simulink software. The parameters are shown in Table 1. The semiconductor devices used in this paper are the IGBT modules of Mitsubishi (CM800HC_H66) 3300 V/800A. The parameters of the IGBT and the diode are also shown in Table 1.
In the simulation, the submodules number is N = 5, and the arm voltage and current from primary and secondary sides are illustrated in Fig. 7. It is seen that the arm currents i arm_Up,s and i arm_Lp,s are almost sinusoidal and mainly composed of DC and fundamental AC components; and although the arm voltages v arm_Up,s and v arm_Lp,s are staircase waveforms, it is also dominated by DC and fundamental frequency AC component, and can be considered as sinusoidal by ignoring the harmonic components.
To prove the validity of the proposed method, the phase-shift angle is changed from 0.524 to 5.766 rad, and the DC power P dc is varied from − 108.7 to 217.3 kW, as shown in Table 2. The phase and amplitude of arm current from both primary and secondary sides also change along with the phase-shift angle. The calculation results compared with the simulation results of primary and secondary sides are presented in Figs. 8a and b, respectively. The relative error e r is defined as e r(n) = P cal(n) − P sim(n) P cal(n) × 100% where P cal(n) , P sim(n) are the calculation and simulation results of number n condition (1 ≤ n≤12). As shown in Fig. 8c, the relative errors e r(n) in all conditions are restricted to ± 2%. Referring to the relative errors (2.5-10%) given in the literatures [25][26][27][28], the relative error in our study is small enough for submodule thermal design and system evaluation.
To further validate the proposed calculation method, the system is tested under other two different fundamental frequencies, 800 and 1200 Hz. As shown in Fig. 9a, as the frequency increased, the total semiconductor loss also increases. Moreover, it can be observed in Fig. 9b that the conduction loss is almost unchanged. It is because that the conduction loss only depends on the device parameters and the arm current, which is analysed in (14)- (27). Obviously, the difference of the total semiconductor loss is mainly derived from the switching loss, as can be seen in Fig. 9c. The switching loss is sensitive to the increment of the fundamental    frequency and increases distinctly, which implies that the fundamental frequency f 0 can affect the switching loss directly as analysed in (28)-(32). In both Figs. 8 and 9, the simulation results match well to the calculation results, which proves the validity of the proposed method.

Conclusion
The paper has proposed a semiconductor loss calculation method for isolated DC-DC MMC with AC-link. Based on the fact that the AC-link is with high frequency, the proposed method has neglected the harmonic components so that the arm voltages and currents can  be simplified and expressed analytically; based on the fact that the DC-DC MMC is modulated by FFM, the switching moments of each submodule have been calculated precisely, and both the conduction loss and switching loss have been expressed in an analytical way. A calculation flowchart has also been provided to calculate the total loss. The calculation results have been compared with the simulation results from a comprehensive switched model, and the proposed method shows good effectiveness within relative errors of ± 2%.

Acknowledgment
This work is supported by the National Natural Science Foundation of China, grant no. 51777085.