Comparison of digital PWM control strategies for high-power interleaved DC–DC converters

: Three pulse-width-modulation (PWM) digital control approaches are evaluated to provide the current sharing between phases in high-power dual-interleaved DC–DC converters. The implementation of a digital peak current, multi-sample averaged current and an enhanced single-sample averaged current control in a TMS320F28377D is described. A summary of stability requirements is provided for designing the controllers and experimental results from a 60 kW, 75 kHz silicon carbide DC–DC converter are used to evaluate the steady-state and dynamic performance of the three control methods. Overall the best performance in terms of tracking and speed of response was achieved by the enhanced single-sample method. The multisampled technique provided the highest tracking accuracy, but at the expense of the slowest dynamic response. The fastest dynamic response was achieved by the digital peak current control, but this method is limited by poor noise immunity and instability for duty ratios in the region of 0.5.


Introduction
By sharing the current between parallel-connected, phase-shifted channels, interleaving techniques provide a method of spreading the thermal load and reducing passive component requirements in high current converter applications. For example, in multi-kW DC-DC converters that might be used in an electric vehicle power train [1]. However, to ensure current sharing between the parallel channels, individual current regulators are normally required, which are often implemented using analogue techniques such as peak current mode (PCM) control [2,3].
Recent advances in digital technology have resulted in microcontroller units (MCUs) such as the TMS320F28377D with the onboard resources and computational speed to implement direct digital control of high-frequency power converters, potentially bringing benefits of improved noise immunity and flexibility. However, the inherent delays of the analogue-to-digital (A/D) conversion, the computation time and the operation of the digital pulse-width-modulation (DPWM) [4,5] introduce an extra phase shift in the control-loop which has a detrimental effect on the controller bandwidth and the system stability [6,7]. Therefore, extensive efforts have been made to reduce the delays of the A/D conversion, the computation time [5,6,8] and the DPWM operation using predictive techniques [7,[9][10][11].
The most common digital current mode controllers aim to regulate either the average current (average current mode, ACM), or the peak current (PCM) that flows through the separate interleaved converter phases. ACM control can be classified into two different categories according to the way the current is sampled: single-sample ACM and multi-sample ACM. PCM control can also be classified into predictive and mixed-signal PCM.
The single-sample ACM and predictive PCM techniques avoid the need for continuous sampling and reduce the ADC conversion time. By suitable selection of the sampling instant of the inductor current, the local average current or peak current can be acquired directly and subharmonic oscillations can be avoided if a suitable modulation carrier is employed [9]. The multi-sampling ACM is ideal for noisy environments; by taking the average of multiple samples in each cycle, the true average current is obtained and the noise-related problems are eliminated. However, the computational resources increase with respect to the single-sample method and limit the achievable operating frequency. The major drawback of the ACM techniques is that the control action takes at least one switching period to be executed after the sampling is performed. This is because the duty ratio is updated only once per switching period. Predictive PCM techniques were conceived to overcome this issue by calculating the value of the peak current a cycle ahead using not only the sampled current but other variables as well, such as the input voltage [9].
The mixed-signal PCM replicates the concept of an analogue PCM controller using a combination of digital modules and analogue comparators. A first version of this solution was successfully demonstrated in [12]; however, due to the limited resources of the available MCUs, the technique was not extendable to interleaved converters. Another example of mixed-signal PWM implemented in a field-programmable gate array for a singletransistor buck converter is shown in [13].
Although analogue and digital PCM and ACM PWM control techniques are well established for single-transistor topologies, their modelling and application to interleaved converters is still developing. For example, a non-linear analysis and a digital PCM controller with variable slope compensation for interleaved converters has been proposed recently [14], whilst an averaged small-signal model of the dual boost interleaved converter with coupled inductors operating in discontinuous mode is proposed in [15]. Furthermore, the impact of the magnetic coupling on the stability of dual-interleaved boost converters with sampled ACM using the sampler decomposition technique is presented in [16].
This paper compares three digital PWM control strategies for a high-power, high-frequency dual-interleaved DC-DC converter. The control strategies investigated are mixed-signal-based PCM, eight-sample ACM and single-sample ACM. The operating principles are similar to those reported in [7,11,12]. However, unlike the implementation in [7], individual current control is used for each phase of the converter with a common current reference. The techniques in [11,12] have not previously been applied to multiphase converters, and due to the features of the MCU employed [17], the digital PCM is easily implemented for the dualinterleaved converter. Moreover, an enhanced version of the singlesample ACM control technique is implemented.

Implementation of the control strategies
The three control strategies were implemented in an evaluation platform developed with a dual-core 32-bit TMS320F28377D Delfino MCU from Texas Instruments. The dual real-time control subsystems provide 200 MHz of signal processing performance and feature two real-time control-law accelerators to implement time-critical control algorithms. The MCU has integrated analogue and control peripherals allowing further system consolidation. Functions such as the discrete slope compensation and signal averaging are implemented into the co-processors and the available peripherals, enabling the MCU to be dedicated to the main control routine.
The dual-interleaved DC-DC converter topology is shown in Fig. 1 and incorporates an interphase transformer (IPT). Q 1 -Q 4 represent the gate drive signals for the transistors, and the pairs Q 1 , Q 3 and Q 2 , Q 4 can operate in a complementary mode, or in buck/ boost mode.

Digital PCM control
The operation of the digital PCM controller is similar to its analogue counterpart. The comparators, ramp generator circuits and PWM modules are all replaced by MCU functions. Fig. 2a depicts the block diagram of the digital PCM controller. The reference for the phase currents, I ref , is combined with the digital slope generator waveforms to form the individual phase reference currents. The two digital slope compensating ramps are phase shifted by 180° and subtracted from the value of I ref to prevent subharmonic instabilities. The resultant internal signals form inputs to independent 12-bit digital-to-analogue converters (D/A) connected to the negative input of on-board analogue comparators. The positive input of each comparator is connected to the measured phase currents, i a (t) and i b (t), of the IPT, respectively.
Sketches of the idealised waveforms are shown in Fig. 2b depicting the phase currents i a (t) and i b (t), the outputs of the D/A, I ref,a and I ref,b , which are the difference between the reference current demand I ref and its respective compensating slope, and the DPWM signals for the lower switches, Q 1 and Q 2 . At the start of the switching period, T, the gate drive signal Q 1 is forced high so the transistor turns on. As the time progresses, the compensating ramp with fixed slope M is subtracted from the initial set point value, I ref , and when the resultant meets the phase current level, the comparator sends an interrupt to the PWM module. Then, the gate drive signal Q 1 is forced low for the remainder of the period, creating a cycle-by-cycle current trip event. At the same time, the output of the digital slope compensator resets to the initial value of I ref and remains static until the next switching cycle.
The propagation delay for the interrupt is ∼60 ns [17] and so the operation of the digital PCM controller is not significantly different to an analogue implementation. Consequently, any change in I ref will result in a virtually immediate change in the phase currents, resulting in a very high bandwidth [13]; however, average current regulation is not achieved because the peak-to-peak phase current in this topology behaves non-linearly with the duty ratio. Current transients during the turn-on instants are blocked from the controller using a leading-edge blanking window of 25 ns. Fig. 3a shows the block diagram of the multi-sample ACM control where the phase currents are individually sampled by a 12-bit A/D converter. Analogue comparators are not required. Before the A/D, the signals pass through anti-aliasing filters each with a 230 kHz cut-off frequency, which is below one-half of the maximum sampling frequency. In order to calculate the average value of the phase current, the controller acquires eight samples of each channel at equally spaced time points T/8 apart. The A/D converters are interrupted by signals generated by the PWM modules so high sampling rates along with precise timing can be achieved.

Multi-sample ACM
At the end of the acquisition process, the average value of the eight samples over the switching cycle is calculated (AVG) and compared against the reference current, I ref . The calculated error passes through a digital proportional-integral (PI) compensator, and the computed duty ratio, D, is updated at the start of the next switching cycle while its corresponding gate drive signal is forced high.
The operation of the multi-sample ACM control with a trailing edge modulation is illustrated in Fig. 3b. The waveforms shown are the phase currents i a (t), i b (t), the counter values C a (t), C b (t), the duty-ratio values D a (t), D b (t), the sampling instants in both phases and the generated PWM signals for Q 1 and Q 2 . When the value of the duty ratio, D a , in the PWM module is higher than the value of the counter, C a , then the gate drive signals are forced low. The duty ratio must be updated within the same switching cycle to avoid an extra one switching-cycle delay. The acquisition time for the eight samples, the calculation of the average value and the processing time of the PI controller have a detrimental effect on the bandwidth of the control loop [18], resulting in slower and possibly more oscillatory regulation of the phase currents. Fig. 4a shows the block diagram of the single-sample ACM control. The phase current is sampled only once in the middle of the transistor conduction intervals (when C a = 0) as shown in Fig. 4b. The acquisition and calculation process starts when the counter C a of the PWM module is equal to zero. Owing to the symmetry of the waveforms over the switching cycle, the acquired sample is approximately the local-average value of the phase current. The sampled average current is then compared against the reference current I ref , and the error is fed into a discrete PI compensator which calculates the new duty ratio. Finally, the calculated duty ratio is loaded into a digital PWM generator to produce the transistor-driving signals. Due to the operation of the DPWM, the duty ratio is commonly updated at the beginning of the next switching cycle; however, this generates an inherent delay of one switching cycle in the control process. To eliminate this delay, the DPWM generator is updated with the new duty ratio as soon as the calculation is finished, as shown in Fig. 4b. The effect of this modification is examined in Section 5.4, demonstrating that it does not have an impact on the regulation of the average current. In contrast with the multi-sample technique, the processing time of the controller and the latency of the A/D conversion become the only sources of delay, leading to an improved control loop bandwidth [16]. As a result, the phase currents will exhibit smaller oscillations and faster settling times.

Comparison of hardware requirements
The hardware resources and the total response time for the three control methods are summarised in Table 1. The comparators, the D/A converters and the slope generators used in the digital PCM control are all on-board the TMS320F28377D MCU. Therefore, the response time is dependent only on the propagation delay from the comparator that feeds the signal into the PWM module. The maximum switching frequency in PCM is limited by the resolution of the compensating ramp generators. Although the A/D modules have the same configuration for both ACM control methods, the averaging and the simultaneous sampling process in the multi-sample ACM increases the total response time. Since the duty ratio is updated at the beginning of the next switching cycle, the maximum switching frequency is limited to 92 kHz.
In contrast, the single-sample ACM only requires the sampling of the phase currents once per switching cycle, and the duty ratio is immediately updated, reducing the response time significantly. It is estimated that the maximum switching frequency is at least five times that of the multi-sample ACM.

Controller design
Boost mode operation was assured in the discussion of controller design since its dynamics are more complex than those in buck mode.

Ramp compensation for the PCM control
The stability regions of the dual-interleaved converter with IPT and PCM are more complicated than for a single converter and are given in [19]. The interaction of the phases through the IPT affects the slopes of the switch currents and consequently, the stability depends not only on the duty ratio, D, but also on the inductance ratio, L r , between the differential inductance of the IPT, L diff , and the filter inductance, L in . The inductance ratio L r is normally much greater than four to ensure continuous conduction in the filter inductor and under this condition, the analysis in [19] has demonstrated that a minimum value for the compensating slope M of 0.25(V BUS /2L in ) guarantees the stability in the region 0.1 < D < 0.9. Table 2 shows the values of the converter's components. The inductance ratio is 134.6, and assuming a maximum bus voltage of 800 V, the minimum slope required for stability, MR s , is 115.6 kV/s. R s is the current transducer gain. In the prototype, a compensating ramp of 120 kV/s was used.

Modelling the ACM control methods
The control loops were modelled as shown in Fig. 5. The samplers S a and S b represent the phase-shifted, A/D conversion of the phase currents. Accurately capturing the interleaved operation of the samplers is important for correct prediction of the closed-loop dynamics [16]. The PI compensators are labelled PI(z), and the computational delay of the control algorithms, t d , is modelled by the time-delay unit e -sτ where with t d as given in Table 1. The DPWM operation is accounted for using a zero-order-hold extrapolator transfer function, G h0 (s) = (1−e -sT )/s whilst the averaged small-signal dynamics of each phase current are modelled by the control-to-phase current transfer functions, G daia (s) and G dbib (s), and the controlto-opposite phase current transfer functions, G daib (s) and G dbia (s). When the components that comprise the converter phases are assumed to be identical G di (s) = G daia (s) = G dbib (s) and G dxi (s) = G daib (s) = G dbia (s).
Finally, the closed-loop transfer functions of Fig. 5 were determined using the sampler decomposition technique [16] yielding the expressions (2) and (3) above.
The modified z-transforms of the constituent transfer functions G di (z), G dxiϕ (z) and G dxiθ (z) are defined as

Design of the PI compensators
The PI compensator design for the ACM controllers was performed in two stages. In the first stage, the Control System Tuner (CST) in Simulink was used together with a decoupled version of the model of Fig. 5 [16]. The CST was programmed to iteratively evaluate the time-domain step responses of the decoupled, closed-loop system at a specific point of operation for several combinations of proportional and integral gains until the closest match to the target response was reached. Then in the second stage, the selected PI gains were evaluated using the full interleaved model of Fig. 5 [16], to verify the stability of the system, and to make final adjustment of the PI parameters.
For the purpose of this work, the target was a standard secondorder response with a maximum overshoot of 1% and a natural frequency of ω n = 20 krad/s (approximate rise time: t r(10−90%) ≈ 150 μs), using a digital backward-Euler PI compensator. The computational delay in the small-signal model was modelled as in (1). The operating point for the design of the compensators was V BAT = 380 V, average current per phase = 75 A, duty ratio = 0.46, average DC inductor current = 150 A and load resistance = 8.6 Ω, corresponding to the worst condition for stability in the experimental evaluation. The converter's component values are listed in Table 2. Fig. 6a compares the ideal unit step response against the closest match that was found using the multi-sample ACM model and the CST tool. The calculated PI gains were K p = 308.2 μ and K i = 12 s −1 . The plotted responses correspond to the full interleaved model shown in Fig. 5. The multi-sample ACM response is seen to exhibit lightly-damped high-frequency oscillations at the beginning of the transient (≈8.3 kHz) together with a low-frequency oscillation (≈833 Hz) which decays over a longer period of time. The lowfrequency oscillatory behaviour is associated with the interaction of the current-control loops [16], whilst the damping of the highfrequency oscillatory behaviour was observed to be indirectly proportional to the integral gain. The rise time of the multi-sample ACM response is approximately three times faster than that of the ideal second-order system due to the fast rise produced by the highfrequency oscillations, whilst the settling time is about 12 times longer than the target due to the low-frequency oscillation.  sample ACM response could be further reduced by increasing K i , but at the expense of reducing the damping of the high-frequency oscillations and increasing the overshoot. Fig. 7 shows the dual-interleaved DC-DC converter and the TI MCU used in the experimental validation. This dual-interleaved bidirectional converter with IPT uses 1200 V SiC metal-oxidesemiconductor field-effect transistors (MOSFETs) from CREE (now Wolfspeed) and it is water cooled. The voltage in the battery port can vary from 300 to 380 V, and the maximum bus voltage is 750 V. The continuous rated power is 60 kW, and a switching frequency of 75 kHz was used for the validation of all the control methods. A host board with the required stages for the conditioning of the current transducers' signals, filtering, protection, buffers and power supplies was developed for the TI control card. The control card of the MCU is mounted on the main interface PCB to maintain a low profile. The platform is then mounted on top of the gate drivers. The phase currents of the IPT are monitored with 400 kHz magneto-resistive current transducers and the conditioning removes the DC offset and sets the overall current gain. The host board can operate in stand-alone mode with an analogue current reference, or in a digital-interface mode, where the reference current can be set via a USB cable, or via a CAN interface. The software to implement the control strategies in the MCU was developed using TI's Code Composer Studio and controlSUITE. Fig. 8 presents a flowchart of the average current control methods in Code Composer.

Accuracy of the sampling methods
The accuracy of the sampling in the A/D converters of the MCU is controlled by the acquisition window [20] allowed to charge the sample-and-hold capacitors. As shown in Table 1, the acquisition time, t S+H , for both sampled methods is equal, and it has been set to 75 ns. By using a first order RC model, the settling accuracy of the sampling for the 12-bit A/D conversion of the MCU can be estimated as [20] Therefore, the accuracy of the A/Ds is expected to be 0.337 LSB, which translates to ± 22 mA given the gain of the current transducers and signal conditioning. However, a more significant source of error is associated with the propagation delays around the control loop, which misalign the current sample locations of the single-sample ACM. As a result, an offset error was observed in the steady-state average value of the phase currents which was directly proportional to the amplitude of the phase current ripple. In the prototype, the estimated total propagation delay of the control loop elements was 1.25 μs ± 0.25 μs, leading to a maximum steadystate error of about 3.7 A ± 0.9 A with the maximum duty cycle.

Performance in steady state
For each control method, the converter was tested in boost mode at power levels up to 60.5 kW, at the maximum bus voltage, 750 V, and with a maximum inductor current of 160 A. Over the battery voltage range, 300 V ≤ V BAT ≤ 380 V, stable voltage and current waveforms were observed for all the control strategies, and the operation remained stable after changes in load and current reference set-point. No limit cycle oscillations were identified during the operation, confirming that quantisation effects are negligible due to the high-resolution capabilities of the A/D and DPWM modules [21][22][23]. However, it was found that the operation of the digital PCM was unstable for duty ratios between 0.52 and 0.57 as a result of measurement noise in the current feedback signals and the very small inductor current slope for duty ratios around 0.5. The ACM strategies were able to operate over the whole range of duty ratio of the converter, even near to D = 0.5. Table 3 compares the most important features of the three control methods for steady-state operation.
The ACM strategies were unable to balance properly the currents when the converter operated in the discontinuous mode, and it was observed that one phase tended to the continuous current mode, whilst the other was in the discontinuous mode. This is because of a larger error in the calculation of the average. However, the current sharing in the discontinuous mode with the digital PCM was good. At different operating conditions in the continuous current mode, the measured DC imbalance between the phases was <5 A, or about 3% of the total input current.

Dynamic performance: step changes in the reference current
The transient behaviour was examined using step changes in load and reference current. Fig. 9 compares the experimental phase current i a for the multi-sample ACM, the single-sample ACM and the PCM strategies for two different battery voltage and power conditions when an additional 10 A per phase is demanded at t = 0 s. To facilitate the analysis of the i a waveforms, their instantaneous average values were plotted and superimposed over the waveforms. The right side of Fig. 9 shows magnified views of the transients. The step changes correspond to an increase in the total input current from 100 to 120 A with V BAT = 300 V, and from 130 to 150 A with V BAT = 380 V.
All the controllers showed good current sharing between the IPT windings during the transients. As seen in Fig. 9, the settling time, t s(10%) , rise time, t r(10−90%) and overshoot, OS, of i a were measured and are summarised in Table 4. The PCM showed the fastest response, reaching the target current within a few switching cycles (Fig. 9). However, the percentage overshoot caused by this fast response is from five to ten times larger than that of the singlesampled ACM, which is the second fastest strategy. Table 4 also compares the performance of an analogue PCM simulated in SABER against the measurements of the digital PWM for the same operating conditions and compensating ramp values. It can be seen that the rise and settling times of the analogue PCM are shorter because there are no time delays. The measured rise time in the digital PCM was the same for both voltage conditions, giving an estimated controller bandwidth which approaches half the switching frequency.
The multi-sample ACM showed the slowest response. As a result, no overshoot was observed in the transients and the estimated bandwidth is <1% of the switching frequency. The response was worse at the minimum battery voltage condition because this condition is away from the design point. After the step current demand, the waveform i a (t) exhibited a high-frequency oscillation of 8.4 kHz, followed by a low-frequency oscillation of 838 Hz as it settled. These frequencies correlate well with the predictions from the small-signal averaged model (Fig. 6a).  Compared with the multi-sample ACM, the single-sample ACM response is from 2 to almost 16 times faster and it settles up to four times faster. These results confirm that the enhanced singlesample ACM control strategy offers a good trade-off between the response speed and overshoot compared with the other two methods. The rise time of the single-sample ACM degraded significantly with the operating condition, attributed to the effects of the frequency oscillation; however, the settling time and the overshoot were improved. The estimated controller bandwidth of the enhanced-single sample ACM is up to 12.4% of the switching frequency. After the current step, the averaged phase current waveform showed a high-frequency oscillation of 8.82 kHz followed by a lower frequency oscillation of 1.11 kHz. These frequencies match well the model predictions (Fig. 6b).  The performance of both ACM methods degraded at different steady-state operating conditions, suggesting that a programmed variation of the PI gains could benefit the converter transient performance when operating over wide voltage and current ranges. Furthermore, an on-line selection of the PWM control strategy could extend the converter operation at light loads -where the PCM ensures the current sharing even with discontinuous phase currents.

Conclusions
This work has presented the implementation, evaluation and comparison of three digital control methods for a dual-interleaved DC-DC converter. These were validated experimentally in a highfrequency, high-power DC-DC converter with SiC MOSFETs at power levels up to 60.5 kW at 750 V with a 75 kHz switching frequency. The conditions for stability were summarised, and the design process of the PI compensators was provided and validated experimentally.
The digital PCM has the fastest dynamic response, but it is unstable in the range 0.52-0.57 due to measurement noise in the current signals and the very low inductor current slope for duty ratios around 0.5. The multi-sampled ACM showed the best tracking of the current demand, but features the slowest response. Finally, the single-sample ACM exhibited an acceptable tracking of current demand and rapid dynamic response.
Fully understanding the advantages and drawbacks of the different digital control strategies is important for converters which have to operate with wide input/output voltage ranges and different load conditions, to enable acceptable steady-state and dynamic performance to be achieved and full use to be made of the MCU.