Reduced switch count-based N -level boost inverter topology for higher voltage gain

: This study proposes a new boost inverter based on a switched-capacitor concept with reduced switch count. The basic unit is a five-level topology, which inherently generates the AC output voltage with the self-voltage balancing of the capacitors. A conventional carrier-based sinusoidal modulation technique has been designed to maintain the capacitor voltage up to the input source voltage. The N -level structure of the proposed basic unit is also presented, which has the additional advantage of higher voltage gain with a single input. A detailed comparison with other similar topologies has been carried out. A laboratory prototype has been used to test the workability of the proposed basic unit and its extension for seven-level through several results.


Introduction
Multilevel inverters (MLIs) have been preferred for DC-AC power conversion due to its numerous and unique features like better output voltage performance in terms of harmonics, lower voltage stresses across switches etc. for high-and medium-power/voltage applications. MLIs found their applications in almost every field like renewable energy systems, distributed generation system, high-voltage DC applications, uninterruptible power supplies, industrial drive applications etc. cascaded H-bridge (CHB), neutral point clamped (NPC), and flying capacitor (FC) have been three elementary and standard MLIs topologies used and commercialised from the last few decades. With a lot of research and development, these topologies have reached their maturity level [1,2].
Recently, the topologies based on the switched-capacitor (SC) concept have gained a lot of attention from the researchers. Apart from the NPC which has the unbalancing of the capacitor voltages, and CHB which requires several isolated DC voltage sources, the SC-based MLI has several features like single source, self-voltage balancing, absence of magnetic components etc. The SC-based MLI can be categorised into two as boosting-type and nonboosting-type topologies. In non-boosting-type topologies, the boosting of the input voltage can be achieved with the help of DC/DC converter [3]. Wang et al. [4] presented a five-level (5L) active NPC inverter topology which uses seven switches, two diodes, and three capacitors. However, the limiting aspect of this structure has been the boosting factor of 0.5. A new 5L faulttolerant inverter has been recommended in [5], which is a hybridisation of H-bridge and one leg of NPC. However, the peak of the output voltage has a lower magnitude than the magnitude of the input voltage.
Several switched-capacitor multilevel inverter (SCMLI)s have been proposed in the literature with a higher boosting factor. Generalised structure of SCMLI-based boost inverter topologies has been proposed in [6][7][8][9]; however, for higher voltage gain, these inverters suffer from the increased number of component count. Several SCMLI-based topologies have been proposed for higher boosting ability while reducing the switch count. A 5L boost topology has been presented in [10] which employs nine switches for a voltage gain of two. Similarly, another 5L inverter has been reported in [11]; however, two capacitors of voltage rating equal to the input voltage source have been used for obtaining twice voltage gain. A 5L FC-based topology has been introduced in [12] which uses four capacitors and ten switches. The higher number of components makes this topology obsolete for practical applications.
In this paper, an effort has been done to propose an improved structure of the boost inverter with higher voltage gains using a lower number of components. Some of the main aspects of the proposed inverter are: • It uses a single input voltage and one capacitor for 5L with twofold voltage gain output voltage waveform. • The general structure of the proposed topology allows for higher levels. • Inherent reversing of polarity and self-balancing of the capacitor voltage. • Two switches of the topology are operated at a fundamental frequency (50 Hz).

Basic unit: 5L topology
The proposed 5L boost inverter topology is illustrated in Fig. 1. It consists of eight switches, one SC unit, and one input voltage source of magnitude V in which can be a photovoltaic array, fuel cell or battery. The switches S 3 and S 4 are configured as reverse blocking switch, i.e. an insulated-gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) in series with a diode and the remaining switches are configured as an IGBT or MOSFET with an anti-parallel diode. Two crossconnected switches, i.e. S 1 and S 2 need to block a voltage of 2V in with the other six switches of the voltage rating equal to the input voltage source. The proposed topology gives a boosting factor of two. In contrast to many other structures using the H-bridge for the generation of polarity, the proposed architecture has an inherent capability to generate both polarities of voltage. The voltage across the SC unit is equilibrated with a voltage magnitude of V in without the need for any sensor and therefore renders the proposed topology cost.

Proposed N-level topology
The proposed 5L topology can also increase the number of voltage levels (N) by connecting several modules of the SC unit. The generalised structure of the proposed topology is shown in Fig. 4a with the proposed SC module illustrated in Fig. 4b. For the inverter topology illustrated in Fig. 3a, the equations with N number of levels are: where N sw , N C , and G represent the switches count, capacitor count, and voltage gain of the proposed topology, respectively.

PWM strategy for the proposed 5L topology
For the control of the switches of the proposed inverter, the levelshifted pulse width modulation (LS-PWM) technique has been applied. With the 5L output voltage, four high-frequency carrier signals i.e. V cr1 -V cr4 are compared with a sinusoidal reference signal V sine , having a frequency of the output voltage waveform. All the four carrier signals are shifted on the vertical axis with a magnitude of A c , which is peak-to-peak magnitude of each carrier signal. Fig. 5 shows the LS-PWM technique for the proposed 5L topology. The gate pulses are generated using the logic given in Table 2. The modulation index (M) for the LS-PWM technique can be defined as  Table 1 Switching combinations of the proposed 5L MLI where V s is the peak magnitude of the reference sinusoidal signal V sine .

Capacitor sizing
The determination of the size of the capacitor has an important parameter to be considered for the SC-based topologies. The ripple voltage of the switched capacitor mainly depends on load current which is the discharging current for the SCs. Based on peak load current I peak , the ripple voltage ΔV C can be calculated as where θ is the maximum discharge angle, f o is the fundamental frequency of the output voltage and C is the capacitance value of the SC unit. Fig. 6 relates the deviation of the capacitor voltage ΔV C with the output voltage in the worse voltage condition with the carrier signals replaced by a DC line having an average magnitude of it. The capacitor voltage decreases during the voltage level of 2V in ; however, it regains the magnitude of input voltage V in during the charging of the capacitor with voltage levels of V in and zero. Due to the symmetrical operation of charging and discharging of the capacitor C, the voltage across it remains balanced.

Comparison analysis
In order to distinguish the advantages of the proposed 5L inverter, Table 3 has been accomplished in terms of different parameters associated with a boost inverter topology as given in Table 3. For the comparison, the topologies with 5L output voltage waveforms have been considered. From the comparison table, the conventional topologies NPC and FC have one major disadvantage of lower voltage gain with a higher number of passive components and switches. The topology proposed in [6,8,9] requires six switches; however, the topology proposed in [9] requires an H-bridge with higher voltage switches and topology presented in [8] requires two capacitors. Similarly, the topologies proposed in [10][11][12] require a higher count of power semiconductor components and capacitors    for the 5L. Similarly, the topology presented in [12] requires four capacitors for 5L output voltage. The proposed topology requires less power semi-conductive devices than the topologies proposed in [7,[10][11][12]. Similarly, the proposed topology requires only one switched capacitor unit for 5L output voltage; however, the topologies proposed in [8,11,12] require more than one capacitor for 5L. From these comparisons, the proposed basic unit with 5L is superior to the similar structures listed in Table 3. One of the important parameters for the MLI topology is the cost. A cost function (CF) to explain this has been defined considering the effects of different constraints are as follows: where α and β are the factors associated with TSV and MBV factors against semiconductor count, respectively. Where TSV and MBV are more important than the device count, the value of α, β > 1. If TSV and PIV are insignificant to the device count, α and β < 1. Table 3 gives the CF for different topologies and the proposed topology has the least CF compared to all other topologies. On the other side, the major short coming of the proposed MLI topology is the floating DC bus for getting multilevel voltage output.

Results and discussion
The validation of the proposed boost inverter is done with the laboratory prototype. This prototype is realised with G60N100 switches, 2200 µF electrolytic capacitor (PG6DI) and DC power supply with 100 V. The switching frequency has been set as 5 kHz.
The gate pulses to drive the proposed boost inverter are generated from the Vertix-5 FPGA control board (XC5VLX50T). Fig. 7 illustrates the hardware prototype of the recommended inverter topology. The proposed inverter topology has been tested for 5L and 7L. Fig. 8a presents the experimental results for change of resistive load from 150 to 75 Ω with a unity modulation index. As observed from this waveform, the output voltage is 200 V (peak) for an input voltage of 100 V since the proposed inverter amplified the voltage by two times. Further, it can be seen that the voltage of the capacitor is stable and matches the input voltage and step change in load does not affect the stability of the capacitor voltage.
The experimental results for RL load (150 Ω and 80 mH) with a unity modulation index of the proposed topology with 5L are shown in Fig. 8b with load parameters of 150 Ω and 80 mH. The experimental results during a step change in power factor (R load to RL load) are presented in Fig. 8c, where the load is changed from 150 Ω to 150 Ω + 80 mH. Fig. 9a illustrates the voltage and current of the capacitor for RL load with a unity modulation are presented. For clear visualisation the voltage ripple of the capacitor, in Figs. 8a and b, and the voltage of the capacitor are  shown with a base of 90 V and volt/division is 4 V, but the average capacitor voltage is 98. The proposed inverter topology has also been tested with 7L output voltage using two switched capacitor units. Fig. 9b shows the experimental results with a resistive load of 150 Ω. Both capacitor voltages are stable at 100 V with the maximum voltage of the output waveform being 300 V. The results under step change in RL load (two RL loads are connected in parallel) of the proposed inverter are shown in Fig. 9c. All figures of Figs. 8 and 9 are evidence that the proposed inverter can work for a different step change in loads with boosting features and maintaining the selfbalancing of the capacitor voltages.

Conclusion
This paper suggested an inverter topology with the characteristics of boosting of the input voltage, inherent voltage balance, and a reduced blocking voltage of the switch. The SC-based inverter proposed in this paper, with these attractive features, offers effective circuit and performance upgradation for DC-AC power conversion systems of high quality. The detailed comparative study has reinforced the superiority of the recommended inverter compared to related prior-art inverters for various conditions. The results obtained through laboratory prototype of the proposed inverter topology with 5L and 7L output voltage confirmed the validity with regard to an extensive range of real-time operational environments.

Acknowledgments
This publication was made possible by Qatar University-Marubeni Concept to Prototype Development Research grant # [M-CTP-CENG-2020-2] from the Qatar University. The statements made herein are solely the responsibility of the authors.