Impact of body biasing on the retention time of gain-cell memories

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain-cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic-compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain-cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.


Introduction
Embedded memories are a crucial building block of virtually all modern systems-on-chip, and account for an increasing share of area and power [1].Gain-cell-based embedded DRAM (eDRAM) has recently gained significant popularity as a potential successor of conventional mainstream SRAM, primarily because of its higher integration density, inherent two-port functionality, decoupled read and write ports (for improved robustness) and logic compatibility [2].The application field of gain-cell-based eDRAM is broad, ranging from high-speed caches in microprocessors [1] to ultra-low power systems [3].The main drawback of gaincell memories is the need for periodic refresh cycles, which results in a considerable amount of power consumption and limits the read/ write availability.Therefore, to improve the competitiveness of gain-cell eDRAM, it is crucial to extend the data retention time.
Data levels in eDRAM are stored as charge on an in-cell storage node (SN) capacitance (C SN ) and therefore data retention is limited by the time it takes for this charge to leak away.Several simple measures can be taken to extend the retention time, such as: (1) increasing C SN through layout techniques [3,4]; (2) minimising the subthreshold conduction through the write access transistor (MW) by using low-leakage MOS transistors [5]; and (3) employing write bitline (WBL) control schemes to minimise charge loss through MW [6].An additional technique that has not yet been applied to gain-cells is threshold voltage (V T ) adjustment through body biasing (BB).While the application of a reverse BB (RBB) raises V T and therefore reduces the charge loss through subthreshold conduction, this means of control can also improve the array availability by applying a forward BB (FBB) during refresh cycles to reduce access time [7].

Contributions
For the first time, this Letter proposes reverse BB as a technique to improve the retention time of gain-cell memories and demonstrates its high effectiveness by means of silicon measurements.Moreover, the retention time penalty of forward BB, used for fast memory access and short refresh times, is evaluated.

Bitcell design
Fig. 1a shows the schematic and the basic operation of the twotransistor (2 T) all-PMOS gain-cell used in this study (a similar cell has previously been proposed in [5]).MW is used to transfer the data driven onto the WBL to C SN .The read access transistor (MR) is used to read out the data level stored in the bitcell.A write access is initiated by applying an underdrive voltage (-V NWL ) to the write wordline (WWL) in order to properly transfer a logic '0' level (V SS ) from WBL to SN in a short time.A read access is initiated by pre-discharging the read bitline (RBL) and subsequently raising the read wordline (RWL).If a logic '0' is stored on C SN , MR will charge RBL past a detectable threshold, whereas if a logic '1' (V DD ) has been written to the SN, RBL will remain discharged.The basic C SN is increased by building up side-wall capacitors between the SN and a constant potential (V DD ) atop the bitcell footprint, using all six available metal layers.
The dominant leakage mechanism that causes the deterioration of the stored data levels is clearly the subthreshold conduction of MW.This is especially true for mature CMOS nodes, such as the 0.18 μm process used in this study, but also holds for a deeply scaled 40 nm CMOS node [6].In order to achieve the longest possible retention time, an I/O PMOS transistor is used to implement MW, as this device features the lowest subthreshold conduction among all devices offered in the chosen 0.18 μm CMOS technology [3].By implementing MR with a PMOS device, as well, the entire array resides in an equi-potential n-well, enabling simple control over the body voltage (V B ) of the bitcells.Reverse biasing the n-well at a voltage above V DD increases the V T of the transistors, thereby suppressing the subthreshold conduction of MW and improving the retention time.Likewise, forward biasing V B below V DD lowers the V T of the transistors, resulting in faster read and write access times.The variable ΔV B is used to express the amount of BB, according to V B = V DD + ΔV B , where positive and negative values of ΔV B correspond to RBB and FBB, respectively.In this study, a biasing range of -250 mV < ΔV B < 125 mV is considered, corresponding to a V T range of -770 mV < V T < -625 mV for a PMOS I/O device under otherwise nominal conditions with V DD = 750 mV.
3 Macrocell architecture and test chip design Fig. 1b shows the layout of the 2 kb gain-cell macro memory in 0.18 μm CMOS technology.The core bitcell array consists of 64 × 32 gain-cells, all sharing the same n-well and V B .n-Well contacts are provided every 16 rows, as well as at the top and the bottom of the array.In addition to the bitcell array, the macrocell comprises the following peripheral circuits: (1) a write address preand post-decoder that drives V DD or -V NWL onto WWL; a read address pre-and post-decoder that drives V DD or V SS onto RWL, level-shifters, WBL drivers, readout sense buffers and timing control units.
Fig. 1c shows a microphotograph of the manufactured test chip.In addition to the 2 kb gain-cell macrocell in the lower left corner, the chip contains a built-in self test (BIST) unit.The main features of the BIST can be summarised as follows: (1) address sequence generation (increasing, decreasing and pseudo-random); (2) data pattern generation (checkerboard, pseudo-random and all-'1', all-'0'); (3) programmable refresh period of the memory under test (MUT); (4) pass/fail decision during readout of the MUT; (5) SRAM for storing maps of MUT retention time, read failures, or write failures; and ( 6) support for two-port operation of the MUT.Finally, the test chip also contains scan chains for full access to the MUT with any data or address sequence pattern independent of the BIST.

Silicon measurement results
The packaged test chips were mounted on a test board by means of a burn-in socket and connected to a TMPC PG3A pattern generator and a Tektronix TLA6403 logic analyser.The main supply of the memory macrocell was set to 750 mV, and the body voltage V B was swept from 500 to 875 mV to analyse the impact of BB.A separate negative voltage of -1.5 V was supplied to the macrocell for the WWL underdrive.The BIST and other digital control units were supplied with the technology's nominal voltage of 1.8 V.Both the write and read access times were set to 1 μs for robust write and read operations, even at the low V DD of 750 mV.This ensured that the measured failures relate to retention time, and were not caused by incomplete writes or erroneous reads because of insufficient access time.
Measurements indicate that the two-PMOS gain-cell retains logic '1' levels for extensive periods ( > 1 s), even when the WBL is held at 0 V (which maximises the subthreshold conduction of MW).This coincides with previous reports that logic '1' levels decay very slowly because of the increasing reverse gate overdrive and body effect of MW as the SN voltage drops [3].Therefore the gaincell's retention time is almost exclusively limited by its ability to hold a logic '0' level.The decay of a cell's logic '0' level is heavily dependent on the state of the WBL.On the one hand, when WBL is low, subthreshold conduction through MW discharges the SN, reinforcing a stored logic '0' level.On the other hand, when WBL is high, a worst-case condition occurs, as leakage through MW causes accelerated decay of a stored logic '0' level.Our measurement setup assumes a 50% write duty cycle (i.e.there is a write access during 50% of the time) and that the probability of writing a '1' (which requires pulling WBL up to V DD ) is 50% as well.Overall, this leads to a write-'1' disturb activity factor (α disturb ) of 25%.
Using the measurement setup described above, retention time was measured for the entire 2 kb array under standard biasing conditions (i.e.V B = V DD = 750 mV) at room temperature (temperature was not controlled).The results of this measurement are shown in Fig. 2a.The minimum and maximum retention times (t ret ) of 2048 measured gain-cells were found to be 23 and 569 ms, respectively, corresponding to a ratio of 25 between the maximum and minimum values.A recent study [8] reports an even higher ratio of over 50 between the maximum and minimum measured retention times in an 1 kb array implemented in 65 nm CMOS.In the present study, the majority of the cells exhibited retention times in the range of 20-200 ms (dark and light blue colours), whereas a small number of cells exhibited considerably higher retention times (yellow, orange and red colours).In order to better visualise the differences among the lower retention times (20-200 ms), Fig. 2b plots t ret on a logarithmic scale.There is no systematic pattern, indicating that the retention time variability arises from local (withindie), random process parameter variations.
The impact of BB on the measured retention times was evaluated by sweeping V B from 500 to 875 mV (−250 mV < ΔV B < 125 mV).The minimum and maximum measured retention times across the entire array are plotted in Fig. 3a.This figure clearly shows that the minimum and maximum retention times change by up to two orders of magnitude over this 375 mV V B range.As expected, the best cells with the highest retention time remain at the same location under varying V B (not shown in the figure).
Finally, Fig. 3b shows the distributions of the retention time across the 2 k measured cells, for three biasing conditions: 100 mV FBB, standard BB (SBB) (i.e.V B = V DD ) and 100 mV RBB.The minimum retention time for each biasing condition is annotated, as well.The spread of retention time across the array is large; however, there is a clear improvement in the minimum, as well as in the average retention times with each 100 mV increase in the BB, illustrating the effectiveness of the proposed technique.

Conclusions
This study showed the impact of body biasing (BB) on the retention time of an all-PMOS 2 T gain-cell topology in a mature 0.18 μm CMOS technology.The measured retention time of a 2 kb memory macrocell is improved by 2.3 × (from 23 to 53 ms) with a RBB of only 100 mV.The cell-to-cell retention time variability is high, ranging from 23 to 569 ms under standard body biasing (SBB); the absence of a systematic pattern in the measured retention time maps suggests that the high variability is caused by local parametric variations, which are particularly high in memory arrays because of the use of minimum-size devices.Moreover, the process parameters of I/O devices, used to achieve high retention times, may be less carefully controlled than those of core transistors.Nevertheless, RBB is an attractive technique to improve the minimum (as well as the average) retention time.
At the same time, the retention time penalty for FBB (used for fast memory access) is high, exhibiting a 2.9 × reduction for 100 mV FBB.However, a possible control scheme could dynamically apply an RBB during retention periods and an FBB during refresh cycles to maximise array availability.Overall, sweeping the body voltage over a range of 375 mV provides an interesting trade-off between access and retention time, with the retention time range spanning almost two orders of magnitude.

Acknowledgments
This work was kindly supported by the Swiss National Science Foundation under the project number PP002-119057.P. Meinerzhagen is supported by an Intel PhD fellowship.

Fig. 1 Fig. 2
Fig. 1 Bitcell, macrocell and test chip a 2 T gain-cell design and basic operation b Layout of 2 kb gain-cell memory macro c Microphotograph of test chip

Fig. 3 V
Fig. 3 V DD = 750 mV with α disturb = 25% at room temperature a Minimum (t ret,min ) and maximum (t ret,max ) retention times across the entire 2 kb array, as a function of ΔV B b Retention time distributions of 2048 measured gain-cells for 100 mV FBB, SBB and 100 mV RBB