Effect of atomic layer deposited ultra-thin SiO 2 layer on vapour-liquid-solid (VLS) grown high dielectric TiO 2 ﬁlm for Si-based MOS device applications

There has been continuous development of Si-based metaloxide semiconductor field effect transistors (MOSFETs) in the last few decades, which has been possible due to the availability of natural gate oxide (SiO2) and its suitable mechanical, elastic and electronic properties. Utilizing benefits of Si with advance technologies, there has been a continuous scaling down in the successive nodes of complementary-metaloxide-semiconductor (CMOS) technology. Due to such aggressive scaling, the thickness of gate dielectric has been reduced to a few atomic layers, consequently increasing the leakage current to unacceptable level. However the constant demand for smaller device with an increase of data rate for mobile computing requires a continuous improvement of low power devices with high speed of operation. Thus, continuous efforts are made to replace SiO2 as gate dielectric by high-k dielectrics such as, TiO2, Al2O3, Ti2O5, La2O3, ZrO2, Y2O3, HfO2 etc. thereby, increasing the physical oxide thickness. Higher oxide thickness helps to reduce static power dissipation by reducing the gate leakage current which provides better control over the gate [1–3]. TiO2 as a gate dielectric has huge potential for its high dielectric constant of 10–100, high resistivity of 1019–1024 ohm m, thermal stability, and abundance in nature due to its presence in several kinds of rocks and mineral. It also presents a superior Si–dielectric interface state density, during the growth process at high temperature it can be segregated and produce SiO2 and metallic oxide. To get rid of this problem a thin layer of SiO2 is deposited over Si, so that the performance of the device can be improved with the same interface quality [1–7]. TiO2 is found in three crystalline forms: anatase, rutile and brookite. Among them brookite is the least explored crystalline form [8]. To the best of our knowledge till date no work is reported on electrical characterization and reliability study for the brookite TiO2 gate dielectric MOS structure on Si substrate with atomic layer deposited (ALD) amorphous SiO2 passivation layer by employing vapour-liquid-solid (VLS) process. So in the present work, the mentioned study has been done on


INTRODUCTION
There has been continuous development of Si-based metaloxide semiconductor field effect transistors (MOSFETs) in the last few decades, which has been possible due to the availability of natural gate oxide (SiO 2 ) and its suitable mechanical, elastic and electronic properties. Utilizing benefits of Si with advance technologies, there has been a continuous scaling down in the successive nodes of complementary-metaloxide-semiconductor (CMOS) technology. Due to such aggressive scaling, the thickness of gate dielectric has been reduced to a few atomic layers, consequently increasing the leakage current to unacceptable level. However the constant demand for smaller device with an increase of data rate for mobile computing requires a continuous improvement of low power devices with high speed of operation. Thus, continuous efforts are made to replace SiO 2 as gate dielectric by high-k dielectrics such as, TiO 2 , Al 2 O 3, Ti 2 O 5 , La 2 O 3 , ZrO 2 , Y 2 O 3, HfO 2 etc. thereby, increasing the physical oxide thickness. Higher oxide thickness helps to reduce static power dissipation by reducing the gate leakage current which provides better control over the gate [1][2][3].
TiO 2 as a gate dielectric has huge potential for its high dielectric constant of 10-100, high resistivity of 10 19 -10 24 ohm m, thermal stability, and abundance in nature due to its presence in several kinds of rocks and mineral. It also presents a superior Si-dielectric interface state density, during the growth process at high temperature it can be segregated and produce SiO 2 and metallic oxide. To get rid of this problem a thin layer of SiO 2 is deposited over Si, so that the performance of the device can be improved with the same interface quality [1][2][3][4][5][6][7]. TiO 2 is found in three crystalline forms: anatase, rutile and brookite. Among them brookite is the least explored crystalline form [8]. To the best of our knowledge till date no work is reported on electrical characterization and reliability study for the brookite TiO 2 gate dielectric MOS structure on Si substrate with atomic layer deposited (ALD) amorphous SiO 2 passivation layer by employing vapour-liquid-solid (VLS) process. So in the present work, the mentioned study has been done on the least studied VLS grown brookite TiO 2 ultra-thin film gate dielectric MOS structure, with and without ALD SiO 2 passivation layer. The film quality and structural properties of the as-grown TiO 2 films are studied by using scanning electron microscope (SEM) images and X-ray diffraction (XRD) measurements, respectively. The electrical characterization of the TiO 2 /SiO 2 /Si and TiO 2 /Si MOS capacitors is performed by the C-V and I-V measurements.

EXPERIMENTAL DETAILS
Thin films of ≈13 nm TiO 2 are grown on SiO 2 /Si and Si substrates by employing VLS technique. Prior to growth, p-type Si substrate is cleaned by standard (RCA) cleaning process. A thin layer of metal catalyst (in this case, Gold (Au)) of ≈7 nm, is deposited on the SiO 2 /Si and Si substrate by sputtering technique. After Au coating, samples are placed in a dual-zone furnace. The sample is kept at 600 • C, in order to form eutectic melt. The temperature is so chosen, such that the formation of Au island, due to phase separation can be minimized. Au acts as a catalyst in this technique and thus controls the growth. Without the use of Au, growth process will not be possible. In the case of thicker Au coating, larger amount of resource is needed to achieve super saturation of TiO 2 vapour and hence rise in the deposited oxide film thickness will also occur. So, ≈7 nm Au coating is adequate to grow ≈13 nm TiO 2 thin film. Mixture of TiO 2 and graphite, proportionate to their atomic weights, is kept in the other zone of the furnace at a comparatively higher temperature in order to form vapour, so that it can be carried by Argon (Ar) flow at 183.9 Torr, and get absorbed by the liquid alloy and the alloy gets supersaturated. The furnace is maintained at the growth temperature for 30 min, and then cooled down slowly. The growth process is stimulated by the components of the vapour which form precipitate at the liquid-solid interface. Aluminum (Al) gate electrode is deposited by thermal evaporation method on TiO 2 film. Electrical characterization of the sample is done with Keithley-4200 SCS parameter analyser. Structural analysis and crystallographic orientation of the

RESULTS AND DISCUSSION
SEM images of the as-grown ultra-thin TiO 2 film tilted at ≈75 • are shown in Figure 1, where in Figure 1(a) SEM image of the sample with SiO 2 passivation layer in between Si and TiO 2 and in Figure 1 Figure 2 at 2θ = 33.5 • , 61.7 • and 75.7 • respectively, which are consistent with the JCPDS card no. 82-1123 [9]. So, it can be concluded from the dominant peaks in XRD pattern that brookite TiO 2 films are formed on both the substrates. A wide peak is also observed from Figure 2(a), which is due to the presence of ALD amorphous SiO 2 [10].
Average crystallite size (D) is measured by using Debye-Scherrer's formula [3]: where, k (≈0.9) is a constant, λ (0.015406) is the X-ray wavelength, β is the FWHM (full width at half maximum) and θ is diffraction angle. Crystallite size calculated by using Equation (1) is listed in Table 1. Report suggests that brookite with crystallite size greater than 11 nm is more stable compared to anatase [8]. In comparison to other reported crystallite size of brookite TiO 2 of ≈50 nm [11] and 3.4-19.8 nm [12], crystallite size achieved in the present work is remarkably high, which suggests uniform film.
The SE measurement has been used to measure the thickness for both the samples. The relevant model structures are considered to be Air/TiO 2 /SiO 2 /Si and Air/TiO 2 /Si. The optical constants of air and the wavelength of incident light have been considered to remain constant in the fitting process. Thickness of TiO 2 films for samples with and without SiO 2 is found to be 12.51 and 12.75 nm, respectively.
A useful technique to understand the interface quality is C-V characterization. So, the C-V measurement has been performed at 100 kHz for TiO 2 /SiO 2 /Si and TiO 2 /Si MOS capacitors and plotted in Figure 3 for both as grown samples. Vertical (black) arrows in Figure 3(a,b) indicate forward and reverse sweep direction. C-V characteristics for TiO 2 /Si sample (Figure 3(b)) is found to be more stretched through the voltage axis compared to the TiO 2 /SiO 2 /Si sample. Therefore it can be observed that the occurrence of donor and acceptor like interface traps, existing in a section of the semiconductor band gap is more for the TiO 2 /Si sample [1]. Thus, introducing SiO 2 layer in between TiO 2 and Si improves the surface quality by reducing the interface traps (Figure 3(a)). The existence of interface traps and/or mobile charges within the oxide layer is also confirmed by the hysteresis voltage. It has been observed that incorporation of SiO 2 passivation layer reduces the hysteresis voltage significantly (as shown in Figure 3(a,b) with horizontal (blue) arrows, thereby improving the interface quality. TiO 2 /SiO 2 /Si sample exhibits a much smaller hysteresis voltage of 0.34 V in comparison with TiO 2 /Si sample which shows comparatively higher hysteresis voltage of 1.32 V. Dielectric constant calculated from accumulation capacitance for the TiO 2 /SiO 2 /Si and TiO 2 /Si sample at 100 KHz are found to be 44.5 and 35.8, respectively. The larger dielectric constant for the former sample may be due to the suppression of the lossy dielectric layer in between TiO 2 film and Si substrate by incorporating SiO 2 passivation layer. Dielectric constant achieved in the present work is comparable to other reported data of 14-65 [1], 24-33 [3], 31-78 [13] and 32-60 [14]. The C-V characteristics are simulated by using a device simulator, SILVACO and are shown in Figure 3(c,d). The Shockley-Read-Hall (SRH) and CVT mobility models along with interface trap modelling have been included in the simulation. The simulated characteristics match well with the experimental data. It is to be noted that, the thickness and dielectric constant of the dielectric layer, and the interface trap density from simulation are in agreement with the experimentally extracted values.
Owing to the interface traps formed at the interface of the substrate and oxide, frequency dispersion is observed for both the samples in the C-V characteristics, and is shown in Figure 3(e,f). Frequency dispersion for TiO 2 /SiO 2 /Si sample (Figure 3(e)) is observed to be very small in comparison to the TiO 2 /Si sample (Figure 3(f)); thereby establishing the fact that the former sample has lower interface traps [1]. The capacitance of the lossy dielectric layer acts in series with the capacitance of the TiO 2 layer, which causes frequency dispersion in the accumulation region. Thus it can be observed that incorporation of SiO 2 layer improves the interface quality by reducing the interface traps.
The leakage current versus applied voltage plot is shown in Figure 4. It can be seen from Figure 4 that leakage current has been lowered for the device with SiO 2 passivation layer, due to the increase in physical oxide thickness as well as improvement of the interface. TiO 2 /SiO 2 /Si device exhibits a leakage current of ≈8.61 × 10 -8 A/cm 2 , whereas TiO 2 /Si device gives a leakage current of ≈4.05 × 10 -6 A/cm 2 at a gate voltage of +2 V. Kahraman et al. [6] reported Gd 2 O 3 /SiO 2 /p-Si MOS structure with 118 nm Gd 2 O 3 and 5 nm SiO 2 layer, which exhibits ≈10 -5 A/cm 2 leakage current at a gate voltage of +2 V. Whereas the MOS structure in the present work of TiO 2 /SiO 2 /Si with ≈13 nm TiO 2 on 5 nm SiO 2 shows much lower leakage current. As-deposited TiO 2 thin film of ≈10 nm grown on p-GaAs substrate by employing VLS method reveals leakage current of ≈10 -2 A/cm 2 at +2 V gate voltage, is reported by Das et al. [1]. Furthermore, annealing at 625 • C reduces the leakage current to ≈10 -5 A/cm 2 . Other reported data of TiO 2 thin film exhibited leakage current at +2 V gate voltage of ≈10 -5 A/cm 2 on p-Si [3] and ≈10 -7 A/cm 2 on n-Si substrate [15]. Thus, the leakage current for both the proposed samples are within the acceptable range for MOS device fabrication.
Mostly Fowler-Nordheim (FN) tunnelling, Poole-Frenkel (PF) tunnelling and Schottky emission are the transport mechanism found through the oxide layers [16].To know the dominant transport mechanism of TiO 2 /SiO 2 /Si sample, the leakage current is plotted and it shows a linear fit with FN tunnelling mechanism at low field (Figure 4(c)) and PF tunnelling at high field (Figure 4(b)), whereas dominant transport mechanism of the second sample (TiO 2 /Si) is a linear fit with Schottky emission at the low field (Figure 4(d)) and PF tunnelling at high field (Figure 4(b)) [1,16]. It can be noticed from Figure 4(b) that, PF tunnelling is higher for the TiO 2 /Si sample. This might be due to the trap-assisted tunnelling owing to the generation of oxygen vacancies in TiO 2 during the growth process [1]. So, it can be concluded that SiO 2 layer incorporation in between TiO 2 and Si substrate makes the interface of TiO 2 and SiO 2 /Si better with lesser oxygen vacancies in TiO 2 .
Dielectric constant and equivalent oxide thickness (EOT) of TiO 2 film for both the samples are calculated using conventional formulas and are listed in Table 2 along with hysteresis voltage, TiO 2 film thickness and leakage current.
Another way to understand the interface quality is by studying the interface traps. High-k dielectrics produce significant number of interface traps which may degrade the electrical performance of the MOS device [17]. Lower interface traps signify superior interface. Figure 5 shows interface trapped (D it ) charge density for both the samples. D it is calculated by low frequencyhigh frequency of C-V measurement technique [18], given by the following Equation (2): It can be seen from the plot that number of interface traps has been reduced significantly for the sample with SiO 2 passivation layer. So, it can be concluded from the plot that a better interface is achieved with the introduction of SiO 2 layer.
To ascertain the device stability, reliability study is done under constant voltage and current stressing. Flat-band voltage shift

CONCLUSION
TiO 2 thin film of ≈13 nm thickness on Si <400> substrate with high dielectric constant and good reliability can be grown by employing cost effective VLS technique on Si substrate, with and without 5 nm ALD SiO 2 passivation layer. Incorporation of ALD SiO 2 layer makes significant improvements in the electrical characteristics and reliability of the device, which can be used to get superior quality MOS devices. XRD and SEM images reveal high quality crystalline TiO 2 films with corresponding substrates. XRD study reveal brookite TiO 2