Implementation of all‐optical Toffoli gate by 2D Si–air photonic crystal

University Grants Commission (Government of India); Department of Physics, The University of Burdwan Abstract The quantum Toffoli gate is one of the essential reversible universal logic gates widely used for optical data processing. Herein, a new scheme of developing all‐optical Toffoli gate using a two‐dimensional silicon–air photonic crystal is proposed. For the realization of the Toffoli gate, the principles of constructive and destructive interference of light are used. The Toffoli gate comprises two‐input–three‐output‐based optical AND gate, and a two‐input–one‐output optical XOR gate. Two Y junction power splitters have been used at the two inputs of the AND gate. The operating wavelength of the proposed Toffoli gate is 1550 nm along with the wafer size of 50 μm � 50 μm. The performance of the Toffoli gate has been analysed and simulated by the plane‐wave expansion method and finite‐difference time‐domain method. The response time and contrast ratios are also obtained from the simulation. The proposed Toffoli gate is intensity encoded with no non‐linear material within the crystal which shows significant improvement over other proposals.

in symmetric configuration with an extinction ratio of 18.57 dB and Q factor of 38.10 dB used the cross-gain modulation and cross-phase modulation phenomenon to get the changes in the carrier density and refractive index of the material [11]. Quantum gates with quantum dots using single-sided optical microcavities have also been proposed, which use the giant optical Faraday rotation technique induced by a single electron spin [36]. All-optical Toffoli gates using coupled-resonator optical waveguides (CROWs) have been reported that generate a strong non-linear interaction that helps the implementation of a single-and two-qubit quantum gates [37].
Herein, the all-optical Toffoli gate was designed and simulated. The designed Toffoli gate has been implemented using a 2D PC composed of silicon (Si) rods in the air. All-optical Toffoli gate has been based on light interference effect and gives low power consumption. The performance of the Toffoli gate has been analysed and simulated by the plane-wave expansion method (PWE) and the finite-difference time-domain (FDTD) method. The proposed gate uses no non-linear material within the crystal.

| DESIGN OF THE ALL-OPTICAL TOFFOLI GATE
All-optical Toffoli gate using a 2D PC comprising silicon rods in the air has been implemented. It is a three-qubit gate with three inputs and three outputs. Toffoli gate has two control bits, and a third bit as the target signal. When both the control bits are in the logic state '1', the target bit changes or complements favouring a NOT operation. It is observed that when both the inputs (I 1 and I 2 ) takes the logic state '1', the third input (I 3 ) is complemented at the output [23][24][25]. It is an interference-based logic operation; if there is constructive interference of light, the output has been taken as ON state that shows the logic state '1' for the normalised intensity of 0.35 or above. For output OFF state, that is, for the logic state '0' will occur due to destructive interference of input light with normalised intensity below 0.25. For intensity-based logic, contrast ratio CR (10 log P 1 P 0 ) is defined as the logarithmic ratio of ON (P 1 ) to OFF (P 0 ) output power where P 1 and P 0 are output power levels corresponding to the logic '1' and logic '0'. It is better to have a high contrast ratio or ON to OFF ratio. Destructive and constructive interferences between the inputs signals provide low-and high-output power levels corresponding to the logic '0' and the logic '1' [4]. Therefore, reducing the output power level (P 0 ) further increases the CR. This CR can be controlled by the proper change of the silicon rod dimensions in the interference points in the crystal.
Being intensity-based logic, it has the advantage of the stageby-stage cascading with proper fan-out. An AND gate and an XOR gate have been cascaded to get the Toffoli logic [25]. The principle of constructive and destructive interferences of light has been used to design the AND XOR logic [4]. The symmetric layout for the proposed Toffoli logic is shown in Figure 1. Here we have three inputs marked as I 1 , I 2 , and I 3 and three outputs marked as O 1 , O 2 , and O 3 and two Y junction power splitters at the inputs of I 1 and I 2 . Many researchers have reported the concept of schematic layout of Toffoli gates with the help of AND gate and XOR gate work [28,29]. The output of the AND gate is treated as an input to the XOR operation. Outputs O 1 and O 2 are simply taken from the inputs I 1 and I 2 , respectively. The output of the AND (I 1 , I 2 ) is XOR-ed with the input I 3 to obtain the output O 3 .The truth table for the implementation of the Toffoli logic is given in Table 1.
The novelty of the current proposal is to develop a Toffoli gate that is very small in size (50 µm � 50 µm) PC wafer operated at 1550 nm wavelength without non-linear element within the crystal.
The use of the PC ensures that the implementation of the Toffoli gate in a minimal system volume with very low light intensity. As the gate inputs and outputs are intensity encoded, conditional and sequential gate systems can also be organised.

| SILICON-AIR TWO-DIMENSIONAL PHOTONIC CRYSTAL
The designed 2D silicon-air PC has a wafer dimension of 50 µm � 50 µm with 43 � 35 silicon rods in a square lattice.The lattice constant of the crystal is 670 nm and the refractive index of the silicon is 3.49. The r/a of the silicon rods is 0.2 where r is the radius of the rods and a is the lattice constant. The band gap of the unperturbed lattice for TE polarisation is shown in Figure 2 which exists for the value from 0.348693 to 0.449631. The corresponding wavelength to the band gap is 1490-1921 nm. The wavelength used for the simulation of the Toffoli gate is 1550 nm.

| IMPLEMENTATION OF TOFFOLI GATE
For its implementation, two power splitters (PS), PC-based AND gate, and XOR gate are essential [4,20].

| Power splitter
The layout of a Y branch PS ( Figure 3) is designed with an input port and two output ports. Three rows of the silicon rods have been removed to create line defects to design the Y branch PS. The input signal at the input port is divided into two channels, which gives the output of the power splitter at Port A and Port B. There are 21 � 21 silicon rods with r/a 0.2 and lattice constant 670 nm. The performance of the designed Y junction PS can be seen in Figure 4. The normalised output at Port A is 0.45 and at port B is 0.45 at the wavelength of 1550 nm. Two PSs of the same design and performance have been used in the proposed Toffoli gate.

| Design of AND gate
The all-optical AND gate has been designed with two input ports and three output ports. In the layout of the AND gate shown in Figure 5, where two PSs have been used, one each for the two inputs (I 1 and I 2 ). There are three outputs (O 1 , O 2 , and O 3 ). The outputs, O 1 and O 2 correspond to the inputs I 1 and I 2 , respectively, and the output O 3 is from the AND operation of I 1 and I 2 . The gate is implemented with silicon-air 2D PCs.
The waveguides have been created in the crystal with the help of line defects by removing an entire row of the silicon rods [12]. The 1550-nm-wavelength light wave can propagate through this waveguide. If there are no extra rods, the intensity of the light wave at the output port should be the same as the input port for a two-port waveguide. In case of the AND gate, at the junction, there are two sets of rods r 1 and r 2 . The r/a ratios of r 1 and r 2 are 0.05 and 0.02, respectively. The normalised intensity available at the output port can be adjusted with these extra rods. The transmission to the output port can be increased or decreased by reducing or enlarging the radius of the rods, respectively. In case there are no extra rods, the intensity of the light wave at the output port should be the same as the input port [4,[12][13][14]. So, in this case, these are reflector rods which help in optimising the transmission and achieve a better contrast ratio. Line defects have been created to design the PS and the output ports of the AND gate. The design of the AND gate is shown in Figure 6. The AND gate is at the T junction of the three arms of the two inputs and the output port (O 3 ). These rods have been inserted to control the transmission of the light towards the output ports. The proposed design of the rods in the AND gate is optimising the transmission for logic '0' and achieve a high contrast (ON-OFF) ratio. The path length of both the inputs (I 1 and I 2 ) is the same, and hence at the T junction, constructive interference takes place. With only one input present (I 1 = 1 and I 2 = 0), because of the presence of the rods r 1 and r 2 , it gives transmission at the output O 3 corresponding to the logic level '0'. With both the inputs present (I 1 = I 2 = 1), the strength of the signal at the output port corresponds to the logic level '1' (Table 2) due to the constructive interference at the T junction ( Figure 6). The performance of the designed AND gate is shown in Table 2.
When both input I 1 = I 2 = 0, the transmission is low, and the gate assumes at a logic state '0'. With only one input available (I 1 = 1 and I 2 = 0), the output transmission (O 3 ) is in the logic state '0'. With both the inputs in the ON state (I 1 = I 2 = 1), the output port O 3 will receive 0.69 normalised intensity due to constructive interference, which depicts the logic state '1'. The contrast ratio for AND gate is 4.9 dB.
There are also outputs O 1 and O 2 that have one-to-one mapping with inputs I 1 and I 2, having the CR of 7.6 dB.
The simulation result for the AND gate is shown in Figure 7. With input I 1 in the ON state and I 2 OFF, it is seen that there is no output at O 2 (Figure 7a). The transmission at output O 1 (Figure 7a) is sufficiently high to be in the logic state '1'. The AND gate output port O 3 (I 1 ·I 2 ), and the intensity at the output is low corresponding to the logic state '0'. Similarly, with only I 2 = 1, I 1 = 0 input, there is output available at O 2 (logic state '1'). For the outputs O 1 and O 3 , the transmission at the output is low corresponding to the logic state '0', which is also shown in Table 3. With both the inputs I 1 and I 2 available, as shown in Figure 7c, the outputs O 1 , O 2 , and O 3 are in the logic state '1'. The transmission at the output O 3 is sufficiently high due to the constructive interference at the T junction and assumption at the logic state '1'.

| Design of XOR gate
The layout of the XOR gate is shown in Figure 8. Port A and Port B are considered as the input port, and Port 3 is considered as the output port. At the junction of each inputs, there are three rods r 3 with ratio r/a = 0.04. These rods help to control the transmission of the light towards the output so as to achieve an optimised design for a high CR. The XOR gate is based on the principle of destructive interference.
With phase difference and path differences (2n + 1)π and (2n + 1) λ/2, respectively (where λ is the free space wavelength of the light and n is a +ve integer), the destructive interference occurs.When both inputs are in the same phase initially, the phase of one of the inputs can be varied by using a phase shifter or by the variation of length of the arms (input

-
to the junction of XOR gate). In this simulation, two arms of the XOR gate have different arm lengths, which introduced path difference for input signals. The proposed XOR gate designed with a lattice constant of 670 nm for the designed crystal and the light wavelength of 1550 nm for the simulation. So, the ratio of wavelength to the lattice constant (a) is = 2.313.
When both the inputs are at the same phase, introducing a path difference in the order of n 2 a; 3n 2 a; 5n 2 a; …, it gives destructive interference at the junction. In this XOR design, the arm length of both inputs is taken 8a and 13.7835a (8a + 5n 2 a), correspondingly. For the XOR gate, one arm is 8 � a path length and the other arm is � 8a þ 5n 2 a � which is 13.7835a or 14a path length. It will introduce a phase difference of 180°between the two input arms. The performance of the designed XOR gate is shown in Table 3. It is observed that when both the inputs are available, there is negligible transmission at the output. When only one input is present, either input A or input B, only then the normalised transmission at the output port achieves the logic state '1'. The contrast ratio of the designed XOR gate is 7.6 dB. The simulation result of the XOR gate is shown in Figure 9. Figure 9a shows simulation results corresponding to the inputs A and B equal to 1; there is destructive interference at the junction and negligible transmission available at the output (logic state '0'). With only one input present (A for Figure 9b and B for Figure 9c), there is sufficient transmission at the output port shown at the logic state '1'.

| Design of all-optical Toffoli gate
The proposed Toffoli gate is an all-optical reversible logic with three inputs and three outputs. All the inputs are assumed to have the same phase at the input, which is only possible if they are drawn from the same source. The schematic layout to implement the Toffoli logic gate operation is already stated in Figure 1. There are two PSs, an AND gate and an XOR gate have been used for the implementation of the Toffoli gate. The design and layout of the Toffoli gate are shown in Figure 10. The proposed Toffoli gate has three inputs (I 1 , I 2 , and I 3 ) and three outputs (O 1 , O 2 , and O 3 ) along with two junctions J 1 and J 2 . The outputs O 1 and O 2 have one-to-one mapping with I 1 and I 2 . For the third output O 3 , the AND-ed output of I 1 and I 2 is XOR-ed with the input I 3 , the operations of which takes place at junctions J 1 -143 and J 2 , respectively. Line defects have been used to design the waveguides in Figure 10. The detailed design of the proposed Toffoli gate is shown in Figure 11. The designed J 1 junction for inputs I 1 and I 2 is having three r 1 rods (ratio r/a = 0.04) that have been optimised for the best performance of the Toffoli operation, and these rods control the light towards the output and also control the transmission to the junction J 1 . The AND operation of I 1 and I 2 takes place at J I . The path lengths for the inputs I 1 and I 2 are the same length of 48a from the input port to the output port O 3 and for I 3 , the path length is 31a from the input to the output port O 3 . Therefore, when both I 1 and I 2 are present at J 1 , it shows constructive interference. The junction J 2 operation shows results corresponding to the XOR gate and destructive interference occurs at this junction. Here the AND-ed output of I 1 and I 2 (I 1 ·I 2 ) is XOR-ed with I 3 . For the input arm of I 3 , there are rods r 4 of ratio r/a 0.05. The other input to the XOR gate has rods r 1 at the junction J 2 . There rods direct light towards the output and also control transmission. Reflection rods r 1 at junction J 2 of ratio r/a0.04 are used. These rods help in reducing reflections at the junction. The arms of junction J 2 have different path lengths so that the inputs become in different phases, and destructive interference takes place at this junction (Table 4, Figure 10). If both the inputs are of the same amplitude and opposite phase, then complete destructive interference happens. If either of the input is having a different amplitude or the phase is not opposite or in both situations, then there will be some transmission (apart from some destructive interference of I 3 with I 1 and I 2 ) at the output of the XOR gates.

F I G U R E 8 Layout and design of XOR gate
In a Toffoli gate, there are three inputs and three outputs, two of the bits as the control bit and the third bit as the target bit. When both these control bits are present, then the target bit complements. When both the control bits are present (I 1 = I 2 = ON), and I 3 is OFF, then due to the constructive interference of I 1 and I 2 at junction J 1 , the output at O 3 has sufficient transmission to be in the logic state '1'. When I 3 is ON and both the control bits I 1 = I 2 = ON, then at junction J 2 (Figure 10), destructive interference takes place; therefore, the transmission intensity at the output O 3 is very less and goes to the logic state '0'. The outputs O 1 and O 2 have one-to-one correspondence with inputs I 1 and I 2 , which are obtained from PS 1 and PS 2 , as shown in Figure 10. The transmission intensity at O 1 and O 2 is sufficient to be at the logic state '1' and is obtained when the inputs I 1   To implement the Toffoli gate, we have selected the rod dimensions and the r/a ratio in such a way that the constructive and destructive interferences occur at the proper places of the junctions to execute the overall Toffoli operation.
The simulation result of theToffoli gate in Figure 12 shows the different logic states of outputs for the various input states. With only I 3 in ON state (Figure 12a), the output O 3 has sufficient transmission at the output (Table 4) and it will be in the ON state.
When I 1 and I 3 are in the ON state (Figure 12b), there is output at O 1 and O 3 . The output O 2 is in the logic state '0'. The transmission of I 1 from junction J 1 is very less (Table 2), whereas I 3 has sufficient transmission intensity (Table 4), so the output O 3 has sufficient transmission to be in the logic state 1. With two inputs I 1 and I 2 in the ON state and I 3 OFF state, then outputs O 1 and O 2 are in the logic state '1'. The inputs I 1 and I 2 undergo AND operation, and due to constructive interference at J 1 junction, transmission intensity of the output O 3 goes to the logic state '1' as shown in Figure 12d. With all the three inputs in the ON state, there is output only at O 1 and O 2 . The output O 3 is complemented as in junction J 2 as destructive interference occurs between I 3 and the AND operated output of I 1 and I 2 (Figure 12c). Hence transmission intensity at output O 3 is less (Table 4), which confirms the logic state.
In Figure 13a,b, the graphs show the variation of the phase of the 1550-nm light wave propagating in the crystal lattice of the lattice constant 670 nm. For every 2.313 � a distance of the lattice, there is a phase variation of 2π.
The time-domain response of the gate is shown in Figure 14. The time-domain response of the Toffoli gate has been obtained at the output port. Response time and bit rate of the proposed Toffoli gate have been calculated from the timeevolving curve as shown in Figure 15. The response time and bit rate of the input signal for the designed Toffoli gate are 0.5333 ps and 1.85 Tbps, respectively. Quantum logic systems are fundamental structures for quantum computing. The proposed Toffoli gate is an implementation using a 2D photonic silicon-air crystal and it is an all-optical universal reversible gate that has much importance in reversible optical processing. The implementation is simple, compact, and no non-linear material has been used for the switching purposes. The wafer size of 50 µm � 50 µm is enough for its implementation. The wavelength used for the simulated results is 1550 nm which is widely used in the C band. The Toffoli gate operates on the principle of constructive and destructive interferences of light with all the inputs initially in the same phase and drawn from a single source of light. The logic is an intensitybased operation and hence can be cascaded with proper fan-out. The simulated result shows the response time of 0.533 ps with the bit rate of 1.85 Tbps (much higher than previous reported work), along with the gate CR of 8.7 and 5.2 dB. In the realisation of the whole scheme, a two-input and three-output AND gate with CR 7.6 and 4.9 dB is also demonstrated. The Toffoli gate can be integrated with optical and photonic nano cavities. In a bulk wafer, such quantum logic gates can be developed by cascading. The present system is designed for a wavelength of 1550 nm.