The suppression of DC-link voltage ﬂuctuations through a source active current feedforward in the active power ﬁlter

An active power ﬁlter (APF), which operates under the power-balance-based scheme (PB scheme), suffers heavier DC-link voltage ﬂuctuation when the loads change suddenly, so that it is apt to be interfered and degraded or even out of stable operation. By analyzing the cause of DC-link voltage ﬂuctuation, this study proposes an improved PB scheme which feeds forward the increment of the fundamental-frequency positive sequence component of the source current. The feed-forward channel is designed by use of the cascaded delayed signal cancellation algorithm and integrated into the conventional PB scheme APF without adding any extra hardware circuit. The current increment fed forward is added into the output of the voltage controller to timely amend the reference current of the current control loop, and thus the active power ﬂow, which caused by loads change, between the APF and its external circuitry can be suppressed. As a result, the DC-link voltage ﬂuctuation is mitigated to allow the APF to better accommodate the abrupt load changes. The conﬁguration of the improved control system is introduced and the stability is analysed. The experiment results demonstrate the effectiveness of the proposed control scheme.


INTRODUCTION
Following the widespread use of various non-linear loads and harmonic-susceptive loads, along with increasing renewable energy generators being put into operation via PWM converters, the power quality issues became significant and urgent [1][2][3][4][5].
The active power filter (APF) is widely used to eliminate harmonics and reactive currents for better power quality of distribution systems [6][7][8][9]. Whether the target harmonic components are needed to be detected from load or source currents leads to two APF control schemes: the harmonic-extraction-based scheme (HE scheme) and the power-balance-based scheme (PB scheme).
In the HE scheme [10][11][12][13][14], the harmonic components must be detected and extracted from load or source currents first, so as to produce the corresponding same amplitude and antiphase harmonic currents and inject them into the point of common coupling (PCC) to maintain the source current as a sinusoid in phase with the grid voltage. Therefore, the HE scheme is always considered as an open-loop system, some factors such as the harmonic sensing and acquiring circuits, the harmonic extraction algorithm and the current control methods will easily affect the performance of the HE-based APF in the practical field. Comparatively, the PB scheme calculates the reference value of the source side current through the DC voltage regulation link and directly controls the source side current, which is regarded as a controlled variable to form a close-loop system from the point of the entire power distribution system and has the advantages of high accuracy and robustness with low requirements of the parameters matching [15][16][17][18].
The PB scheme exhibits a more promising filtering performance. However, the serious oscillation of the DC-link voltage will occur at some sudden load change conditions when an APF employs the existing PB scheme [19]. It decreases the DC voltage utilisation and deteriorates the compensating performance of the APF, and even induces the instability and even damages the APF, limiting the application of APFs in occasions of frequent load changes such as traction motor, beam-pumping unit and so forth. Therefore, how to keep the oscillation of the DC-link voltage within a reasonable range is vital for implementation of the PB scheme in an APF.
There have been some reports regarding to improve the APF performance via regulating its DC-link voltage [19][20][21][22][23][24][25][26][27][28]. Literature [20] suggests suppressing the DC-link voltage oscillation in transient states by controlling the energy flowing into the DC capacitor to be zero in one source cycle. Afterwards, a more accurate 7-step compensator had been presented in [21] to maintain the mean active-power flowing into or out of the DC capacitor at zero every 1/(k -1) source cycle. Based on this, Tomoyuki et al. modified the voltage feedback reference utilising the calculated value of the theoretical stored energy ripple [22]. Considering the impact induced by the third-order harmonic current compensation, an additional fundamental current compensating scheme was utilised in [23] to suppress DC-link voltage impulse. In order to enhance the dynamic performance of the APF under load variation condition, a controller based on online trained recurrent probabilistic fuzzy neural network with an asymmetric membership function (RPFNN-AMF) had been developed to substitute for the conventional proportional-integral (PI) controller in [24]. Additionally, some non-linear and adaptive control strategies were studied [25][26][27]. However, these approaches are only suitable for the HE scheme APF and not for the PB scheme APF.
In the studies of the PB scheme APF, a modified one cycle control scheme was proposed in [15] to distinguish harmonic components from reactive components of load currents and an advanced control strategy with the conventional PI and vector PI controller was proposed in [30] to enhance the compensation performance. However, the DC-link voltage regulation performance of the APF was still poor. To overcome the DClink voltage fluctuation of the PB scheme APF, a feed-forward method has been used, in which the fundamental component is filtered out from the load current and fed forward to improve the dynamic speed of responding to load change [18]. Undoubtedly, it is an effective restraint method against the DC-link voltage fluctuation, but requiring an additional set of sensors to measure the load current undermines the cost-saving advantage of the PB scheme APF. Meanwhile, more complex algorithms are needed to separate the active power component from the load current. A hybrid control strategy termed as dual sliding mode (DSM) PI was proposed in [19] to regulate the DC-link voltage of the APF with PB scheme. It employs a sliding mode scheme to improve the dynamic response via a high gain for the large error and a low constant gain for the steady-state error to assure the stability. It is, however, difficult to determine the design criteria and the sliding surface in practical application. Furthermore, the five-level packed U-cell inverter with the PB scheme was utilised in [29] to improve the performance of DC-link voltage from the perspective of topology. On the basis of analysing the relationships of the source current, the APF current and the DC-link voltage fluctuation, this study introduces a source current feed-forward channel into the conventional PB scheme to mitigate the DC-link voltage fluctuation. By feeding the increment of the source active current forward and adding it to the output of the voltage control loop (VCL) to amend the reference current of the current control loop (CCL), the proposed improved PB scheme finally managed to prevent the active-power from flowing into or out of the APF. In this study, the cascaded delayed signal cancellation (CDSC) operator has been used to design the feed-forward channel to extract control signals from the source current effectively. The proposed method can be developed without adding any extra hardware circuit and can share the same algorithm (i.e. CDSC) with PLL, thus it is easier to be integrated into the existing PB scheme based APF.
The features of the existing relevant schemes are summarised in Table 1 for easier comparison. It can be seen from Table 1 that the proposed method requires less sensors and can eliminate the DC-link voltage fluctuation of the PB scheme to achieve satisfactory harmonics compensation performance by simpler computation.
The rest of this study is organised as follows. The proposed method of the source active current feed-forward is derived based on the analysis of the cause of DC-link voltage fluctuation in Section 2. The implementation of the proposed method is introduced in Section 3, including the configuration of DC-link voltage and current regulators, the design of newly added feed-forward link and the stability analysis of the improved PB scheme. Experiments have been conducted to compare the performances of the conventional and improved PB schemes in Section 4. Section 5 gives a conclusion and Section 6 gives the acknowledgements.

2.1
The APF configuration and the cause of DC-link voltage fluctuation As observed from Figure 1 that the APF utilises the double close loop structure: • The inner CCL for the supply current regulation.
• The outer VCL for the DC-link voltage regulation.
Only three kinds of electric variables (e s , i s and u dc ) need to be detected for the PB scheme control implementation. e s is sent to the phase-locked loop (PLL) to provide the s ph , which tracks the real-time phase of the grid voltage. u dc is fed to the The control block diagram of the conventional PB scheme outer loop to compare with U dc first, and then the compared result Δu dc turns into the voltage regulator (VR) to generate the desired I sref , which multiplies s ph to get i sref . Finally, i s is directly fed back to track its reference i sref , and the error signal Δi s is fed to current regulator (CR) to produce compensating signal. It is thus obvious that an APF with the PB scheme not only saves sensors but also avoids designing the complicated harmonics extraction link, and this also makes the CR computation more efficient relatively. However, a defect of heavy DC-link voltage fluctuation would begin to surface when this control scheme faces abrupt load changes.
Why does the PB scheme induce a poor performance under the severe load variations? How to speed up the dynamic response of the source current to the load change and reserve excellent steady state filtering performance of the APF at the same time? To solve these problems, this study turns to the control block diagram of the conventional PB scheme shown in Figure 2 to find the factors in slowing down the speed of response to abrupt load changes.
As shown in Figure 2, the sudden change of i l will certainly lead to a corresponding change of i s first, but this incipient change of i s will be suppressed swiftly by the CCL because its reference, i sref,αβ , still remains unchanged. However, due to the system need of maintaining a power balance, the power difference between the source and the load has to be supplemented instantly by the APF current i c that comes from charging or discharging the DC-capacitor, and this will make for a DC-link voltage fluctuation, which is also the only variable to reflect the active-power change of the system according to the PB scheme. Subsequently, after the time-consuming filtering and regulating process of the VCL, the VR generates the updated I sref with the changed u dc , and then new value of i sref,αβ is obtained by modulating I sref with s ph,αβ , and thus the updated i s can finally be obtained, via the CCL, to fit the changed load and recover the value of DC-link voltage.
From the above adjustment process after the load changes, it can be discerned that the u dc fluctuation cannot be eliminated completely because the power imbalance originated from the load change has not been sensed by the control system until it gave rise to variation of u dc . Furthermore, the VCL has only a narrow frequency band in general to prevent the DC-link voltage ripple from entering the CCL, which also further prolongs the update duration of i sref,αβ and aggravate the fluctuation of u dc .

The solution to suppress the DC-link voltage fluctuation
According to the aforementioned analysis, in the transient process, a part of active-power which should have been supplied directly to the load from the source, now with interventions from the APF controller, has to be buffered by the APF before being provided to the load. This is exactly the operating principle of the PB scheme as well as the intrinsic reason of u dc fluctuation. Therefore, trying to speed up the update speed of i sref,αβ to keep up with the changed i l could be the fundamental approach to lessen the exchange capacity of instantaneous active power between the APF and its external circuitry to suppress the excessive u dc fluctuation. Improving the dynamic performance of the VCL would broaden its frequency band and leak some voltage ripples into CCL, which would degrade the harmonics compensation performance and even lead to an instability of the whole control system. Taking the active component of i l as a feed-forward signal and adding it to the initial value of i sref,αβ could help acquiring new reference current more quickly [18], however, additional sensors for load currents measurement would not only increase cost but also make the system more complicated.
Considering the relationship between i s and i l in the PB scheme based APF, the fundamental-frequency active component (FFAC) increment of source current, Δi sp , is an appropriate variable as a feed-forward signal to modify the current reference of the CCL.
From Figure 1, there is When the system goes into steady state, currents i s , i c , i l meet following expressions: where i sp is the FFAC of source current, and i lp , i lh are the FFAC and other components of the load current respectively. i p is the dissipating current of APF itself. From Equations (1) and (2), Equation (3) can be obtained as After the load changed to i ′ l as i ′ l = i l + Δi l = i l + Δi lp + Δi lh (4) where Δi lp , Δi lh and Δi p are the increments of i lp , i lh and i p respectively. The corresponding active power current variation is the increment of i sp , that is From Equation (6), Δi sp represents the total active power current demand of the whole APF system caused by the load change. Therefore, it is more reasonable to use Δi sp instead of Δi lp as a feed-forward signal to help updating the reference input of CCL more quickly.
Moreover, according to the PB scheme, i s is constantly controlled to track i sp by the close loop control system, so its fundamental frequency positive sequence (FFPS) component is automatically equal to i sp when the system reaches a dynamic balance. They both have the same phase with the grid voltage, that is, the output phase of the PLL. Thus, only the amplitude increment of FFPS component is needed to be directly added up to the output of the VR as shown in Figure 3. Figure 3 shows the modified control system structure of the proposed strategy for the PB scheme APF. A feed-forward channel made up of the CDSC filter and the amplitude increment operator (AIO) is added to the conventional PB scheme. The CDSC filter is employed to extract the FFPS component, i sp,αβ , from i s . Then, the amplitude of i sp,αβ and its increment for every interval Δt, denoted by ΔI sp , are figured out by the AIO and sent to merge with I sref to form the modified amplitude of the current reference, I ′ sref , which can be expressed as The updated reference input of CCL is eventually gained as

IMPLEMENTATION OF THE PROPOSED SCHEME
From Figure 3, it is demonstrated that only a feed-forward branch is to be added and nothing else of the conventional control system of the PB scheme APF needs to be changed in the proposed strategy. So, classical control methods such as PI control and proportional-resonant (PR) control are still suitable for the VR and CR. The configuration of relevant controllers will be presented below. The crucial performance of the feed-forward channel is its rapidity. In order to shorten the signal processing time, the CDSC algorithm was designed to extract the FFPS current from i s in the study.

Configuration of DC-link voltage regulator and current regulator
In this study, the control model has been established on the basis of instantaneous energy balance principle [37]. A PI controller has been employed as the VR, whose transfer function G VR (s) is where k VP affects response speed and stability of VR, and k VI is related to static errors and dynamic performance of VR.
According to the internal model principle, a PR controller in a stationary reference frame is able to compensate the target harmonics without steady-state tracking errors [38]. In order to avoid the instability derived from an infinite gain and to improve the adaptability to frequency jitters, a quasi-PR controller has been applied here, combining with an integral unit, to form the CR which transfer function G CR (s) is expressed as C⋅ k CRn s s 2 + C s + (n ) 2 (10) In Equation (10), k CP and k CI have the similar effects on CR as k VP and k VI have on VR. The value of resonant coefficient k CRn affects system immunity and actual effect of compensation for the target harmonics (nω), and the cutoff angle frequency C can change the bandwidth around nω. In this study, k CP and k CRn were adjusted to meet requirements of stability, dynamic and steady-state performance, and C was selected to put up with frequency jitter from 49.5 to 50.5 Hz. The specific parameters of the VR and CR are shown in Table 2.

Design of the CDSC-filter for the FFPS component
The CDSC filter is made up of several delayed signal cancellation (DSC) operators. For ease of presentation of the DSC operator, the three-phase source current i s = [ i sa i sb i sc ] T is first  (11) whereT is Clarke transformation matrix. When i s is asymmetric and distorted, i s, (t ) can be decomposed as a series harmonics ∑ i h s, (t ) where h is the harmonic order. The DSC operator distinguishes the targeted harmonic component from multitudinous harmonic components in the distorted current signal by the law that different harmonics rotate over different angles in the same duration [31][32][33][34][35][36]. According to references [32][33], the structure diagram of the generalised DSC operator can be given as in Figure 4 and the corresponding equation can be expressed as: where R( r ), T and m are the rotation matrix, the fundamental period of source current and the delay factor, respectively, and R( r ) is where r = 2 h * ∕m is the controllable rotation angle determined by m and the targeted harmonic order h * . By choosing parameters m and h * suitably, a generalised DSC operator can be configured to retain the desired frequency component and eliminate or attenuate other frequency components as well. Furthermore, a specified harmonic can be eliminated by multiple DSC operators with different m and h * , and in turn, a given DSC operator under a pair of m and h * can eliminate a series of harmonics. Therefore, it is possible to construct a CDSC filter with the minimum number of optimal DSC operators to extract FFPS component, i sp,αβ , from distorted source current.
In this study, aiming at an APF working in the typical threephase three-wire supply system with the rated frequency of 50 Hz and the asymmetrical harmonic source load, DSC 1 2 , DSC 1 4 , DSC 1 8 , DSC 1 16 and DSC 1 32 are selected and the overall CDSC filter can be constituted as shown in Figure 5. The amplitude-frequency characteristics of each DSC operator and overall CDSC filter are given in Figure 6, which shows obviously that the FFPS current can be extracted exactly whereas almost all other frequency components had been removed.

Stability analysis of the improved PB scheme
According to Figure 3, the closed-loop transfer function of the source current controller can be expressed as where G d (s) = 1 1+1.5⋅T s ⋅s is used to characterise the delay of sampling and filtering, and T s is the sampling period; G L (s) = 1 s⋅L+R , in which L = L 1 +L 2 and R are the equivalent inductance and internal resistance of the output filter respectively.
Bode diagram of the G CCT (s) is plotted in Figure 7.
where G dc (s) = k p s⋅C dc , in which k p is the equivalent gain between the APF current and the DC-link capacitor current. Figure 8 shows the bode diagram of the G VCL (s) with the proposed control scheme. From Figure 8, it can be seen that G VCL (s) maintain unity gain at low frequency range up to 10 Hz and the designed current regulators do not cause the magnitude of G VCL (s) going higher than 0 dB. Figure 9 shows the pole-zero map of the G VCL (s) with the proposed control scheme. From Figure 9, it can be seen that all poles of the voltage closed-loop transfer function G VCL (s) remain to the left of the imaginary axis, which means that the proposed control system is stable.
Besides, considering the influence of the feed-forward link on the system, the transfer function of DC-link voltage and load disturbance is obtained as where is the equivalent transfer function of designed feed-forward link and the delay brought by the CDSC filter is about 31 32 T ≈ 0.97T. It can be seen from Equation (16) that the feed-forward link does not affect the denominator of the closed-loop transfer function of the system and does not influence the stability of the whole system as well.

EXPERIMENTAL VERIFICATION
A series of simulations and experiments were carried out based on the three-phase APF depicted in Figure 1 and had similar results, so only experimental results are given here. The VSC consisted of three Infineon IGBT modules (FF150R12RT4) driven by the Concept 2SC0108Ts which received control signals from digital signal processor chip TMS320F28377, by which the algorithms of the two different schemes were implemented. The LCL output filter was designed according to

FIGURE 10
The simplified main circuit diagram

FIGURE 11
Experimental platform [39][40][41]. The loads are composed of a resistive load, an inductive load and a three-phase diode rectifier with resistors R 1 (called case 1) or R 1 in parallel with R 2 (called case 2) in DC side. The supply voltage is generated by a 12 kVA programmable AC source supply (Chroma 61511). The simplified main circuit diagram and experimental platform appear in Figures 10 and 11. The detailed parameters are given in Table 3.

4.1
The steady state performance Figure 12 shows the steady state waveforms and harmonic spectrums of phase A source current, i sa , before the APF put into operation. Obviously, the time domain waveforms of i sa distorted seriously and THD values of i sa were 23.89% (in case 1) and 16.03% (in case 2). It can be seen intuitively from Figures 13 and 14 that the waveforms of i sa had been close to a sinusoid after having been compensated by the APF with either the conventional or the improved PB scheme. The THD values of i sa were reduced to

4.2
The DC-link voltage regulating performance Figure 15 presents the experiment waveforms of DC-link voltage, phase A load current, i la , under the two different schemes. In Figure 15(a), with the conventional PB scheme, u dc dropped FIGURE 13 Experimental waveforms and frequency spectrums of phase A source current with the conventional PB scheme APF

FIGURE 14
Experimental waveforms and frequency spectrums of phase A source current with the improved PB scheme APF down to 180.5 V and went upward to 219.4 V, respectively, with the rectifier load shifting from case 1 to case 2 and back to case 1 again, and took about 2.2 s to restore to the set value of 200 V. The control effect of the improved PB scheme is shown in Figure 15

4.3
The compensation performance and the adaptability to the load fluctuation Figure 16 displays the waveforms of u dc , i sa , i la , phase A filter current i ca and frequency spectrum of i sa under two different schemes. Figures 16(a) and (c) give the entire waveforms of the conventional PB scheme during the load shifting between case 1 and case 2, and the zoom-in waveforms from 1 s to 1.2 s after the load had switched, respectively, while Figures 16(b) and (d) give the corresponding waveforms of the improved PB scheme. It can be observed from the waveforms of i sa and its frequency spectrums in Figures 16(c) and (d) that there were a large number of harmonic components superimposing on i sa with the conventional PB scheme, but a good sine wave had been obtained by the improved PB scheme due to its shorter transient process.
Further, to compare the immunities to the load sudden change between the two schemes, the experiments had been redone with replacing value of R 2 with 5 ohms. As in Figure 17(a), the APF with the conventional PB scheme was not able to limit the DC-link voltage to a manageable range and quit running owing to overvoltage protection. But with the improved PB scheme, the APF controlled the DC-link voltage back to the set value effectively and maintained normal operations under the same conditions, as shown in Figure 17(b).

CONCLUSION
Existing PB scheme based APFs have the drawback of DClink voltage fluctuation caused by sudden load change, which degrades their compensation performances, threatens their operation safety and limits their application scenarios. The reason for the DC-link voltage fluctuation is that the DC-capacitor buffered some of the active power while the load changed. This study proposed an improved PB scheme, in which a feedforward link had been added to prevent the active power from being buffered. The CDSC filter that had been selected and designed to draw out the FFPS active components from the source current, combined with the amplitude increment operator to form the feed-forward link. Simulations and experiments

FIGURE 16
The waveforms of u dc , i sa , i la , phase A compensation current and the frequency spectrums of i sa under two schemes. (a) The waveforms of the entire process under the conventional PB scheme, (b) the waveforms of the entire process under the improved PB scheme, (c) The time-axis zoom-in waveforms of the selected period in Figure 16(a), (d) the time axis zoom-in waveforms of the selected period in Figure 16(b)

FIGURE 17
The performance comparison between the two schemes when the DC load switched from 44 to 4.5 ohms (a) the conventional PB scheme, (b) the improved PB scheme are conducted to validate the proposed scheme and relevant designs. Confirmed by Figures 12-17, the proposed scheme has significantly weakened the DC-link voltage fluctuation and improved the adaptability to sudden load changes along with a certain extent improvement in the compensation performance. The scheme is not only easy to implement but also cost saving because it only needs to add the feed-forward correlation algorithm to the original algorithm without adding any hardware.